16-bit microprocessors

16-bit microprocessors

1. 16-bit microprocessors
Zahra Sadeghi

2. 68000 architecture

3. 68000 architecture
16 bit external word length :16 data pin

4. Register organization
Register:32 bits 8 data registers:D0-D7
7 address registers:A0-A6
Data registers: accumulator + counter
Data and address register:index register
Addressable space=2^24~16MB


Data registers address registers

5. A7:proccessor stack pointer



Sr: processor status register
Pc: program counter

6. Instruction word format

7. instructions

One operand and two operand
two operand: OP src,dst
Ex: add #9,d3
dst [src]+[dst]
Source op or destination op must be in Dn
Second op:register or memory location

8. Addressing modes
Source is data register direct
General form – ADD D1,D3
Both source and destination are data register direct.
Source is address register direct
General form – ADD A1,D3
Source is address register direct; destination is data
register direct.
Source is immediate
General form – ADD #7,D3 (ADDI #7,D3 )
Source is immediate; destination is data register
direct.

9. Absolute modes of addressing
LONG :address:32 bits
Short :address :16 bit
General form - ADD LABEL,D3
Source is absolute (an address specified by a symbol)
Autoincrement
General form - ADD (A0)+,D3
Source is address register indirect with postincrement.
After access to operand,An is incremented(1,2,4)
Aoutodecrement
General form - ADD -(A0),D3
Source is address register indirect with predecrement.

10. Assembly language
Assembler instruction must indicate the desired size
Size indicator: L: long word; W: word; B: byte
ADD #20,D1 ~ ADD.W #20,D1
numbers : default Decimal
prefix $ Hexadecimal
prefix % Binary
Alphanumeric characters must be between single quot
ORG: starting address of a block of instruction or data
EQU: equates names with numerical values
DC: Define Constant
ORG 100
PLACE DC.B 23.$4F,%10110101
DS: Define Storage
ARRAY DS.L 200

11. Logic instructions

NAME SIZE ADDRESSING MODE
AND B,W,L s =Dn ; d = Dn
ANDI B,W,L s = Immed
EOR B,W,L s = Dn
EORI B,W,L s = Immed
OR B,W,L s=Dn,Sr=Dn
NOT
NEG

12. Condition code flags


N: (Negative) set to 1 when result is negative
Z: (Zero)
V: (oVerflow)
C: (Carry)
X: (eXtended) special for 68000 :is set to 1 the same
way as the c flag but is not affected by as many
instructions
C and X are set 1 to signify borrow signal
they depend on the carry_out from bit positions
7,15,31 for byte , word , long word

T S I X N Z V C

13. Conditional branching
The Bcc instructions
Dependent upon the value of a bit in the Status
Register.







Note: You don't test the X bit.

14. Branch instruction)conditional)
Branch address=[updated PC]+ offset
Offset: the distance from the word that follows the branch
instruction op_code word
8 bit offset : 8 bit in op_code :+127…-128 bytes
16 bit offset :+32… -32 k

1000 LOOP ADD.W (A2)+,D0
1002 SUB.W #1,D1
1004 BGT LOOP
1006





Op_code offset
Op_code word
Op_code word
Op code -6

15. DBcc Dn,label (cc=condition)

16. DBcc instruction

more powerfull
Sequence of instructions
Providing convenient means for loop control
Counter register= Dn

1.If condition specified by cc then label
2.Else Decrement Dn
3.if Dn== -1 then next instruction
4.If Dn!= -1 then branch at label

DBcc D3,LOOP Bcc NEXT
Next instruction SUBQ #1,D3
BGE LOOP
NEXT next instruction

17. Unconditional branching
BRA instruction BRA <label>
Program control passes directly to the instruction located at label.
The size of the jump : -32768 to +32767.
Ex: BRA LOOP
JMP instruction JMP <ea>
Program controls jumps to the specified address.
no restriction on the size of the jump
JMP AGAIN ;absolute long addressing mode
JMP (A2) ;address register indirect
;addressing mode

18. subroutine

branch to subroutine:BSR
push the address of the next instruction on the 68000
stack pointed at by A7, i.e. they push the long word
address of the next instruction after the call onto the
stack.

Return from subroutine: RTS
pops a long word, an address, off the stack (in A7) and
loads the PC with that address

19. BSR <label>, label :with no more than a 16-bit
signed offset
JSR <ea>, <ea> : memory addressing mode,
i.e. <ea> cannot be a data or address register.
JSR SUB ;jumps to a subroutine anywhere in memory
BSR SUB ;jumps to a subroutine within a limited addressing range

RTS
JMP (SP)+

20. How to pass parameters to subroutines
Using data registers - call by value (uses actual
data values) - put arguments in data registers
before JSR
Using address registers - call by reference
(uses actual data values) - put the addresses of
the arguments in address registers before JSR
Using program memory
arguments listed in a table or array, pass base
address of table to subroutine via an address
register
Using the stack (the preferred method) -

21. Stack
A7:points to processor stack
Supervisor mode: system software
processor can execute all machine instructions
User mode: application programs
privileged instructions cannot be executed

A7

Bit S determines which mode is active
begin in high memory and are pushed toward low
memory
user stack pointer
Supervisor stack pointer

22. stack
MOVEM:saves or restores multiple registers
Push: MOVEM <source>,-(SP)
Pop: MOVEM (SP)+,<destination>
LINK Ai,#disp: Ai= frame pointer
1.Pushes the contents of Ai onto stack
2.Copies A7 into Ai
3.Adds displacement to value to A7(top of
stack)
UNLK: reverses the actions of link:
1.Loads A7 from Ai
2.Pops Ai off the stack and back into Ai

23. …
MOVE.L P2,-(A7)
MOVE.L P1,-(A7)
BSR SUB1
2014 MOVE.L (A7),RES [D0]
ADDI.L #8,A7 [D1]
… [D2]
2100 SUB1 LINK A6,#0 [A0]
MOVEM.L D0-D2/A0,A7 [A6]
MOVEA.L 8(A6),A0 2014
… P1
UNLK A6 P2
RTS

24. 8086 architecture

25. 8086 architecture
Addressing pins:20;
memory addressing capacity=2^20~1MB
data pins=16
Use of pins:both address and datum cannot be
sent to bus at the same time
One supply voltage of +5V;
One clock phase up to 5MHz
Two other versions of 8086 8086-1(10 MHz)
8086-2(8 MHz)

26. Registers
Control unit and working registers:
1.Data group: set of arithmetic instruction
2.Pointer group:base and index registers
3.Segment group
Data group consists of :Ax,Bx,Cx,Dx
Bx:Base register in addressing calculations
Cx: is used as an counter
Dx: hold I/O address

27. Pointer group:BP,SP,SI,DI,IP
RET:
pops the IP value from the stack into IP.
increments the sp by 2.
CALL:
pushes the IP into stack
BP SI ,DI
push BP cld
mov BP,SP mov cx,50
… lea di,str2
…. Lea si,str1
pop BP rep movsb
ret

28. segment group:CS,SS,DS,ES registers
Offset : in assembler language
Effective address: in machine language :16bits
Phisical address:20 bits :on the address bus
Registers for addressing:BX,IP,SP,BP,SI,DI:16 bit
Effective address
or offset
4 bits
Segment address

Physical address
16 bits
20 bits
16bits

29. segments
Each 64k capacity long
Beginning at a 16 byte
Memory capacity:1M
Segments can be overlapped:to better utilize memory
program
code segment

another segment

30. Flags
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



0101 0100 0011 1001
+ 0100 0101 0110 1010
1001 1001 1010 0011

SF=1; ZF=0 ;PF=1 ; CF=0 ; AF=1 ; OF= 1
of df if tf sf zf af pf cf

31. Addressing modes
Instruction instruction memory instruction register


a) Immediate b) direct c) register
Mov ax,50 mov ax,place mov ax,bx

Instruction register memory


d) register indirect EA= BX
DI,SI
mov bx,offset place
mov ax,[bx]
datum
EA datum register datum
register
EA datum

32. Addressing modes
instruction
memory
EA
register


mov al,list+1
e) register relative

instruction register
index:si,di
base:bp,bx
register

f) based index
mov al,[bx+si]
address
+
datum
register displacement
Base reg. displacement
Base address
+ datum
index

33. g)relative base address








BX SI
mov al,[bx+si+3] EA= BP + DI + displacement


index
Base addr
+
Base reg Index reg displacement
datum

34. Branch instruction
Machine code format:
8 bit signed(2’s complement)
D8:displacement relative to the address of next instruction in sequence
Effective branch address=D8+IP

Language conditional branch instructin:
operation operand
jnz l1
Negative D8:backward branch from the next instruction
Positive D8 :forward

Distance between the address and next instruction:
-128 …+127

Op_code D8

35. Example:
0050 AGAIN: INC CX
0052 ADD AX,[BX]
0054 JNZ AGAIN
0056 NEXT: MOV RESULT,CX

0050 effective branch address
- 0056 (IP)when jnz branch decision is made
-6

36. عبانم:
COMPUTER ORGANIZATIONB
by:Carl Hamacher,Zvonko Vranesic,Safwat Zaky
STRUCTURED COMPUTER ORGANIZATION
by: A.S Tornenbaum
THE ART OF ASSEMBLY LANGUAGE
PROGRAMMING
by:James F.Peters, Reston Pubco
The 80x86 IBM PC and compatible computrs
by: Muhammad Ali Mazidi , Janice Gillispie Mazidi
www.cwru.edu
www.old_computers.com
www.library.nci.com
www.informit.com
www.peyuide.com

37. Segments devide memory into overlapping segments
Each 64k capacity long
Beginning at a 16 byte 00000
Memory capacity:1M 00010
00020

.
.

10000
10010
10020

38. Name addressing symbol addressing function
Immediate #value operand=value
Absolute short value EA=sign extended w value
Absolute long value EA=value
Register Rn EA=Rn
Register indirect (An) EA=[An]
Autoincrement (An)+ EA=[An]
Auodecrement (An)- EA=[An]
Indexed basic w value (An) EA=w value +[An]
Indexed full w value (An,Rk,s) EA=B value +[An]+[Rk]
relative basic w value or label EA=w value +[pc]
Relative full B value (pc,Rk,s) EA=B value +[pc]+[Rk]

39. Logic instructions

Determine if the pattern in positions b18
through b14 is 11001:

AND.L #$7C000,D1
CMPI.L #$64000,D1
BEQ YES
MOVEQ source = an 8-bit immediate
constant
destination = data register