7-B-SysVerilog_DataTypes.pptx _

it speaks about the data types in verilog and various propoerties of diferent types of verilog

1. System Verilog Data Types (Chapter 2 )

2. Data Types in Verilog-95 9/22/2023 Verification with System Verilog 2 ‘ Reg ’ and ‘net’ They all hold 4-state values (0, 1, Z and X) They can be single bit, multibit ( eg : vectors) , signed 32 bit( eg : integer ), unsigned 64 bit ( eg : time ), signed 64 bit floating point ( eg : real ). All are static => retain values throughout simulation. Can’t hold local variables

3. New Data Types in System verilog 9/22/2023 Verification with System Verilog 3

4. ‘Logic’ data type 9/22/2023 Verification with System Verilog 4 One data type for both combinational and sequential.. Avoid headache of deciding between ‘ reg ’ or ‘net’. Can be driven by continuous assignments, gates, modules and for storing variables. Limitation Can’t be driven by multiple drivers ( eg : modeling a bus). Need to use ‘wire’ for multiple drivers

5. ‘2 state’ data types 9/22/2023 Verification with System Verilog 5 In V erilog, all data types are 4-states. System verilog introduces ‘ two-state ’ data types (hold only ‘0’ or ‘1’). We use them where ‘x’ and ‘z’ not needed eg : test benches, loop variables, Make the simulators more efficient and also reduces memory storage requirements. Ans : No.. One is 2 state and other is 4 state. Also, one is signed and other is unsigned.. Hence range of data stored is different. *Note 1) System verilog stores each element as a long-word (32 bit). Longint is stored in 2 long words. Four state type like logic is also stored as 2-long words (64 bits) 2) ‘ int ’ is a 2 state data type while ‘integer’ is a 4 state data type. Ques : Can we use ‘byte’ and logic[7:0] interchangably ?

6. ‘2 state’ data types: warning 9/22/2023 Verification with System Verilog 6 Be careful while connecting 2 state variables to outputs of DUT.. If pin drives ‘X’ or ‘Z’, it is converted to two state values (either 0 or 1). You will be working with incorrect data.. Hence if you have this connection, use ‘$ isunknown ’ command to check if any unknown (x or z for 2 state variable) output is being got..

7. Arrays Fixed Size Arrays & Dynamic Arrays ( Verilog has only fixed size arrays) 9/22/2023 Verification with System Verilog 7

8. Fixed Size Arrays 9/22/2023 Verification with System Verilog 8 Lower bound is assumed to be zero if not mentioned (just like C ). In V erilog we need to explicitly provide upper and lower bounds. Will this work in Verilog? Multi-dimensional arrays

9. Initializing Arrays 9/22/2023 Verification with System Verilog 9

10. Array Operations (for, foreach ) 9/22/2023 Verification with System Verilog 10

11. Array Operations (multi-dimensional) 9/22/2023 Verification with System Verilog 11 Note the syntax :md[ I,j ]

12. Copy and Compare 9/22/2023 Verification with System Verilog 12 Note: we can’t perform aggregate arithmetic operations like addition etc on arrays. Need to use loops

13. Packed and Unpacked arrays 9/22/2023 Verification with System Verilog 13 Each array is only 8 bits long, but by default it is stored in a long word (32 bits) Unpacked Array

14. Packed and Unpacked arrays 9/22/2023 Verification with System Verilog 14 For some data types, we may want to access entire value or a part of it. Eg : 32 bit register, we may want to access as a 32 bit value or as 4 separate bytes. It is treated as both an array and a single value Stored in contiguous locations, no unused space is left. Packed Array

15. Mixing Packed and Unpacked arrays 9/22/2023 Verification with System Verilog 15 For some data types, we may want to access entire value or a part of it. Eg : 32 bit register, we may want to access as a 32 bit value or as 4 separate bytes. It is treated as both an array and a single value Stored in contiguous locations, no unused space is left.

16. Dynamic Arrays 9/22/2023 Verification with System Verilog 16 What if we don’t know the size of the array till run-time. If we allocate too many => waste of memory Create 20 locations and copy old five.

17. Copying between Fixed and Dynamic Arrays 9/22/2023 Verification with System Verilog 17 Fixed array can be copied to a dynamic array as long as both have the same base type ( eg : int , float). Dynamic array can be copied to a fixed array as long as they have same number of elements and the type matches.

18. Queues 9/22/2023 Verification with System Verilog 18 Indexing starts from 0 Note: when a queue is created, some amount of space is allocated so that new elements can be added.. No need to call ‘new’ function repeatedly

19. Associative Arrays 9/22/2023 Verification with System Verilog 19 What if we want to create very large arrays (Gb memory modelling for processors). We may be accessing only a few thousand locations from random points (executable code from particular location, data from somewhere else)… Hence.. Even dynamic arrays initializing is waste of memory locations. Associative memory: can address very large address space but allocates memory only when we write in to it. They can be indexed using any of the supported data types. Only these locations are allocated, rest are free Similar to pointers…. Use * “Tree” data structure is used to store and access the array.

20. Associative Arrays 9/22/2023 Verification with System Verilog 20 Foreach (variable[iterator]) The iterator can be anything, not needed to be defined before. Study about “addressing using strings”. ‘first’ and ‘next’ are functions that modify the index and return a ‘0’ or ‘1’ depending on existence of data in the position

21. Arrays Methods 9/22/2023 Verification with System Verilog 21 These can be used on any unpacked array types (fixed, dynamic, queue, associative) Self study: How to choose storage type based on need (flexibility, speed, memory usage and sorting requirements) Array Reduction Methods Sum, product, or, xor Array locator methods Find, find_index , find_first , find_last , min, max, unique

22. User Defined Types 9/22/2023 Verification with System Verilog 22 Very useful data type: unsigned, 2 state, 32 bit integer. (most values in testbenches are positive.. Hence useful in verification) Not really a new type, just a macro for variable size

23. User Defined Structures 9/22/2023 Verification with System Verilog 23 Creates a single pixel Creates a new type for creating multiple pixels Packed structure.. To save space.. Not use 3 long words ..

24. Enumerated Types 9/22/2023 Verification with System Verilog 24 We create a new enum data type and then define variables based on that. Start from ‘0’ by default. Color is assigned red/blue/green Default values are overridden. Init = 0, decode =2, idle = 3

25. Enumerated Types 9/22/2023 Verification with System Verilog 25 Remember : Enumerated variables are stored as int (2-state). Int are by default initialized to 0. Find out if there is any fault in the following : ‘position’ is initialized to 0. but zero is not a legal vaue of type ordinal_e

26. Enumerated Types 9/22/2023 Verification with System Verilog 26

27. Strings 9/22/2023 Verification with System Verilog 27 Remember : String indexes from 0 -> N-1 No null character at end. Uses dynamic memory. so no worries about running out of space.

28. Tata.. bye bye .. ‘data types’ Kabhi Alvida na kahna .. Hum Lab mein phir milenge !!!!!!!