8085microprocessor-functional block diagram, Arithmetic Logic Unit (ALU), Timing and control Unit, pptx

introduction to microcontroller 8085Instruction and data flow, System timing diagram– interrupts

1. 8085 Microprocessor

2. What is Microprocessor?

3. Microprocessor: A microprocessor- - is a multipurpose, programmable logic device that - reads the binary instructions from a storage device called memory, - accepts binary data as input and processes data according to those instructions and - provides result as output. Microcomputer is one of the microprocessor-based systems.

4. The microprocessor is a semiconductor device consisting of electronic logic circuits. It is capable of performing various computing functions and making decisions to change the sequence of program execution.

5. The microprocessor can be broadly divided into three parts: 1. Arithmetic / Logic unit 2. Registers 3. Control unit Arithmetic / Logic unit (ALU) This is the area of the microprocessor where various computing functions are performed on data. The ALU unit performs such arithmetic operations as addition and subtraction, and logic operations such as AND, OR and EXCLUSIVE OR. Results are stored either in registers or in memory.

6. Registers This area of microprocessor consists of various registers. These registers are primarily used to store data temporarily during the execution of program. Some of the registers are accessible to the user through instructions.   Control unit The control unit provides the necessary timing and control signals to all the operations in the microcomputer. It controls the flow of data between the microprocessor and memory and peripherals.

7. Memory Memory stores binary information such as instructions and data, and provides that information to the microprocessor whenever necessary. To execute programs, the microprocessor reads instructions and data from memory and performs computing operations in its ALU section. Results are either transferred to the output section for display or stored in memory for later use.   Input/Output (I / 0) This section communicates with outside world. I/O devices are also known as peripherals. The input devices are keyboard switches and an analog to digital converter. These devices are used to transfer data from outside world to microprocessor. The output devices are Light emitting diodes (LEDS), cathode ray tube (CRT) or video screen, printer, plotter, magnetic tape or digital to analog converter. These devices transfer data from microprocessor to the outside world. The data can be displayed on CRT or video screen and it can be printed on paper by using printer.

8. System Bus The system bus is a communication path between microprocessor and peripherals. It is a group of wires to carry bits. There are several buses in system.   Primary function of the CPU of a microcomputer: 1. To fetch, decode, and execute program instructions in the proper order. 2. Transfer data to and from memory and to and from I/O section. 3. Responds to external interrupts. 4. provide overall timing and control signals for the entire system. 5. R/W of data into memory so bi-directional bus is required. 6. All processing and data flow is done in the system with MPU chip.

9. Block diagram of ALU: ALU is 8-bit unit It performs arithmetic, logic, rotate operations. It consists of binary adder to perform addition and subtraction by 2’s compliment method. The result is typically stored in accumulator. Accumulator, temporary register and the flag resisters are closely associated with ALU. Temporary register is used to hold the data during arithmetic/logical operation.

10. Block Diagram of A Generic-Microprocessor

11. 1. Arithmetic and Logic unit 2 . Several Registers : Instruction Register, Accumulator, Status Register, Temporary Register, Stack pointer, Data Address Register 3. Program counter 4. Instruction decoder 5. Timing and control section 6. Bus buffers and latches. 7. Internal buses and control lines 8. Several control inputs and outputs. 9.Interrupt control.

12. 1) Address Bus

13. 2) Data Bus

14. 3) Data address Register

15. 4) Arithmetic and Logic unit

16. 5) Accumulator:

17. 6) Instruction Register and Instruction Decoder Instruction Register This is a 8 bit register. The first byte (i.e. 8 bits) of an instruction is stored in this register. 2) Instruction Decoder This unit interprets the contents of instruction register. It determines the exact steps to be followed in executing the entire instruction and directs the control section accordingly.

18. 7) Status Register:

19. 8) Program Counter

20. 9) Stack Pointer

21. 10) Timing and control unit

22. 10) Control Inputs and Outputs

23. 11) Bus Buffers and Latches

24. The time required by the microprocessor to complete an operation of accessing memory or input/output devices  is called machine cycle. One time period of frequency of microprocessor is called t-state. Time required to execute and fetch an entire instruction  is called instruction cycle. It consists: Decode instruction – Decoder interprets the encoded instruction from instruction register. Reading effective address – The address given in instruction is read from main memory and required data is fetched.

25. 12) Machine Cycle The clock circuit generates a two phase non overlapping clock signal ǿ1 and ǿ2. Clock signals are divided into T sates like T1,T2,T3……etc. Collection of T state is called as Machine cycle. The instruction cycle is collection of machine cycles. For example ADD instruction is divided into 3 machine cycles like M1,M2,M3. M1 takes 4 T states, M2 takes 3 T states and M3 takes 2 T states.

26. 13) ADD instruction: Adds the content of accumulator to the content of next byte in memory and leaves the sum in accumulator. During M1, MPU decodes ADD instruction, During M2, MPU reads next byte and During M3 add operation is performed. Machine Cycles and Instruction cycles are not of same length.

27. 8085 Microprocessor Architecture

28. Generally, the 8085 is an 8-bit  microprocessor,  and it was launched by the Intel team in the year of 1976 with the help of NMOS technology. This processor is the updated version of the microprocessor. The configurations of  8085 microprocessor  mainly include data bus-8-bit, address bus-16 bit,  program counter -16-bit, stack pointer-16 bit, registers 8-bit, +5V voltage supply, and operates at 3.2 MHz single segment CLK. The applications of 8085 microprocessor are involved in microwave ovens, washing machines, gadgets, etc. The  features of the 8085 microprocessor  are as below: This microprocessor is an 8-bit device that receives, operates, or outputs 8-bit information in a simultaneous approach. The processor consists of 16-bit and 8-bit address and data lines and so the capacity of the device is 2 16  which is 64KB of memory. What is the 8085 Microprocessor?

29. Features of 8085 μicroprocessor:

30. the architecture of the 8085 microprocessor mainly includes the timing & control unit, arithmetic and logic unit,  decoder,  instruction register, interrupt control, a register array, serial input/output control. the most important part of the microprocessor is the central processing unit.

31. Central Processing Unit (CPU) The Central Processing Unit of any microcomputer is the microprocessor. Hence microprocessor is also known as the heart of the computer. The CPU performs the various activities in response to a set of instructions called a program. Programs are stored in the memory. The CPU reads in data control signals (instructions) through the input ports and executes one instruction at a time. So, generally speaking, a microprocessor is nothing but the CPU . The Intel 8085 CPU is an 8-bit device with a clock speed of 3 - 5 MHZ. It has 80 basic instructions and 246 op-codes. Its clock cycle is 320 ns. The time for the clock cycle of Intel 8085 is 200 ns. The 8085 CPU consists of three major sections, They are: ( i ).Arithmetic and logic unit (ALU) (ii).Registers (iii).Timing and Control unit.

32. Accumulator • Arithmetic and logic Unit • General purpose register • Program counter • Stack pointer • Temporary register • Flags • Instruction register and Decoder • Timing and Control unit • Interrupt control • Serial Input/output control

33. 1. Accumulator

34. 2. ALU (Arithmetic & Logic Unit) • To perform arithmetic operations like Addition & Subtraction • To perform logical operations like • AND • OR • NOT (Complement) The ALU also performs all the complementing, logical AND, logical OR, logical Exclusive OR, incrementing and decrementing, rotate, shift and clear. An ALU is made of many logic gates and adders etc. Accumulator, temporary register and flag register is closely associated with ALU.

35. What are the types of registers in microprocessor?

36. Temporary registers: These registers are used by the ALU to store the data on  temporary basis  and these are not accessed by the programmer. These are of 2 types:   1) Temporary data register – It is an 8-bit register that holds the operand and provides it to the ALU for program execution. Also, the immediate results are stored by the ALU in this register. 2) W and Z register – These registers are also used to hold the temporary values. It is used by the control section of the microprocessor so as to store the data during operations.

37. General purpose Registers 8085 microprocessors contain  6 general purpose registers  that are present inside the microprocessor and  stores 8-bit data  in order to execute a program. These general purpose registers are  B, C, D, E, H and L . These registers can be combined to form pairs – BC, DE and HL in order to execute the 16-bit operation. These are programmable registers, that means these registers are accessed by the programmer to insert and transfer the data by making use of instructions.

38. Special purpose Registers   1.Accumulator (A) It is an 8-bit tri-state register. It is mainly used for arithmetic, logic, load and store operations. It is also used in I/O operations. In most of operations, the result is stored in Accumulator after execution.

39. IR (Instruction Register) is a special purpose register, which is used to receive the 8-bit opcode portion of an instruction. It is not accessible to the programmer. What it means is that there are no instructions by which the programmer can load it with values of his choice. 2. Instruction Register

40. 3. Flag Registers The  Flag register  is a Special Purpose Register. Depending upon the value of result after any arithmetic and logical operation the flag bits become set (1) or reset (0). In 8085 microprocessor, flag register consists of 8 bits and only 5 of them are useful. The 8085 flags are: - Sign flag (S) - Zero flag (Z) - Auxiliary carry flag (AC) - Parity flag (P) - Carry flag (Cy) The respective position of these flag bits in flag register has been show the below figure. The positions marked by “x” are to be considered as don't care bits in the flags register. The user is not required to memorize the positions of these flags in the flags register.

41. Now consider the programmer's view of 8085 contains the flags register has been depicted in the following figure - These individual flags are either set to 1, or reset to 0 depending on the result of execution of the last executed arithmetic or logical instruction. But in a few arithmetic and logical instructions, some or none of these flags are affected. Also there are some arithmetic and logical instructions, flag bits in the flag register will not get affected as well. As example in the execution of DCX and INX instructions, flag bit in flag register will not get affected at all. However, in any data transfer instruction, none of the flags bits in flag register are affected.

42. a) sign flag The S flag is set to 1, when the result thus produced against any logical or arithmetic operations is negative, indicated by MS bit of 8-bit result being 1. It is reset to 0 otherwise if the result is positive, indicated by MS bit of 8-bit result being 0. Thus, the value of S flag is essentially the value of the MS bit of the 8-bit result. Instructions that use the S flag are quite often used in the user programs. After the execution of arithmetic or logical operation, if bit D7 of result is the sign flag is set to 1. This flag is used with sign numbers.

43. This flag is set, when MSB (Most Significant Bit) of the result is 1. Since negative binary numbers are represented in the 8085 CPU in standard two’s complement notation, SF indicates sign of the result. 1-MSB is 1 (negative) 0-MSB is 0 (positive) ( In a digital data bit string, the  MSB  is a bit of the highest digit, and the  LSB  is a bit of the lowest digit. ... For example, 99 in the decimal system is expressed as ( MSB )01100011( LSB ) in the binary system. In this case, the  MSB  is 0 and the  LSB  is 1.)

44. Example 1 : MVI A 30 (load 30H in register A) MVI B 40 (load 40H in register B) SUB B (A = A – B) These set of instructions will set the sign flag to 1 as 30 – 40 is a negative number. Example 2: MVI A 40 (load 40H in register A) MVI B 30 (load 30H in register B) SUB B (A = A – B) These set of instructions will reset the sign flag to 0 as 40 – 30 is a positive number.

45. b) Zero flag After any arithmetical or logical operation if the result is 0 (00)H, the zero flag becomes set i.e. 1, otherwise it becomes reset i.e. 0. from 01H to FFH zero flag is 0 1- zero result 0- non-zero result The Z flag is set to 1, if after arithmetic and logical operations, the 8-bit result thus produced, is 00H. If the 8-bit result is not equal to 00H, the Z flag is reset to 0. Thus the Z flag is hoisted to indicate that the result is 0. The zero flag is set to 1 if the ALU operation results in 0, and the flag is reset if the result is not 0. The flag is modified by the results in the accumulator as well as in registers.

46. Example: MVI A 10 (load 10H in register A) SUB A (A = A – A) These set of instructions will set the zero flag to 1 as 10H – 10H is 00H

47. c) Auxiliary Carry Flag (AC)  In arithmetic operation, when carry is generated by digit D3 and passed on to digit D4 the A flag is set. This flag is used in BCD number system(0-9). If after any arithmetic or logical operation D(3) generates any carry and passes on to B(4) this flag becomes set i.e. 1, otherwise it becomes reset i.e. 0. This is the only flag register which is not accessible by the programmer 1- carry out from bit 3 on addition or borrow into bit 3 on subtraction 0- otherwise

48. Example: MOV A 2B (load 2BH in register A) MOV B 39 (load 39H in register B) ADD B (A = A + B) These set of instructions will set the auxiliary carry flag to 1, as on adding 2B and 39, addition of lower order nibbles B and 9 will generate a carry.

49. D) Parity Flag (P) This flag tests for number of 1 bits in accumulator. If the accumulator holds an even number of 1s, it is said that even parity exists and the parity flag is set to 1. If accumulator holds odd number of 1 then it is reset to 0. If after any arithmetic or logical operation the result has even parity, an even number of 1 bits, the parity register becomes set i.e. 1, otherwise it becomes reset i.e. 0.1-accumulator has even number of 1 bits. 0-accumulator has odd parity

50. Example: MVI A 05 (load 05H in register A) This instruction will set the parity flag to 1 as the BCD code of 05H is 00000101, which contains even number of ones i.e. 2. In above example no. of 1s =3 (odd no of 1s) So, parity flag is reset to 0 In above example no. of 1s =4 (even no of 1s) So, parity flag is set to 1

51. E) Carry flag (Cy)  If an arithmetic operation results in carry the carry flag is set, otherwise it is reset. The carry flag also serves as a borrow flag for subtraction. After performing the addition of any two 8-bit numbers, the carry generated can be either 0 or 1. That is only 1-bit. Thus to store the carry information 1-bit storage is enough. The Cy flag is stored in the LS bit position in the flags register. Instructions that use the Cy flag are widely used in the user programs.

52. Example 1 : In the addition of 45H and F3H, the result thus produced will be 38H and with Cy flag = 1, as shown below. Example 2 : In the addition of 85H and 1EH, the result thus produced will be A3H with Cy = 0, as shown below.

53. Program Counter (PC) : It is basically a  special purpose register  that is used to store the memory location of the instruction to be performed. As it is clear that in order to fetch an instruction from the memory the microprocessor needs to know about its address. It is a 16-bit register as it stores address. This register is used by the microprocessor to line up the instructions that are to be executed in a sequential manner. It functions in such a way that it fetches the opcode from one memory location and simultaneously gets incremented by the next memory location. Thus, it provides sequencing of the program to be executed.

54. Stack Pointer (SP) : It is also a 16-bit register and is a part of memory. The data is stored in the stack in serial format and stack pointer generally stores the address of the last data element stored in the stack. Thus the stack is based on  LIFO . Whenever a new data is added in the stack, then the stack pointer starts pointing towards the very next memory location. As against, when a data element is removed from the stack, then the stack pointer points to previous occupied memory location.

55. Instruction Register and Decoder During an instruction fetch, the first byte of an instruction, the opcode is transferred to 8-bit instruction register. The contents of instruction register are, in turn available to instruction decoder. The output of decoder , gated by timing signals, controls the register, ALU and data and address buffers. The output of decoder and internal clock generator produce the state and machine cycle timing signals.

56. Interrupts When microprocessor receives any interrupt signal from peripheral(s) which are requesting its services, it stops its current execution and program control is transferred to a sub-routine by generating  CALL  signal and after executing sub-routine by generating  RET  signal again program control is transferred to main program from where it had stopped. When microprocessor receives interrupt signals, it sends an acknowledgement (INTA) to the peripheral which is requesting for its service.

57. The highest interrupt priority is TRAP . This will cause program execution control to transfer to memory location 0024H. This input can not be disabled and therefore it is called nonmaskable interrupt. The next 3 interrupts are also called restarts. Their priority and address is branched. All last 4 interrupts can be enabled or disabled by software. Hence they are maskable interrupts.

58. Serial Input and output 8085 Microprocessor has two Serial Input/output pins that are used to read/write one bit data to and from peripheral devices. SID (Serial Input Data) line : -There is an One bit Input line inside the 8085 CPU (Pin number 5) -1 bit data can be externally read and stored using this SID line -The data that is read is stored in the A7th bit of the Accumulator -RIM instruction is used to read the SID line SID can be used as a general purpose TEST input.

59. SOD (Serial Output Data) Line -There is a One bit Output port inside the 8085 CPU (Pin number 4 -1 bit data can be externally written in this port. -To write data into this port, SIM instruction is used. -The data that is to be written in this port must be stored in the A7th bit of the Accumulator. - Bit A6 of the Accumulator is known as SOE (Serial output Enable). This bit Must be set to 1 to enable Serial data output. SOD can serve as 1-bit control output.

60. The 8085 Pin Diagram

61. 8085 pin diagram consist of following 6 groups: Address bus Multiplexed Address/ Data bus Control and Status Signals Power supply and frequency signals Externally initiated signals Serial I/O ports

62. 1. Address Bus The 8085 has eight signal lines, A15 - A8, Which are unidirectional and used as the higher order address bus.

63. 2) Multiplexed Address/ Data bus The signal lines AD - AD, are bidirectional. They are used as lower order address bus as well as the data bus i.e. they are used for dual purpose. In executing an instruction, during earlier part of cycle these lines are used as the low-order address bus. During later part of cycle, these lines are used as data bus. This is known as multiplexing the bus. The 8085 has a special signal called ALE (Address Latch Enable for informing the peripheral when the address / data bus is sending an address and when it is functioning as a data bus.

64. 3) Control and Status signals This group of signals includes two control signals RD and WR, three status signals IO/M, S1 and S0 and one special signal ALE. Control signals (RD, WR) Status signals (IO/M, S1, S0) Special Signal (ALE)

65. ALE –  It is an Address Latch Enable signal. It goes high during first T state of a machine cycle and enables the lower 8-bits of the address, if its value is 1 otherwise data bus is activated.   IO/M bar –  It is a status signal which determines whether the address is for input-output or memory. When it is high(1) the address on the address bus is for input-output devices. When it is low(0) the address on the address bus is for the memory.   SO, S1 –  These are status signals. They distinguish the various types of operations such as halt, reading, instruction fetching or writing. 

66. 1) ALE : This is address Latch Enable. This is a positive going pulse generated every time the 8085 begins an operation (machine cycle). This indicates that the bits on AD--AD, are address bits. This signal is used to separate the address bits. 2. RD bar: This is Read control signal. This is active low signal. This signal indicates that selected I/O or memory device is to be read and data are available on data bus. 3) WR bar : This is write control signal. This also active low. This signal indicates that the data on data bus are to be written into selected memory or I / O locations.

67. 4) IO/M bar: This is a status signal used to differentiate between I / O and memory operation. When it is high, it indicates an I / O operation. When it is low, it indicates a memory operation. 5) S1 and S0: These are status signals. They can identify various operations. The machine cycle types along with status signals are listed in figure (5.5).

68. 4) Power supply and clock frequency Signals

69. 5) Interrupts The 8085 has five interrupt signals - INTR, RST 7.5, RST 6.5, RST 5.5 and TRAP. These signals can be used to interrupt a program execution. 1) INTR : This is interrupt request signal. This is a general purpose interrupt. 2) RST 7.5, RST 6.5, RST 5.5 : These are restart interrupts. These are vectored interrupts and transfer the program control to specific memory locations. They have high priorities than INTR. Among these three, the priority order is 7.5, 6.5 and 5.5. 3) TRAP : This is non-maskable interrupt and has the highest priority.

70. 6) INTA bar : This is interrupt acknowledge. The microprocessor acknowledges an interrupt request by the INTA signal. In addition to the interrupts, three pins RESET, HOLD and READY accept the externally initiated signals as inputs.

71. 7) Ready If the signal at this READY pin is low , the microprocessor enters into a wait state. This signal is used primarily to synchronize slower peripherals with the microprocessor.

72. 8) DMA( Direct Memory Access) Signals: HOLD: When HOLD pin is activated by an external signal, the microprocessor relinquishes control of buses and allows the external peripherals to use them. For example HOLD signal is used in Direct memory Access (DMA) data transfer. 2) HLDA : This is hold acknowledge. Microprocessor acknowledges the hold request by HLDA.

73. 9. Reset Signals:    RESET IN bar: When the signal on this pin goes low, the program counter is set to zero, the buses are tristated and MPU is reset. 2) RESET OUT : This signal indicates that the MPU is being reset. The signal can be used to reset other devices.

74. 10) Serial I/O Ports The 8085 has two pins to implement serial transmission, SID (Serial input data) and SOD (serial output data). A single bit can be serially inputted through SID. The output pin SOD is set or reset as per 8085 SIM instruction.

75. 8085 interrupts

76. Interrupt  is the method of creating a temporary halt during program execution and allows peripheral devices to access the microprocessor. The microprocessor responds to that interrupt with an  ISR  (Interrupt Service Routine), which is a short program to instruct the microprocessor on how to handle the interrupt. The following image shows the types of interrupts we have in a 8086 microprocessor

77. Interrupt is a process where an external device can get the attention of the microprocessor. The process starts from the I/O device The process is asynchronous . Classification of Hardware Interrupts Hardware Interrupts can be classified into two types: Maskable Interrupts (Can be delayed or Rejected) Non-Maskable Interrupts (Can not be delayed or Rejected) Interrupts can also be classified into: Vectored (the address of the service routine is hard-wired) Non-vectored (the address of the service routine needs to be supplied externally by the device)

78. What happens when MP is interrupted ? When the Microprocessor receives an interrupt signal, it suspends the currently executing program and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt. Each interrupt will most probably have its own ISR. Responding to an interrupt may be immediate or delayed depending on whether the interrupt is maskable or non-maskable and whether interrupts are being masked or not.

79. Hardware Interrupts Hardware interrupt is caused by any peripheral device by sending a signal through a specified pin to the microprocessor. There are 5 Hardware Interrupts in 8085 microprocessor. They are –  INTR, RST 7.5, RST 6.5, RST 5.5, TRAP Software Interrupts Some instructions are inserted at the desired position into the program to create interrupts. These interrupt instructions can be used to test the working of various interrupt handlers. There are 8 software interrupts in 8085 microprocessor. They are –  RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7 .

80. What are maskable and non maskable interrupts in microprocessor? Maskable Interrupts  are those which can be disabled or ignored by the  microprocessor . These  interrupts  are either edge-triggered or level-triggered, so they can be disabled. INTR, RST 7.5, RST 6.5, RST 5.5  are maskable interrupts in 8085 microprocessor. Non - Maskable Interrupts  are those which cannot be disabled or ignored by  microprocessor . TRAP is a non-maskable interrupt . The 8085 has two hardware interrupt pins, i.e.  NMI and INTR . NMI is a non-maskable interrupt and INTR is a maskable interrupt having lower priority. One more interrupt pin associated is INTA called interrupt acknowledge.

81. Vectored and Non-Vectored Interrupts Vectored Interrupts are those which have fixed vector address (starting address of sub-routine) and after executing these, program control is transferred to that address. Non-Vectored Interrupts (Scalar Interrupt) are  those in which vector address is not predefined . The interrupting device gives the address of sub-routine for these interrupts.  INTR  is the only non-vectored interrupt in 8085 microprocessors.

82. INTERRUPT VECTOR ADDRESS TRAP (RST 4.5) 24 H RST 5.5 2C H RST 6.5 34 H RST 7.5 3C H           INTERRUPT VECTOR ADDRESS RST 0 00 H RST 1 08 H RST 2 10 H RST 3 18 H RST 4 20 H RST 5 28 H RST 6 30 H RST 7 38 H

83. Difference between Vectored and Non-vectored interrupt

84. Priority of Interrupts When microprocessor receives multiple interrupt requests simultaneously, it will execute the interrupt service request (ISR) according to the priority of the interrupts.

85. Interrupts 95

86. Interrupts What happens when MP is interrupted ? When the Microprocessor receives an interrupt signal, it suspends the currently executing program and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt. Each interrupt will most probably have its own ISR. Responding to an interrupt may be immediate or delayed depending on whether the interrupt is maskable or non-maskable and whether interrupts are being masked or not. 96

87. The 8085 Interrupts 97

88. The 8085 Interrupts The 8085 has 5 interrupt inputs. The INTR input. The INTR input is the only non-vectored interrupt. INTR is maskable using the EI/DI instruction pair. RST 5.5, RST 6.5, RST 7.5 are all automatically vectored. RST 5.5, RST 6.5, and RST 7.5 are all maskable. TRAP is the only non-maskable interrupt in the 8085 TRAP is also automatically vectored 98

89. The 8085 Interrupts Interrupt name Maskable Vectored INTR Yes No RST 5.5 Yes Yes RST 6.5 Yes Yes RST 7.5 Yes Yes TRAP No Yes 99

90. 8085 Interrupts 100 8085 TRAP RST7.5 RST6.5 RST 5.5 INTR INTA

91. Interrupt Vectors and the Vector Table 101

92. Example: Let , a device interrupts the Microprocessor using the RST 7.5 interrupt line. Because the RST 7.5 interrupt is vectored, Microprocessor knows , in which memory location it has to go using a call instruction to get the ISR address. RST7.5 is knows as Call 003Ch to Microprocessor. Microprocessor goes to 003C location and will get a JMP instruction to the actual ISR address. The Microprocessor will then, jump to the ISR location The process is illustrated in the next slide.. 102

93. The 8085 Non-Vectored Interrupt Process The interrupt process should be enabled using the EI instruction. The 8085 checks for an interrupt during the execution of every instruction. If INTR is high, MP completes current instruction, disables the interrupt and sends INTA (Interrupt acknowledge) signal to the device that interrupted INTA allows the I/O device to send a RST instruction through data bus. Upon receiving the INTA signal, MP saves the memory location of the next instruction on the stack and the program is transferred to ‘call’ location (ISR Call) specified by the RST instruction 103

94. The 8085 Non-Vectored Interrupt Process Microprocessor Performs the ISR. ISR must include the ‘EI’ instruction to enable the further interrupt within the program. RET instruction at the end of the ISR allows the MP to retrieve the return address from the stack and the program is transferred back to where the program was interrupted. 104

95. The 8085 Non-Vectored Interrupt Process The 8085 recognizes 8 RESTART instructions: RST0 - RST7. each of these would send the execution to a predetermined hard-wired memory location: 105 Restart Instruction Equivalent to RST0 CALL 0000H RST1 CALL 0008H RST2 CALL 0010H RST3 CALL 0018H RST4 CALL 0020H RST5 CALL 0028H RST6 CALL 0030H RST7 CALL 0038H

96. Restart Sequence The restart sequence is made up of three machine cycles In the 1st machine cycle: The microprocessor sends the INTA signal. While INTA is active the microprocessor reads the data lines expecting to receive, from the interrupting device, the opcode for the specific RST instruction. In the 2nd and 3rd machine cycles: the 16-bit address of the next instruction is saved on the stack. Then the microprocessor jumps to the address associated with the specified RST instruction. 106

97. Hardware Generation of RST Opcode 107 The following is an example of generating RST 5: RST 5’s opcode is EF = D D 76543210 11101111

98. Hardware Generation of RST Opcode 108

99. Issues in Implementing INTR Interrupts 109

100. Issues in Implementing INTR Interrupts Can the microprocessor be interrupted again before the completion of the ISR ? As soon as the 1st interrupt arrives, all maskable interrupts are disabled. They will only be enabled after the execution of the EI instruction. Therefore, the answer is: “only if we allow it to”. If the EI instruction is placed early in the ISR, other interrupt may occur before the ISR is done . 110

101. Multiple Interrupts & Priorities How do we allow multiple devices to interrupt using the INTR line? The microprocessor can only respond to one signal on INTR at a time. Therefore, we must allow the signal from only one of the devices to reach the microprocessor. We must assign some priority to the different devices and allow their signals to reach the microprocessor according to the priority. 111

102. The Priority Encoder 112

103. The 8085 Maskable/Vectored Interrupts The 8085 has 4 Masked/Vectored interrupt inputs. RST 5.5, RST 6.5, RST 7.5 They are all maskable. They are automatically vectored according to the following table: The vectors for these interrupt fall in between the vectors for the RST instructions. That’s why they have names like RST 5.5 (RST 5 and a half). 113 Interrupt Vector RST 5.5 002CH RST 6.5 0034H RST 7.5 003CH

104. Masking RST 5.5, RST 6.5 and RST 7.5 These three interrupts are masked at two levels: Through the Interrupt Enable flip flop and the EI/DI instructions. The Interrupt Enable flip flop controls the whole maskable interrupt process. Through individual mask flip flops that control the availability of the individual interrupts. These flip flops control the interrupts individually. 114

105. Maskable Interrupts and vector locations 115 Interrupt Enable Flip Flop INTR RST 5.5 RST 6.5 RST 7.5 M 5.5 M 6.5 M 7.5 RST7.5 Memory

106. The 8085 Maskable/Vectored Interrupt Process 116

107. The 8085 Maskable/Vectored Interrupt Process 117

108. Manipulating the Masks 118

109. How SIM Interprets the Accumulator 119 SDO SDE XXX R7.5 MSE M7.5 M6.5 M5.5 1 2 3 4 5 6 7 RST5.5 Mask RST6.5 Mask RST7.5 Mask } 0 - Available 1 - Masked Mask Set Enable 0 - Ignore bits 0-2 1 - Set the masks according to bits 0-2 Force RST7.5 Flip Flop to reset Not Used Enable Serial Data 0 - Ignore bit 7 1 - Send bit 7 to SOD pin Serial Data Out

110. Triggering Levels 120

111. Determining the Current Mask Settings RIM instruction: Read Interrupt Mask Load the accumulator with an 8-bit pattern showing the status of each interrupt pin and mask. 121 Interrupt Enable Flip Flop RST 5.5 RST 6.5 RST 7.5 M 5.5 M 6.5 M 7.5 RST7.5 Memory SDI P7.5 P6.5 P5.5 IE M7.5 M6.5 M5.5 1 2 3 4 5 6 7

112. How RIM sets the Accumulator’s different bits 122 SDI P7.5 P6.5 P5.5 IE M7.5 M6.5 M5.5 1 2 3 4 5 6 7 RST5.5 Mask RST6.5 Mask RST7.5 Mask } 0 - Available 1 - Masked Interrupt Enable Value of the Interrupt Enable Flip Flop Serial Data In RST5.5 Interrupt Pending RST6.5 Interrupt Pending RST7.5 Interrupt Pending

113. Pending Interrupts Since the 8085 has five interrupt lines, interrupts may occur during an ISR and remain pending. Using the RIM instruction, it is possible to can read the status of the interrupt lines and find if there are any pending interrupts. 123

114. TRAP 124

115. The 8085 Interrupts Interrupt Name Maskable Masking Method Vectored Memory Triggering Method INTR Yes DI / EI No No Level Sensitive RST 5.5 / RST 6.5 Yes DI / EI SIM Yes No Level Sensitive RST 7.5 Yes DI / EI SIM Yes Yes Edge Sensitive TRAP No None Yes No Level & Edge Sensitive 125

116. Thank You……..