8086 Architecture, Pin diagram, Addressing modes (3).pdf

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1. 8086 Microprocessor
Architectureof8086
Memorysegmentation,
Signal Description,
Addressing modes,

2. MODULEI
⚫Architectureof8086
⚫Memorysegmentation
⚫Signal description
⚫Addressingmodes

3. MICROPROCESSOR
⚫Asinglechipcomputer
⚫Devicewhichhasdataprocessingcapability
⚫Programcontrolledsemiconductordevice(IC)
whichfetches(frommemory),decodesand
executesinstructions.
⚫ItisusedasCPU(CentralProcessingUnit)in
computers.
⚫Microcontroller???
◦P+RAM+ROM+I/Oports+Timer
◦LessbulkierthanP
MODULE1

4. hardware
ThirdGeneration
During1978
HMOStechnologyFasterspeed,Higher
packingdensity
16bitprocessors40/ 48/64pins
Easiertoprogram
Dynamicallyrelatable programs
Processorhasmultiply/dividearithmetic
Morepowerfulinterrupthandling
capabilities
FlexibleI/Oportaddressing
Intel8086(16bitprocessor)
FirstGeneration
Between1971–1973
PMOStechnology,non compatiblewithTTL
4bitprocessors16pins
8and16bitprocessors40pins
Duetolimitationsofpins,signalsare
multiplexed
FifthGenerationPentium
32-bitP
Superscalararchitecture
FourthGeneration
During1980s
LowpowerversionofHMOStechnology
(HCMOS)
32bitprocessors
Physical memory space 2
24 bytes = 16 Mb
Virtual memory space 2
40bytes = 1 Tb
Floatingpointhardware
Supportsincreasednumberofaddressing
modes
Intel80386,80486
SecondGeneration
During1973
NMOStechnologyFaster speed,Higher
density,CompatiblewithTTL
4/8/16bitprocessors40pins
Abilitytoaddresslargememoryspaces
andI/O ports
Greaternumberoflevelsofsubroutine
nesting
Betterinterrupthandlingcapabilities
Intel8085 (8bitprocessor)
GENERATION
MODULE1

5. 8086-Overview
⚫First16-bitprocessorreleasedbyINTEL
in1978
⚫Powerfulinstructionset
⚫20-bitaddressingcapability
⚫Powerfulsetofregisters-generalpurpose
andspecialpurposeregisters
MODULE1

6. HOMEWORK
⚫DRAWTHEINTERNALBLOCK
DIAGRAMOF8086(detailed)
◦Refer Lyla B Das., The X86 Microprocessors
Architecture,ProgrammingandInterfacing

7. 8086ARCHITECTURE
MODULE1

8. ARCHITECTURE
MODULE1

9. Someof the16bitregisterscan be
usedastwo8 bitregistersas:
AXcanbeusedasAHandAL
BXcanbe usedasBH and BL
EUdecodesandexecutes
instructions.
AdecoderintheEUcontrol
systemtranslates
instructions.
16-bit ALU for
performing arithmetic
andlogicoperation
Four general purpose
registers(AX,BX,CX,DX);
Pointer registers (Stack
Pointer,BasePointer);
and
Index registers (Source
Index,DestinationIndex)
eachof16-bits
EXECUTIONUNIT
MODULE1

10. AccumulatorRegister(AX)
Consists oftwo 8-bitregisters AL andAH, whichcan
becombinedtogetherandusedasa16-bitregisterAX.
ALinthiscasecontainstheloworderbyteofthe
word,andAHcontainsthehigh-orderbyte.
TheI/OinstructionsusetheAXorALforinputting/
outputting16 or8bitdatatoorfromanI/Oport.
MultiplicationandDivisioninstructionsalsousetheAX
orALasimplicitregisterforoneoftheoperands.
EXECUTIONUNIT
MODULE1

11. BaseRegister(BX)
Consistsoftwo8-bitregistersBLandBH,whichcanbe
combinedtogetherandusedasa16-bitregisterBX.
BLinthiscasecontainsthelow-orderbyteoftheword,and
BHcontainsthehigh-orderbyte.
Thisistheonlygeneralpurposeregisterwhosecontents
canbeusedforaddressingthe8086memory.
Allmemoryreferencesutilizingthisregistercontentfor
addressinguseDSasthedefaultsegmentregister.
EXECUTIONUNIT
MODULE1

12. CounterRegister(CX)
Consistsoftwo8-bitregistersCLandCH,which
canbecombinedtogetherandusedasa16-bit
registerCX.
Whencombined,CLregistercontainsthelow
orderbyteoftheword,andCHcontainsthehigh-
orderbyte.
InstructionssuchasSHIFT,ROTATEandLOOPuse
thecontentsofCXasacounter.
EXECUTIONUNIT
MODULE1

13. DataRegister(DX)
Consistsoftwo8-bitregistersDLandDH,which
canbecombinedtogetherandusedasa16-bit
registerDX.
Whencombined,DLregistercontainsthelow
orderbyteoftheword,andDHcontainsthehigh-
orderbyte.
Usedtoholdthehigh16-bitresult(data)in16X
16multiplicationorthehigh16-bitdividend(data)
beforea32÷16divisionandthe16-bitremainder
afterdivision.
EXECUTIONUNIT
MODULE1

14. StackPointer(SP)andBasePointer(BP)
SPandBPareusedtoaccessdatainthestacksegment.
SPalwayspointstothetopofthestack
SPcontentsareautomaticallyupdated(incremented/
decremented)duetoexecutionofaPOPorPUSH
instruction.
BPcanpointtoanylocationinthestack
EXECUTIONUNIT
MODULE1

15. SourceIndex(SI)andDestinationIndex(DI)
Usedinindexedaddressing.
InstructionsthatprocessdatastringsusetheSIandDI
registerstogetherwithDSandESrespectivelyin
ordertodistinguishbetweenthesourceand
destinationaddresses.
EXECUTIONUNIT
MODULE1

16. FlagRegister
15141312 11 10 9 8 7 6 5 4 3 2 1 0
AF PF CF
CarryFlag
Thisflagisset,whenthereisa
carryoutofMSBincaseof
additionoraborrowincase
ofsubtraction.
ParityFlag
Thisflagissetto1,ifthelower
byteoftheresultcontainseven
numberof1’s;foroddnumber
of1’ssettozero.
AuxiliaryCarryFlag
Thisisset,ifthereisacarryfromthe
lowestnibble,i.e,bitB3duringaddition,or
borrowforthelowestnibblei.e.,B3
duringsubtraction..
Zero flag
This flag is set, when the result
of computation is zero
This flag is set, when the
result of computation is
negative
SignFlag
TrapFlag
Ifthisflagisset,theprocessor
entersthesinglestepexecution
odebygeneratinginternal
erruptsaftertheexecutionof
eachinstructionInterruptFlag
ausesthe8086torecognize
ernalmaskinterrupts;clearing
OF DF IF TFSFZF
OverflowFlag
Thisflagisset,ifanoverflowoccurs,i.e,iftheresultofa
signedoperationislargeenoughtoaccommodateina
d
ca
c
estinationregister.Theresultisofmorethan7-bitsinsizein
m
seof8-bitsignedoperationandmorethan15-bitsinsizein int
aseof16-bitsignoperations,thentheoverflowwillbeset.
C
ext
DirectionFlag
autodecrementingmode.
Thisisusedbystringmanipulationinstructions.Ifthisflagbitis‘0’,the
stringisprocessedbeginningfromthelowestaddresstothehighest
address,i.e.,autoincrementingmode.Otherwise,thestringis
processedfromthehighestaddresstowardsthelowestaddress,i.e.,
EXECUTIONUNIT
MODULE1

17. DedicatedAddertogenerate
20bitaddress
Four 16-bit segment
registers
CodeSegment(CS)
DataSegment(DS)
StackSegment(SS)
ExtraSegment(ES)
BUSINTERFACEUNIT
DEPARTMENTO
Se
F
gm
E
e
C
n
E
t
,
Registers>>
ARYANETINSTITUTEOFTECHNOLOGY
MODULE1

18. ADDRESSGENERATION:
◦20-bitaddressofabyteiscalleditsphysicaladdress
◦Itisspecifiedasalogicaladdresswhichisintheformof
two16-bitnumbersintheformatbaseaddress:offset
◦Segmentregistercontains16-bitbase(segment)address
◦Pointerregisterorindexregistercontainsoffsetaddress
◦Segmentaddressleft-shifted4times+offsetaddress=
physicaladdress
BUSINTERFACEUNIT
MODULE1

19. 0101010101010101
00010101010110100101
155 A5
BUSINTERFACEUNIT
Segmentaddrleft
shiftedwith
appendedzeros
Offset
Physicaladdress
ADDRESSGENERATION
⚫Eg:physicaladdress=155A5h(20bit)
⚫Segmentaddress=1005h(16bit)
0001000000000101
⚫Offset=5555h(16bit)
00010000000001010000
MODULE1

20. PhysicalAddress(20Bits)
Adder
SegmentRegister(16bits) 0000
OffsetValue (16bits)
MODULE1
ADDRESSGENERATION

21. MEMORYSEGMENTATION
⚫8086 has20-bitaddressbus
⚫Canaccess2
20addresslocations=1MB
⚫Physicalmemoryaddressrangingfrom00000hto FFFFFh
⚫Totalmemorysizedividedinto16segmentsof64KBeach-
segmentation
⚫4typesofsegments-data,code,extra&stacksegments
⚫Dataisstoredindatasegment
⚫Programcodeincodesegment
⚫Extrasegmentisanothertypeofdatasegmentusedina
specialway
⚫Stacksegmentisanareaofmemorywhichfunctionsandis
accesseddifferentlyfromtheother3segments
BUSINTERFACEUNIT
MODULE1

22. MEMORYSEGMENTATION
⚫Generalconcerns:
◦Segmentaddressesaredivisibleby16
◦Segmentscanbeoverlapping-morethan1logicaladdressforthe
samephysicaladdress
◦Therecanbemanysegmentswithsamebaseaddressbuttheoffsets
withinthesegmentwillhavetobetakencareoftoprevent
overwritingofdata.
◦Asegmentcanhaveamaximumsizeof64KB
◦Aprogramneednothaveall4segments,butitwillhaveatleastthe
codesegment
◦Theaddressusedininstructionsarecalledlogicaladdressesandare
translatedbytheBIUtophysicaladdress
BUSINTERFACEUNIT
MODULE1

23. MODULE1
BUSINTERFACEUNIT
MEMORYSEGMENTATION
⚫Advantages
◦Itallowsaddressregisterstohavethesamesize
asthedataregisterswhileallowingtheuseof20-
bitphysicaladdress
◦Alladdressesinmemoryarere-locatable
◦Allowsplacingofcode,dataandstackportionsof
thesameprogramindifferentparts(segments)of
memory,fordataandcodeprotection

24. CodeSegmentRegister
16-bit
CScontainsthebaseorstartofthecurrentcode
segment;IPcontainsthedistanceoroffsetfromthis
addresstothenextinstructionbytetobefetched.
BIUcomputesthe20-bitphysicaladdressbylogically
shiftingthecontentsofCS4-bitstotheleftandthen
addingthe16-bitcontentsofIP.
This20-bitaddressisthenplacedontheaddressbusand
theinstructionbyteisfetched.
Thusthelogicaladdressforaninstructionbyteisofthe
formCS:IP
BUSINTERFACEUNIT
MODULE1

25. DataSegmentRegister
16-bit
DSpointstothecurrentdatasegment;operands
formostinstructionsarefetchedfromthissegment.
The16-bitcontentsoftheSourceIndex(SI)or
DestinationIndex(DI)ora16-bitdisplacementare
usedasoffsetforcomputingthe20-bitphysical
address.
BUSINTERFACEUNIT
MODULE1

26. StackSegmentRegister
Stackin8086 isLIFOstack
16-bitstackpointer(SP)pointstothetopofthe
stack
Baseaddress(16bit)isavailableinstacksegment
register(SS)
LogicaladdressofastackcanbeoftheformSS:SP
orSS:BP
BIUcomputesthe20-bitphysicaladdressby
logicallyshiftingthecontentsofSS4-bitstotheleft
andthenaddingthe16-bitcontentsofSP.
BUSINTERFACEUNIT
MODULE1

27. ExtraSegmentRegister
16-bit
Pointstotheextrasegmentinwhichdata(inexcess
of64KpointedtobytheDS)isstored.
StringinstructionsusetheESandDItodetermine
the20-bitphysicaladdressforthedestination.
BUSINTERFACEUNIT
MODULE1

28. InstructionPointer
16-bit
Alwayspointstothenextinstruction
thecurrentlyexecuting
tobe
codeexecutedwithin
segment.
So,thisregistercontainsthe16-bitoffsetaddress
pointingtothenextinstructioncodewithinthe
64Kbofthecodesegmentarea.
Itscontentisautomaticallyincrementedasthe
executionofthenextinstructiontakesplace.
MODULE1
BUSINTERFACEUNIT

29. AgroupofFirst-In-First-
Out(FIFO)inwhichupto
6bytesofinstructioncode
areprefetchedfromthe
memoryaheadoftime.
Thisisdoneinorderto
speeduptheexecutionby
overlappinginstruction
fetchwithexecution.
Thismechanismisknown
aspipelining.
Instructionqueue
BUSINTERFACEUNIT
MODULE1

30. ASSIGNMENT1
⚫INSTRUCTIONSETOF8086
◦Datatransferinstructions
◦Branchinstructions
◦Arithmeticinstructions
◦Logicalinstructions
◦Shiftandrotateinstructions
◦Stringinstructions

31. HOMEWORK
⚫Drawthepindiagramof8086

32. HARDWARE
SPECIFICATION
MODULE1

33. AD
0-AD
15(Bidirectional)
Address/Databus
Loworderaddressbus;thesearemultiplexed
withdata.
WhenADlinesareusedtotransmitmemory
addressthesymbolAisusedinsteadofAD,for
exampleA
0-A
15.
WhendataaretransmittedoverADlinesthe
symbolDisusedinplaceofAD,forexampleD
0-
D
7,D
8-D
15orD
0-D
15.
A
16/S
3,A
17/S
4,A
18/S
5,A
19/S
6
Highorderaddressbus.Thesearemultiplexed
withstatussignals
PINSANDSIGNALS
COMMONSIGNALS

34. BHE(ActiveLow)/S
7(Output)
BusHighEnable/Status
Itisusedtoenabledataontothemost
significanthalfofdatabus,D
8-D
15.8-bit
deviceconnectedtoupperhalfofthedata
bususeBHE(ActiveLow)signal.Itis
multiplexedwithstatussignalS
7.
MN/MX
MINIMUM/MAXIMUM
Thispinsignalindicateswhatmodethe
processoristooperatein.
RD(Read)(ActiveLow)
The signalisusedforreadoperation.
Itisanoutputsignal.
Itisactivewhenlow.
PINSANDSIGNALS
COMMONSIGNALS

35. TEST
TESTInputistestedbythe‘WAIT’instruction.
8086willenterawaitstateafterexecutionofthe
WAITinstructionandwillresumeexecutiononly
whentheTESTismadelowbyanactive
hardware.
Thisisusedtosynchronizeanexternalactivityto
theprocessorinternaloperation.
READY
Thisistheacknowledgementfromtheslow
deviceormemorythattheyhavecompletedthe
datatransfer.
Thesignalmadeavailablebythedevicesis
synchronizedbythe8284Aclockgeneratorto
providereadyinputtothe8086.
Thesignalisactivehigh.
PINSANDSIGNALS
COMMONSIGNALS

36. RESET(Input)
Causestheprocessortoimmediatelyterminate
itspresent activity.
ThesignalmustbeactiveHIGHforatleastfour
clockcycles.
CLK(Clock)
Theclockinputprovidesthebasictimingfor
processoroperationandbuscontrolactivity.Its
anasymmetricsquarewavewith33%dutycycle.
INTR(InterruptRequest)
Thisisatriggeredinput.Usedbyanexternal
devicetointerrupt8086,whichrespondsonlyifIF
flagis1.
NMI(NonMaskableInterrupt)
Highpriorityinterrupt.Requestisacceptedno
matterwhatIFis.
PINSANDSIGNALS
COMMONSIGNALS

37. The8086microprocessorcanworkintwomodes
ofoperations:MinimummodeandMaximummode.
Intheminimummode
microprocessordonotassociate
ofoperationthe
withanyco-
andcannotbeusedformultiprocessorprocessors
systems.
Inthemaximummodethe8086canworkinmulti-
processororco-processorconfiguration.
Minimumormaximummodeoperationsare
decidedbythepinMN/MX(Activelow).
Whenthispinishigh8086operatesinminimum
modeotherwiseitoperatesinMaximummode.
PINSANDSIGNALS
MODULE1
MIN/MAXMODESIGNALS

38. DT/R (DataTransmit/Receive)Outputsignalfromthe
processortocontrolthedirectionofdata
flow throughthedatatransceivers
DEN (DataEnable)Outputsignalfromtheprocessorused
asoutputenableforthetransceivers
ALE (AddressLatchEnable)Usedtodemultiplexthe
addressanddatalinesusingexternallatches
M/IO UsedtodifferentiatememoryaccessandI/O
access.Formemoryreferenceinstructions,itis
high.ForINandOUTinstructions,itislow.
WR Writecontrolsignal;assertedlowWhenever
processorwritesdatatomemoryorI/Oport
INTA (InterruptAcknowledge)Whentheinterruptrequest
isacceptedbytheprocessor,theoutputislow
on thisline.
MODULE1
PINSANDSIGNALS
MINIMUMMODESIGNALS
PINS24TO31

39. HOLD Inputsignaltotheprocessorfromthebus
masters
asarequesttograntthecontrolofthebus.
UsuallyusedbytheDMAcontroller toget
the controlofthebus.
HLDA (HoldAcknowledge)Acknowledgesignalbythe
processortothebusmasterrequestingthecontrol
ofthebusthroughHOLD.
Theacknowledgeisassertedhigh,
whenthe processoracceptsHOLD.
MODULE1
PINSANDSIGNALS
MINIMUMMODESIGNALS
PINS24TO31

40. ??????0,??????1,??????2Statussignals;usedbythe8086bus
controllertogeneratebustimingandcontrol
signals.Thesearedecodedasshown.
PINSANDSIGNALS
MAXIMUMMODESIGNALS
MODULE1
PINS24TO31REASSIGNED

41. ????????????0,????????????1(QueueStatus)Theprocessorprovidesthestatusof
queueintheselines.
Thequeuestatuscanbeusedbyexternaldeviceto
tracktheinternalstatusofthequeuein8086.
The outputon QS
0andQS
1canbeinterpretedas
showninthetable.
MODULE1
PINSANDSIGNALS
MAXIMUMMODESIGNALS
PINS24TO31REASSIGNED

42. RQ/
GT0,
RQ/GT1
(BusRequest/BusGrant)Theserequestsareusedby
otherlocalbusmasterstoforcetheprocessorto
releasethelocalbusattheendoftheprocessor’s
currentbuscycle.
Thesepinsarebidirectional.
TherequestonGT0willhavehigherprioritythan
GT1
MODULE1
MAXIMUMMODESIGNALS
PINSANDSIGNALS
PINS24TO31REASSIGNED
LOCK AnoutputsignalactivatedbytheLOCK
prefix instruction.
Remainsactiveuntilthecompletionof
the instructionprefixedbyLOCK.
The8086outputlowontheLOCKpin
while executinganinstructionprefixed
byLOCKto
preventotherbusmastersfromgainingcontrolof
thesystembus.

43. ADDRESSING MODES
MODULE1

44. Every instruction of a program has to operate on a data.
Thedifferentwaysinwhichasourceoperandisdenoted
inaninstructionareknownasaddressingmodes.
1.RegisterAddressing
2.ImmediateAddressing
3.DirectAddressing
4.RegisterIndirectAddressing
5.IndexedAddressing
6.BasedIndexedAddressing
7.RelativebasedindexedAddressing
8.ImpliedAddressing
ADDRESSINGMODES

45. Theinstructionwillspecifythename ofthe
registerwhichholdsthedatatobeoperatedby
theinstruction.
Example:
MOVCL,DH
Thecontentof8-bitregisterDHismovedto
another 8-bitregisterCL
(CL)(DH)
ADDRESSINGMODES
1.RegisterAddressing
2.ImmediateAddressing
3.DirectAddressing
4.RegisterIndirectAddressing
5.IndexedAddressing
6.BasedIndexedAddressing
7.RelativebasedindexedAddressing
8.ImpliedAddressing

46. Inimmediateaddressingmode,an8-bitor16-bit
dataisspecifiedaspart of theinstruction
Example:
MOVDL,08H
The8-bitdata(08
H)givenintheinstructionis
movedto DL
(DL)08
H
MOVAX,0A9FH
The16-bitdata(0A9F
H)givenintheinstructionis
movedtoAXregister
(AX)0A9F
H
ADDRESSINGMODES
1.RegisterAddressing
2.ImmediateAddressing
3.DirectAddressing
4.RegisterIndirectAddressing
5.IndexedAddressing
6.BasedIndexedAddressing
7.RelativebasedindexedAddressing
8.ImpliedAddressing

47. Here,theeffectiveaddressofthememory
locationatwhichthedataoperandisstoredis
givenintheinstruction.
Theeffectiveaddress is justa16-bitnumber
writtendirectlyintheinstruction.
Example:
MOV BX, [1354H]
MOV BL,[0400H]
squarebracketsaroundthe1354
HdenotesThe
thecontentsofthememory location.When
executed,thisinstructionwillcopythecontentsof
thememorylocationintoBXregister.
Thisaddressingmodeiscalleddirectbecausethe
displacement oftheoperandfromthesegment
baseisspecifieddirectlyintheinstruction.
ADDRESSINGMODES
1.RegisterAddressing
2.ImmediateAddressing
3.DirectAddressing
4.RegisterIndirectAddressing
5.IndexedAddressing
6.BasedIndexedAddressing
7.Relativebasedindexed
Addressing
8.ImpliedAddressing

48. InRegisterindirectaddressing,nameofthe
registerwhichholdstheeffectiveaddress(EA)
willbespecifiedintheinstruction.
RegistersusedtoholdEAareanyofthefollowing
registers:
BX,BP,DIandSI.
ContentoftheDSregisterisusedforbase
addresscalculation.
Example:
MOVCX,[BX]
Operations:
EA=(BX)
BA=(DS)x16
10
MA=BA+EA
(CX)(MA)or,
(CL)(MA)
(CH)(MA+1)
Note:Register/memory
enclosedinbracketsreferto
contentofregister/memory
ADDRESSINGMODES
1.RegisterAddressing
2.ImmediateAddressing
3.DirectAddressing
4.RegisterIndirectAddressing
5.IndexedAddressing
6.BasedIndexedAddressing
7.Relativebasedindexed
Addressing
8.ImpliedAddressing

49. SIorDIregisterisusedtoholdanindexvaluefor
memory.
Incaseof8-bitdisplacement,itissignextended
to 16-bitbeforeaddingtothebasevalue.
Example:
MOVCX,[SI]
Operations:
offset =(SI)
BA=(DS)x16
10
MA=BA+offset
(CX)(MA)or,
(CL)(MA)
(CH)(MA +1)
ADDRESSINGMODES
1.RegisterAddressing
2.ImmediateAddressing
3.DirectAddressing
4.RegisterIndirectAddressing
5.IndexedAddressing
6.BasedIndexedAddressing
7.RelativebasedindexedAddressing
8.ImpliedAddressing

50. InBasedIndexAddressing,theeffectiveaddress
iscomputed fromthesumofabaseregister(BX
orBP)andanindexregister(SIor DI).
Example:
MOVDX,[BX+SI]
Operations:
000A
H0A
H (Signextended)
EA=(BX)+(SI)
BA=(DS)x16
10
MA=BA+EA
(DL)(MA)
(DH)(MA+1)
ADDRESSINGMODES
1.RegisterAddressing
2.ImmediateAddressing
3.DirectAddressing
4.RegisterIndirectAddressing
5.IndexedAddressing
6.BasedIndexedAddressing
7.RelativebasedindexedAddressing
(DX)(MA)or,
8.ImpliedAddressing

51. ADDRESSINGMODES
1.RegisterAddressing
2.ImmediateAddressing
3.DirectAddressing
4.RegisterIndirectAddressing
5.IndexedAddressing
6.BasedIndexedAddressing
7.RelativebasedindexedAddressing
8.ImpliedAddressing
Inrelativebased Indexed Addressing, the
effectiveaddressiscomputed fromthesumofa
baseregister(BXorBP),anindexregister(SIor
DI)andadisplacement.
Example:
MOVDX,[BX+SI+0AH]
Operations:
000A
H0A
H (Signextended)
EA=(BX)+(SI)+000A
H
BA=(DS)x16
10
MA=BA+EA
(DX)(MA)or,
(DL)(MA)
(DH)(MA+1)

52. Instructions usingthismode have no
operands.Theinstructionitselfwillspecify
thedatatobeoperatedbytheinstruction.
ADDRESSINGMODES
1.RegisterAddressing
2.ImmediateAddressing
3.DirectAddressing
4.RegisterIndirectAddressing
5.IndexedAddressing
6.BasedIndexedAddressing
Example:CLC
7.RelativebasedindexedAddressing
Thisclearsthecarryflagtozero.
8.ImpliedAddressing