8086 memory interface.pptx

Memory

1. 8086 µ p - memory Interface (1) Chapter(7)

2. Computer Block Diagram

3. Bits stored in a semiconductor latch or flip-flop Bits stored as charge on a capacitor

4. MEMORY BASICS Address Data 1 2 3 4 5 6 7

5. MEMORY READ Read

6. MEMORY WRITE write

7. Rom

8. EPROM 2764 8KX8

9. EPROM intel 2716 2KX8

10. EEPROM ATMEL 2864 8KX8

11. SRAm

12. SRAM 4016 2KX8

13. SRAM CY6264 8KX8

14. MEMORY EXPANSION

15. MEMORY ADDRESS DATA WR OE CE MWR MRD CS MEMORY FUNCTIONAL BLOCK DIAGRAM

16. MEMORY WORD SIZE (DATA BUS) EXPANSION

17. MEMORY WORD SIZE (DATA BUS) EXPANSION (continued)

18. MEMORY ADDRESS (WORD CAPACITY) EXPANSION

19. MEMORYADDRESS (WORD CAPACITY) EXPANSION (continued)

20. THE MEMORY CAN ALSO be EXPANDED bothe WORD SIZE AND CAPACITY at the SAME TIME to GET the DESIRED MEMORY SIZE

21. HOME WORK Expand the 2Kx8 (2716) EPROM to get 2Kx16 memory size, draw the block diagram. Expand the 2KX8 (2716) EPROM to get 4KX8 memory size, draw the block diagram. Expand the 2KX8 (2716) EPROM to get 8KX16 memory size, draw the block diagram. How many 2716 memory chip are needed for each case of the above?

22. Memory up to 1MB Logical Presentation 7 15 8 7 Physical Presentation Address BUS (20 bit) Address BUS (20 bit) Data BUS (16 bit) Data BUS (16 bit) (D8-D15) (D0-D7) 1MB 512KB 512KB Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 EVEN BANK ODD BANK 19 BIT BHE A0

23. 8086 Byte access on even address ( low) Address bus A 19 – A 1 D 15 – D 8 D 7 – D ____ BHE ( HIGH ) Y Y + 1 X + 1 X A ( LOW ) A0 is set to 0 to enable low bank BHE is set to logic 1 to disable high bank Data is transferred via D0 ( LSB ) – D7 ( MSB )

24. 8086 Byte access on odd address ( high bank) Address bus A 19 – A 1 D 15 – D 8 D 7 – D ____ BHE ( LOW ) Y Y + 1 X + 1 X A ( HIGH ) A0 is set to 1 to disable low bank BHE is set to logic 0 to enable high bank Data is transferred via D8 ( LSB ) – D15 ( MSB )

25. 8086 Word access on even address ( lowbank )-aligned Address bus A 19 – A 1 D 15 – D 8 D 7 – D ____ BHE ( LOW ) Y Y + 1 X + 1 X Both A0 and BHE is enabled ; data transferred from both banks at same time Data is transferred via D0 ( LSB ) – D15 ( MSB ) Aligned and occurs in 1 bus cycle A ( LOW )

26. The END