8086 Microprocessor Architecture: 16-bit microprocessor

This presentation gives you easier way to study 8086 i.e. 16 bit microprocessor. 8086 microprocessor's architecture contains two basic functional units namely Bus Interface Unit and Execution Unit. BIS fetches the instructions from memory. It reads/writes instructions to/from memory. Input/Output of data to/from I/O peripheral ports. Address generation of memory reference. Queing instructions. Thus, BIU handles all transfer of data and address. Tasks of EU: Decodes the instructions. Executes the decoded instructions. Tells BIU from where to fetch the instruction. EU takes care of performing operation on the data. EU is also known as heart of the data.

1. 8086 Architecture
-Presented By,
Ashvini A Todkar
Assistant Professor, ATS’s SBGI Miraj
1

2. Block diagram of 8086
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3. Software Model of the 8086 Microprocessors
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4. 8086 Registers
4CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX

5. General Purpose Registers
•Normally used for storing temporary results
•Each of the registers is 16 bits wide (AX, BX, CX, DX)
•Can be accessed as either 16 or 8 bits AX, AH, AL
5
AX -the Accumulator
BX -the Base Register
CX -the Count Register
DX -the Data Register

6. General Purpose Registers
•AX
–Accumulator Register
–Preferred register to use in arithmetic, logic and data
transfer instructions because it generates the shortest
Machine Language Code
–Must be used in multiplication and division
operations
–Must also be used in I/O operations
•BX
–Base Register
–Also serves as an address register
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7. General Purpose Registers
•CX
–Count register
–Used as a loop counter
–Used in shift and rotate operations
•DX
–Data register
–Used in multiplication and division
–Also used in I/O operations
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8. Pointer and Index Registers
•All 16 bits wide, L/H bytes are not accessible
•Used as memory pointers
–Example: MOV AH, [SI]
•Move the byte stored in memory location whose addressis contained in
register SI to register AH
•IP is not under direct control of the programmer
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9. Flag Register
9
Carry
Parity
Auxiliary Carry
Zero
Overflow
Direction
Interrupt enable
Trap
Sign
6 are status flags
3 are control flag

10. 8086 Programmer’s Model
10
ES
CS
SS
DS
IP
AH
BH
CH
DH
AL
BL
CL
DL
SP
BP
SI
DI
FLAGS
AX
BX
CX
DX
Extra Segment
Code Segment
Stack Segment
Data Segment
Instruction Pointer
Accumulator
Base Register
Count Register
Data Register
Stack Pointer
Base Pointer
Source Index Register
Destination Index Register
BIU registers
(20 bit adder)
EUregisters

11. The Stack
•Thestackisusedfortemporarystorageofinformation
suchasdataoraddresses.
•WhenaCALLisexecuted,the8086automaticallyPUSHes
thecurrentvalueofCSandIPontothestack.
•Otherregisterscanalsobepushed
•Beforereturnfromthesubroutine,POPinstructionscan
beusedtopopvaluesbackfromthestackintothe
correspondingregisters.
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12. The Stack
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13. INTEL 8086 -Pin Diagram
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14. INTEL 8086 -Pin Details
14
Ground
Clock
Duty cycle: 33%
Power Supply
5V 10%
Reset
Registers, seg
regs, flags
CS: FFFFH, IP:
0000H
If high for
minimum 4
clks

15. INTEL 8086 -Pin Details
15
Address/DataBus:
Contains address
bits A
15-A
0 when ALE
is 1 & data bits D
15–
D
0when ALE is 0.
Address Latch Enable:
When high,
multiplexed
address/data bus
contains address
information.

16. INTEL 8086 -Pin Details
16
INTERRUPT
Non -maskable
interrupt
Interrupt request
Interrupt
acknowledge

17. INTEL 8086 -Pin Details
17
Direct
Memory
Access
Hold
acknowledge
Hold

18. INTEL 8086 -Pin Details
18
Address/Status Bus
Address bits A
19–
A
16& Status bits S
6
–S
3

19. INTEL 8086 -Pin Details
19
Bus High Enable/S7
Enables most
significant data bits
D
15–D
8during read
or write operation.
S
7: Always 1.
BHE#, A
0:
0,0:Whole word
(16-bits)
0,1:High byte
to/from odd address
1,0:Low byte
to/from even address
1,1:No selection

20. INTEL 8086 -Pin Details
20
Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V
Minimum Mode Pins
Maximum Mode
Pins

21. Minimum Mode-Pin Details
21
Read Signal
Write Signal
Memory or I/0
Data Bus Enable
Data
Transmit/Receive

22. Maximum Mode -Pin Details
22
Status Signal
Inputs to 8288 to
generate eliminated
signals due to max
mode.
S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access
101: read memory
110: write memory
111: none -passive

23. Maximum Mode -Pin Details
23
DMA
Request/Grant
Lock Output
LockOutput
Usedtolockperipherals
offthesystem
Activatedbyusingthe
LOCK:prefixonany
instruction

24. Maximum Mode -Pin Details
24
Queue Status
Used by numeric
coprocessor (8087)
QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of
opcode

25. Minimum Mode 8086 System
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26. Minimum Mode 8086 System
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27. ‘Read’ Cycle timing Diagram for
Minimum Mode
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28. ‘Write’ Cycle timing Diagram for
Minimum Mode
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29. Maximum Mode 8086 System
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30. Maximum Mode 8086 System
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31. Maximum Mode 8086 System
•Here,eitheranumericcoprocessorofthetype8087oranother
processorisinterfacedwith8086.
•TheMemory,AddressBus,DataBusesaresharedresources
betweenthetwoprocessors.
•ThecontrolsignalsforMaximummodeofoperationare
generatedbytheBusControllerchip8788.
•ThethreestatusoutputsS0*,S1*,S2*fromtheprocessorare
inputto8788.
•TheoutputsofthebuscontrolleraretheControlSignals,namely
DEN,DT/R*,IORC*,IOWTC*,MWTC*,MRDC*,ALEetc.
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32. Memory Read timing in
Maximum Mode
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33. Memory Write timing in
Maximum Mode
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34. 8086 Control Signals
1.ALE
2.BHE
3.M/IO
4.DT/R
5.RD
6.WR
7.DEN
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35. Coprocessor and Multiprocessor
configuration
•MultiprocessorSystemsrefertotheuseofmultiple
processorsthatexecutesinstructionssimultaneously
andcommunicatewitheachotherusingmailboxesand
Semaphores.
•Maximummodeof8086isdesignedtoimplement3
basicmultiprocessorconfigurations:
1.Coprocessor(8087)
2.Closelycoupled(8089)
3.Looselycoupled(Multibus)
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36. Coprocessor and Multiprocessor
configuration
•CoprocessorsandCloselycoupledconfigurationsare
similarinthatboththe8086andtheexternalprocessor
sharesthe:
-Memory
-I/O system
-Bus & bus control logic
-Clock generator
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37. Coprocessor / Closely Coupled
Configuration
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38. TEST pin of 8086
•UsedinconjunctionwiththeWAITinstructionin
multiprocessingenvironments.
•Thisisinputfromthe8087coprocessor.
•Duringexecutionofawaitinstruction,theCPUchecksthis
signal.
•Ifitislow,executionofthesignalwillcontinue;ifnot,it
willstopexecuting.
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39. Coprocessor Execution Example
Coprocessor cannot take control of the bus, it does everything through the CPU
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40. Closely Coupled Execution Example
•Closely Coupled
processor may take
control of the bus
independently.
•Two 8086’s cannot
be closely coupled.
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41. Loosely Coupled Configuration
•hassharedsystembus,systemmemory,andsystem
I/O.
•eachprocessorhasitsownclockaswellasitsown
memory(inadditiontoaccesstothesystemresources).
•Usedformediumtolargemultiprocessorsystems.
•Eachmoduleiscapableofbeingthebusmaster.
•Anymodulecouldbeaprocessorcapableofbeingabus
master,acoprocessorconfigurationoracloselycoupled
configuration.
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42. Loosely Coupled Configuration
•Nodirectconnectionsbetweenthemodules.
•Eachsharethesystembusandcommunicatethrough
sharedresources.
•Processorintheirseparatemodulescansimultaneously
accesstheirprivatesubsystemsthroughtheirlocal
busses,andperformtheirlocaldatareferencesand
instructionfetchesindependently.Thisresultsin
improveddegreeofconcurrentprocessing.
•Excellentforrealtimeapplications,asseparatemodules
canbeassignedspecializedtasks
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43. Advantages of Multiprocessor
Configuration
1.Highsystemthroughputcanbeachievedbyhavingmorethan
oneCPU.
2.Thesystemcanbeexpandedinmodularform.
Eachbusmastermoduleisanindependentunitandnormallyresideson
aseparatePCboard.Onecanbeaddedorremovedwithoutaffectingthe
othersinthesystem.
3.Afailureinonemodulenormallydoesnotaffectthebreakdown
oftheentiresystemandthefaultymodulecanbeeasily
detectedandreplaced
4.Eachbusmasterhasitsownlocalbustoaccessdedicated
memoryorIOdevices.Soagreaterdegreeofparallelprocessing
canbeachieved.
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44. WAIT State
•Awaitstate(T
w)isanextraclockingperiod,inserted
betweenT2andT3,tolengthenthebuscycle,allowing
slowermemoryandI/Ocomponentstorespond.
•TheREADYinputissampledattheendofT2,andagain,
ifnecessaryinthemiddleofTw.IfREADYis‘0’thena
Twisinserted.
44 1 2 3 4
Clock
READY
Tw

45. 8086 System Memory Circuitry
1.Minimum Mode System Memory Circuitry
2.Maximum Mode System Memory Circuitry
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46. Minimum Mode System Memory Circuitry
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47. Maximum Mode System Memory Circuitry
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