9 semiconductor memory

Semiconductor Memory

1. Semiconductor Memory
UshaMehta
[email protected]

2. Introduction
and
Memory Architecture

3. Concept, Design Parameters, and
Requirements
Concept
•Data storage essential for processing
•Binary storage
•Switches
•How do you implement this in Hardware?
Requirements
•Easy reading
•Easy Writing
•High density
•Speed, more speed and still more speed
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4. Design Parameters
•Area Efficiency of Memory Array: of stored
data bits per unit area
•Memory Access Time: the time required to
store and/or retrieve a particular data bit.
•Static and Dynamic Power Consumption
4
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5. Memory….
•Want inexpensive, fast memory
•Main memory
•Large, inexpensive, slow memory
•stores entire program and data
•Cache
•Small, expensive, fast memory
•stores copy of likely accessed parts of larger
memory
•Can be multiple levels of cache
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6. Memory Hierarchy in Computer System
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7. Advanced Memory Hierarchy in
Computer System
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8. Virtual memory
•Virtual memory is a section of volatile
memory created temporarily on the storage
drive. It is created when a computer is
running many processes at once and RAM is
running low.
•The operating system makes part of the
storage drive available to use as RAM. Virtual
memory is much slower than main memory
because processing power is being taken up
by moving data around, rather than just
executing instructions.
•Latency is increased when the computer
needs to use virtual memory.
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9. Swapping
•Swappingis the process the OS uses to move
data between RAM and virtual memory. The OS
moves data from processes that are not
immediately needed out of the RAM and stores
them in virtual memory. It copies the data back
into RAM when the process is needed again.
•Using virtual memory slows the computer down
because copying to a hard disk takes much
longer than reading and writing RAM. Semiconductor Memory
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10. Memory Timing Definitions
•Cycle time of a memory is the minimum time between
successive read or write.
•Cycle time > Access time.
•Read and write cycle time not same (we take is same for
simplicity in system design)
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AccessTime:timebetweenrequestandwordarrives
CycleTime:timebetweenrequests

11. Memory Architecture

12. Bit Cell
•Each bit cell is connected
to a wordlineand a bitline
•Wordline(Row Line): to select the memory cell
•For each combination of address bits, the
memory asserts a single wordlinethat activates
the bit cells in that row.
•Bitline(Columnline): to read or write the content
in Cell
•When the wordlineis HIGH, the stored bit
transfers to or from the bitline. Otherwise, the
bitlineis disconnected from the bit cell. The
circuitry to store the bit varies with memory
type.
12
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13. Address Signals of memory
•Bit line and Word Line to select the cell for read
and write of memory
•BL: connected to Source of transistor
•WL: connected to Gate of Transistor
•Column Address Strobe CAS : Word Lines
•Row Address Strobe RAS: Bit Lines
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14. Random Access Memory :
Basic Organization
•N words
•M bits per word
•N select lines
•1:N decoder
•very inefficient design
•difficult to place and
route
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15. Random Access Memory:
Real Organization
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16. Size of Row-Column Decoders
•aspect ratio (height : width) should be relative
square
•Row / Column organization (matrix)
•A = log2(R); B = log2(C)
•R * C = N
•number of rows should be power of 2
•number of bits in a row
•sense amplifiers to amplify the voltage from
each memory cell
•1 -> 2
R
row decoder
•1 -> 2
C
column decoder
•implement M of the column decoders (M
bits, one per bit)
•M = output word width
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17. 2D Memory Organization
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18. 2.5D Memory Organization
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19. 2.5 D Memory Organization
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20. Hierarchical Memory ArchitectureGlobal Data Bus
Row
Address
Column
Address
Block
Address
Block Selector Global
Amplifier/Driver
I/O
Control
Circuitry
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
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21. Semiconductor Memory

22. Semiconductor Memory
Classification
Read-Write Memory
Non-Volatile
Read-Write
Memory
Read-Only Memory
EPROM
E
2
PROM
FLASH
Random
Access
Non-Random
Access
SRAM
DRAM
Mask-Programmed
Programmable (PROM)
FIFO
Shift Register
CAM
LIFO
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23. Memory Classification
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24. For quick remembrance….
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25. Write Ability
•Ranges of writability
•High end
•processor writes to memory simply and quickly
•e.g., RAM
•Middle range
•processor writes to memory, but slower
•e.g., FLASH, EEPROM
•Lower range
•special equipment, “programmer”, must be used to
write to memory
•e.g., EPROM, OTP ROM
•Low end
•bits stored only during fabrication
•e.g., Mask-programmed ROM
•In-system programmable memory
•Can be written to by a processor in the microcomputer
system
•Memories in high end and middle range of write ability
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26. Storage permanence
•Range of storage permanence
•High end
•essentially never loses bits
•e.g., mask-programmed ROM
•Middle range
•holds bits days, months, or years after memory’s power
source turned off
•e.g., NVRAM
•Lower range
•holds bits as long as power supplied to memory
•e.g., SRAM
•Low end
•begins to lose bits almost immediately after written –
refreshing needed
•e.g., DRAM
•Nonvolatile memory
•Holds bits after power is no longer supplied
•High end and middle range of storage permanence
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27. Equivalent Circuits of Memory Cells(1)
(a) DRAM (b) SRAM
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28. (c) Mask ROM (d) EPROM (e) FRAM
Equivalent Circuits of Memory Cells(2)
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29. Non Volatile -Read Only Memory
•Can be read from but not written to, by a
processor in an microcomputer system
•Traditionally written to, “programmed”, before
inserting to microcomputer system
•Uses
•Store software program for general-purpose
processor
•Store constant data (parameters) needed by
system
•Implement combinational circuits (e.g.,
decoders)
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30. Non-Volatile Memory
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31. NOR Based ROM Structure
31
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32. NOR Based ROM Structure
•The memory cells in a column makes a structure
like NOR gate.
•At a time, only any one row line (WL) to be
activated by “1”, rest all to be “0”
•It means, only one transistor in that column is
conducting while all others are open.
•At the cross point of activated WL and selected
BL, if active transistor exists, the BL pulls down
to “0”
•And if active transistor does not exist there, the
BL remains pull up to “1”
•The logic “1”is stored as absence of active
transistorand “0”as presence of active
transistor 32
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33. NAND Based ROM Structure
33
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34. NAND Based ROM Structure
•The memory cells in a column makes a structure
like NAND i.e. all transistor in series.
•At a time, only any one row line (WL) to be
activated by “0”, rest all to be “1”
•It means, only one selected transistor in that
column is open while all others are conducting.
•At the cross point of activated WL and selected
BL, if non-active transistor exists (shorted), the
BL pulls down to “0”
•And if non-active transistor does not exist there,
the BL remains pull up to “1”
•The logic “0”is stored as absence of active
transistor and “1”as presence of active
transistor 34
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35. NOR based Row Decoder
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36. Column Decoder
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37. Binary Tree Column Decoder
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38. Mask ROM
•Oldest technology
•Used for volume applications
•Long turnaround
•Used for applications such as embedded systems and
boot ROM
•Connections “programmed” at fabrication
•set of masks
•Originally “mask” used as last step in manufacturing
•Specify metal layer (connections)
•Lowest write ability
•only once
•Highest storage permanence
•bits never change unless damaged
•Typically used for final design of high-volume systems
•spread out NRE (non-recurrent engineering) cost for a low
unit cost
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39. Stick Diagram of MASK Programmed NOR
Based ROM
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40. Stick Diagram of MASK Programmed
NAND Based ROM
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41. Non Volatile –One Time Programmable
Memory
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42. One Time Programmable Memory
•Connections “programmed” after manufacture by
user
•user provides file of desired contents of ROM
•file input to machine called ROM programmer
•each programmable connection is a fuse
•ROM programmer blows fuses where connections
should not exist
•Very low write ability
•typically written only once and requires ROM
programmer device
•Very high storage permanence
•bits don’t change unless reconnected to
programmer and more fuses blown
•Commonly used in final products
•cheaper, harder to inadvertently modify
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43. One Time Programmable: Fuse Technology
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44. One Time Programmable: Anti-Fuse
Technology
44
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45. Antifuse
•When unprogrammed: Very high resistance
:Open
•When programmed: Very low resistance link
between two nodes : Short
•Compliment to Fuse technology
•Application of high voltage and current at
selective transistor converts highly resistive
amorphous silicon to conductive polysilicon
45
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46. OTP Memory
•When unprogrammed(originally) : all fuses
intact.
•Placing ‘1’ on row line will turn on transistor
connected to it and hence column line is pulled-
down to logic 0
•For logic “1’, the concerned fuse is blown by
applying high voltage, Here column line is pulled
up to ‘1’. 46
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47. EPROM & EEPROM:
Non Volatile Read-Write Memory
Floating gate
Source
Substrate
Gate
Drain
n
+
n
+_
p
t
ox
t
ox
Floating Gate Avalanche Injection
MOS Transistor
Schematic symbol
G
S
D
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48. Electrically Programmable Memory
•Programmable component is a
MOS transistor
•Transistor has “floating” gate
surrounded by an insulator
a.Negative charges form a channel
between source and drain
storing a logic 1
b.Large positive voltage at gate
causes negative charges to move
out of channel and get trapped in
floating gate storing a logic 0
c.(Erase) Shining UV rays on
surface of floating-gate causes
negative charges to return to
channel from floating gate
restoring the logic 1
d.An EPROM package showing
quartz window through which UV
light can pass
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49. Floating-Gate Avalanche Injection
MOS : FAMOS
5 V
-2.5 V
5 V
DS
Programming results in
higherV
T
.
12 V
10 V5 V
6 V
DS
Avalanche injection
Presence of Charge on Floating gate determines
the value (1 or 0)of memory cell
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50. Tunnelling in FAMOS
•High gate voltage attracts e tunnel to
Floating Gate
•Trapping of the electrons drops the effectivity
gate voltage (selflimiting)
•Trapped E a higher voltage is needed to
create channel higher threshold voltage
•exeffectivethreshold voltage is 7V 5V is not
high enough to turn it on
•Delta Vth = -DeltaQ/C_FQ (cap between
external contact and floating gate)
•SiO2 good insulator charge is trapped
forever!
•Problem: high voltage for programing : solution
materials and profile of dopants
50
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51. Erasable PROM -UVPROM
•Better write ability
•can be erased and reprogrammed thousands of times
•Reduced storage permanence
•program lasts about 10 years but is susceptible to
radiation and electric noise
•Typically used during design development
•Common technologies used UV light to erase complete
device
•Took about 10 minutes
•Holds state as charge in very well insulated areas of the
chip
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52. Electrically Erasable PROM -EEPROM
•Programmed and erased electronically
•typically by using higher than normal voltage
•can program and erase individual words
•Better write ability
•can be in-system programmable with built-in
circuit to provide higher than normal voltage
•writes very slow due to erasing and programming
•“busy” pin indicates to processor EEPROM still
writing
•can be erased and programmed tens of
thousands of times
•Storage permanence to EPROM (about 10 years)
•Far more convenient than EPROMs, but more
expensive
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53. Floating Gate Tunnel Oxide
FLOTOX EEPROM
Floating gate
Source
Substrate
p
Gate
Drain
n
1
n
1
FLOTOX transistor
Fowler-Nordheim
I-Vcharacteristic
20–30 nm
10 nm
-10 V
10 V
I
V
GD
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54. •Low and high threshold voltages for control gate voltage
A “Programmable-Threshold” Transistor
I-V Characteristic of Flash Memory
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Word line voltage

55. 55
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•If the EEPROM cell is programmed -> High
voltage applied to Gate -> Many electrons on
Floating gate -> when apply normal control
voltage on Gate-> the high number of electrons
has created a high threshold voltage for
transistor-> No channel will be formed between
source & drain -> No output current ->
interpreted as logic “0” bit stored
•If the EEPROM cell is in original state-> No high
voltage applied to Gate -> No electrons deposited
on Floating gate -> when apply normal control
voltage on Gate-> regular threshold voltage->
channel will be formed between source & drain ->
output current flows-> interpreted as logic “1” bit
stored

56. EEPROM Memory Cell : Two Transistors
•The NMOS is used for
selection and is controlled
by the word line. It can
withstand a part of the high
voltage and reduce the
probability of breakdown of
the ultra-thin oxide layer of
the floating gate tube.
•The floating gate transistor
serves as a memory and
stores data through a
tunnel oxide layer.
56
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57. Erase-write-read operations of
two transistor EEPROM memory cell
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Operation Gate Source Drain
Program +++Ve gnd +Ve
Erase -Veor gnd Floating Floating
Read +Ve Gnd( to sense
amplifier )
+Ve

58. EEPROM
•EEPROM is non volatile RWM very much useful
for general applications for example, electronic
lock, where the correct combination can be
stored for comparison with an input code, but
occasionally changed
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59. Flash Memory
While EPROM is reprogrammed bit-by-bit, flash
memory is reprogrammed in blocks, making it
faster. It is nonvolatile.
59
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60. 60
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61. Flash memory
•Single Transistor Cell
•Individually programmable.
•Globally erase.
•A single cell can not be erased and rewritten.
•When reprogramming, erase the entire data
and hence all bits are set to “1” and tehn
rewrite “0” at the individual cell as per need.
61
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62. Flash Cell
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63. NOR Based Flash Memory
•Erase all bits together
•Set the Source at 12V and
ready for erase pulse (known
duration)
•All T are erased at once 
100mS to 1 Sec
•Read all to see all is actually
erased
•Write “0” on required
bits
•Select the Word line and
apply high voltage
•Read the addressed
bit
•Select the bit line and sense
it
63
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64. Basic Operations in a NOR Flash
Memory―
Erase
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65. Basic Operations in a NOR Flash
Memory―
Write
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66. Basic Operations in a NOR Flash
Memory―
Read
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67. •https://www.iue.tuwien.ac.at/phd/windbacher
/node14.html
67
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68. 68
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69. NAND Flash Memory
Unit Cell
Word line(poly)
BL
Courtesy ToshibaGate
ONO
FG
Gate
Oxide
Select line
Select line
Source line
(Diff. Layer)
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70. NAND Flash Memory
Word linesSelect transistor
Bit line contact Source line contact
Active area
STI
Courtesy Toshiba
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71. Characteristics of State-of-the-art
NVM
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72. •Simple combinational Boolean network
•Only one word line selected at a time
•Active transistors exist at cross point
•Dynamic ROM
•use periodic precharge signal to reduce static power
Nonvolatile Memory
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73. •Initially, NMOS at every row-column intersection
•‘1’-bits are realized by omitting drain or source
connection
or gate electrode of corresponding NMOS
Layout example of a NOR ROM array
Layout of NOR ROM Array(1)
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74. •In reality, metal column lines laid out directly
on top of diffusion column to reduce horizontal
dimension
Layout of the 4-bit X 4-bit NOR ROM array (pp. 46)
Layout of NOR ROM Array(2)
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75. •Every two rows share a common ground
connection
•Every metal to diffusion contact shared by two
adjacent devices
Implant-mask Programmable NOR ROM
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76. •Based on implant-mask programming
•Raised threshold voltage >V
OH “1”-bit
•Non-implanted “0”-bit
•higher core density (smaller silicon area per
stored bit)
4-bit x 4-bit NOR ROM Array
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77. •Bit line : depletion-load NAND gate
•Deactivated transistor “1”-bit
•Shorted or on transistor “0”-bit
4-bit x 4-bit NAND ROM Array
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78. •Lowered threshold voltage < 0V “0”-bit
•Much more compact than NOR ROM
•Access time is slower than NOR ROM
Implant-mask layout of NAND ROM
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79. •Select a particular memory location in array
•Row address decoder example
Design of Row and Column Decoders(1)
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80. •ROM array and row decoder (two adjacent NOR
arrays)
Design of Row and Column Decoders(2)
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81. •Lower voltage for logic “0”
•Realized using same layout strategy as memory
array
Row Decoder for NAND ROM
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82. •Using NOR address decoder and NMOS pass
transistor
•Only one pass transistor turned on at a time
•2
M
(M+1) transistors required
Column Decoder(1)
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83. •Binary selection tree decoder
•NOR address decoder not needed
Reduce the number of transistors
significantly
•But, long data access time
Column Decoder(2)
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84. •Analyze the access time of a 32-kbit NOR ROM
array
Example 10.1(1)2
20 /
n ox
C A V 2
3.47 /
ox
C F cm 20 /Poly sheet resistance square
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85. •Assume 7 row address bits and 8 column address bits (128
rows and 256 columns)
•Calculate row resistance and capacitance
•Calculate row access time
Example 10.1(2)10.4 /
row ox
C C W L fF bit    (# ) ( ) 60 /
row
R of squares Poly sheet resistance bit    15.36
Ti
all columns
R R k   2.66
Ti
all columns
C C pF 0.38 15.53
row T T
t R C ns   
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86. •A more accurate delay: Elmore time constant for RC ladder
circuits
•Calculate column access time
128-input NOR gate representation
Example 10.1(3)256
11
20.52
k
row jk k jk j
kj
t R C ns where R R

   ,,
128 ( )
1.5
column gd driver db driver
C C C
pF
  
 ,,
0.0118 /
gd driver db driver
where C C pF word line
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87. •To calculate column access time, consider the worst-case signal
propagation delay τ
PHLfor below inverter
Example 10.1(4)18
column
t ns 38.5
access row column
t t t ns  
(using eq. 6.18: t
PHL)
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88. •One transistor with floating gate
•Memory cell can have two states (two threshold)
•Electron accumulated at the floating gate higher threshold “1”
state
•Electron removed from the floating gate lower threshold “0” state
Hot electron injection mechanism Fowler-Nordheim tunneling mechanism
(Data programming) (Data erasing)
10.5 Flash Memory
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89. Q
FC: charge stored at floating gate
C
total: total cap.
C
FC: cap. between floating and control gate
C
FS, C
FBand C
FD: cap. between floating gate and source, bulk and drain
V
CGand V
D: voltage at control gate and drain
V
T(FG) : threshold voltage to turn on the floating gate transistor
Equivalent Capacitive-Coupling CircuitFG FC FD
FG CG D
total total total
QC C
V V V
C C C
   total FC FS FB FD
C C C C C    ( ) ( )
total FG FD
T T D
FC FC FC
CQ C
V CG V FG V
C C C
   ()
FG
T
FC
Q
V CG
C

  
V
FGby capacitive coupling
after V
CG& V
Dapplied
min. V
CGto turn on the
control gate transistor
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90. •Bias conditions and configuration of NOR Cells
•F-N tunneling mechanism for erase operation
•Hot-electron injection mechanism for programming operation
NOR Flash Memory Cell
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91. Bias Conditions of NOR Cell
Signal
Operation
Erase Programming Read
Bit line 1 Open 6V 1V
Bitline 2 Open 0V 0V
Source line 12V 0V 0V
Word line 1 0V 0V 0V
Word line 2 0V 12V 5V
Word line 3 0V 0V 0V
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91

92. •Cross-section view and configuration of NAND
cells
•F-N tunneling mechanism for erase
•F-N tunneling mechanism for program
•Slower programming and read speed
but smaller area than NOR cell structure
NAND Flash Memory Cell
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92

93. Bias Conditions of NAND Cell
Signal
Operation
Erase Programming Read
Bit line 1 Open 0V 1V
Bitline 2 Open 0V 1V
Select line 1 Open 5V 5V
Word line 1 0V 10V 5V
Word line 2 0V 10V 5V
Word line 3 0V 10V 5V
Word line 4 0V 10V 5V
Word line 5 0V 20V 0V
Word line 6 0V 10V 5V
Word line 7 0V 10V 5V
Word line 8 0V 10V 5V
Select line 2 Open 0V 5V
Source line Open 0V 0V
p-well 2 20V 0V 0V
n-sub 20V 0V 0V
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93

94. Comparison between NOR and NAND
NOR NAND
Erase method F-N tunneling F-N tunneling
Programming method Hotelectron injection F-N tunneling
Erasespeed Slow Fast
Program speed Fast Slow
Readspeed Fast Slow
Cell size Large Small
Scalability Difficult Easy
Application Embedded system Mass storage
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94

95. •Effective memory density can be improved
•Possible state number limited by
•Available charge range
•Accuracy of programming and read operations
•Disturbance of state over time
Threshold voltage distribution of 2bits/cell storage
Multilevel Cell Concept
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95

96. •On-chip charge pump used to generate programming voltage
•Chain of diode and cap. to charge or discharge each half cycle
Flash Memory Circuit( ( 1)) ( ( ))
out in DD T DD T
V V V V MN V V MNn     
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Semiconductor Memory
96

97. Flash Memory
•Extension of EEPROM
•Same floating gate principle
•Same write ability and storage permanence
•Fast erase
•Large blocks of memory erased at once, rather
than one word at a time
•Blocks typically several thousand bytes large
•Writes to single words may be slower
•Entire block must be read, word updated, then
entire block written back
•Used with embedded microcomputer systems
storing large data items in nonvolatile memory
•e.g., digital cameras, MP3, cell phones
Semiconductor Memory
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97

98. Summery
Semiconductor Memory
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98

99. Semiconductor Memory
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99

100. Memory Comparison….
•Traditional ROM/RAM
distinctions
•ROM
•read only, bits stored
without power
•RAM
•read and write, lose
stored bits without
power
•Traditional distinctions
blurred
•Advanced ROMs can be
written to
•e.g., EEPROM
•Advanced RAMs can
hold bits without power
•e.g., NVRAM
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100

101. Volatile Read/Write Memory
•SRAM: Static RAM
•Consists of a latch, Memory cell uses flip-flop to store bit,
Requires 6 transistors
•Don’t need the refresh operation
•High speedand low power consumption it is mainly used for
cache memory and memory in hand -held devices
•DRAM: Dynamic RAM
•Memory cell uses A capacitor to store data, and a transistor to
access the capacitor
•More compact than SRAM but Slower to access than SRAM
•Retains data for only 2 –4 ms
•“Refresh” required due to capacitor leak
•word’s cells refreshed when read
•Low cost, and high densityit is used for main memory Semiconductor Memory
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101

102. •FRAM
•Similar structure to that of DRAM
•the ferroelectric capacitor where the cell data
are modified by changing the polarization of
ferroelectric material
•PSRAM: Pseudo-static RAM
•DRAM with built-in memory refresh
controller
•Popular low-cost high-density alternative to
SRAM
•NVRAM: Nonvolatile RAM
•Holds data after external power removed
•Battery-backed RAM
•SRAM with own permanently connected battery
•writes as fast as reads
•no limit on number of writes unlike nonvolatile ROM-
based memory
Semiconductor Memory
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102

103. Static Random Access Memory
SRAM

104. System Level View of SRAM
Semiconductor Memory
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104

105. SRAM Read Timing
•t
AA(access time for address): how long it takes
to
get stable output after a change in address.
•t
ACS(access time for chip select): how long it
takes
to get stable output after CS is asserted.
•t
OE(output enable time): how long it takes for
the
three-state output buffers to leave the high-
impedance state when OE and CS are both
asserted.
•t
OZ(output-disable time): how long it takes for
the
three-state output buffers to enter high-
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105

106. SRAM Read Timings
Semiconductor Memory
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106

107. Latch as Memory Element
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107

108. SRAM Cell Technologies
Thin Film Transistor
Which one is compact in size compared to rest all?
Resistive load SRAM
UndoppedPolysilicon Resistors stacked on top of
the cell using double-polysilicon technology i.e. one
layer of polysilicon for gates of enhancement MoS
and the second layer for resistors.
Hence, area requirements of four transistors only
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108

109. Types of SRAM Cell
•Resistive Load nMOS SRAM
•Smallest in Size
•Trade off in resistance value
•Resistance value low for acceptable noise margin and pull up times
•Resistance value high to reduce stand by current and power
•High Power
•Depletion Load nMOS SRAM
•Comparatively small in size
•Better static characteristics and noise margin
•Not suitable for high density SRAM
•Full CMOS
•The lowest static power
•Superior noise margin
•Superior sweeting speed
•Comparatively large area
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109

110. Basic SRAM Cell -6T
Semiconductor Memory
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110

111. Basic states of SRAM
•bistable(cross-coupled) INVs for storage
•access transistors MAL & MAR to access the
stored data for read and write
•word line, WL, controls access
•Hold
•word line = 0, access transistors are OFF
•data held in latch
•Write
•word line = 1, access transistors ON
•bit and bit_baract as input lines
•new data (voltage) applied to bit and bit_bar
•data in latch is overwritten with new value
•Read
•word line = 1, access transistorsON
•bit and bit_baract as output lines
•bit and bit_barare read by a sense amplifier
•Sense Amplifier
•basically a simple differential amplifier
comparing the bit and bit_bar
•if bit>bit_bar, o/p is 1, if bit<bit_bar, o/p is 0
•allows o/p to be set quickly without fully
charging/discharging bit line
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111

112. SRAM Write Circuit
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112

113. When WL=1
Read Enabled….
Reading ‘1’
•Data is ‘1’ i.e. Q=1, QB=0
•BL and BLB are already precharged.
•No voltage difference between BL and Q
•Voltage Difference between BLB (1) and QB (0)
•BLB starts discharging through QB.
•BLB voltage starts decreasing.
•BL > BLB so output ‘1’
•Sense amplifier acts as comparator and senses
this difference and declares the bit as ‘1’
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113

114. When WL=1
Read Enabled….
Reading ‘0’
•Data is ‘0’ i.e. Q=0, QB=1
•BL and BLB are already precharged.
•No voltage difference between BLB and QB
•Voltage Difference between BL (1) and Q (0)
•BL starts discharging through Q.
•BL voltage starts decreasing.
•BL < BLB so output ‘0’
•Sense amplifier acts as comparator and senses this
difference and declares the bit as ‘0’
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114

115. When WL=1
Write Enabled….
Writing ‘1’
•Assuming Q=0, QB=1
•BL and BLB are inputs so BL applied ‘1’ and
BLB applied ‘0’.
•BLB is ‘0’ and QB is VDD so it starts
discharging.
•When QB decreases to less than Vt,
•PDL is OFF and PUL is ON.
•Hence Q is Vdd
•i.e. Q= 1 and meanwhile QB reaches to 0
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115

116. When WL=1
Write Enabled….
Writing ‘0’
•Assuming Q=1, QB=0
•BL and BLB are inputs so BL applied ‘0’ and
BLB applied ‘1’.
•BL is ‘0’ and Q is VDD so it starts discharging.
•When Q decreases to less than Vt,
•PDR is OFF and PUR is ON.
•Hence QB is Vdd
•i.e. QB= 1 and meanwhile Q reaches to 0
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116

117. Design Criteria for CMOS SRAM Cell
•ThemajordesigncriteriatodecideW/Lof
differenttransistorsare:
•Thedata-readoperationshouldnotdestroythestoredinformation
intheSRAMcell
•Thecellshouldallowmodificationofthestoredinformationduring
thedata-writephase
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117

118. REFRESH!
Semiconductor Memory
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118

119. Read 0 Operation
•No variation in C’ but C drops through M3
and M1
•As CC is very high, C drops slightly , few
hundred millivolts only but sense amplifier
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119

120. Read 0 Operation
Semiconductor Memory
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120

121. Write ‘0’ Operation, ‘1’ stored in cell
•Our goal is to make V1=> 0V and V2 =>VDD.
•Now We have planned M4 & M2 such that, we
can’t increase V2 more than Vth of M1. It
means that we can not start increasing V2
using pair of M4-M2 but we should start
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121

122. Write ‘0’ Operation, ‘1’ stored in cell
Semiconductor Memory
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122

123. •https://xtronics.com/wiki/How_EPROMS_Wor
k.html
123
Semiconductor Memory
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124. SRAM Design Considerations

125. •Stored data can be retained indefinitely
•Simple latch with two stable operating points
•Two access switches to connect 1-bit SRAM
•Poly resistor load inverter structure is more compact cell size
(resistor stack on top of cell)
•Load R trade off : low power wider noise margin, high
speed
Symbolic representation Generic topology of SRAM Resistive-load
SRAM
Static Random Access Memory(1)
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125

126. •Depletion-load NMOS SRAM
•Six-transistor
(one poly and one metal layer)
•Cell size relatively small
•Static characteristics and noise
margins better than resistive-load cell
•Static power consumption
•Full CMOS SRAM
•Most popular
•Lowest static power
•Superior noise margins and switching
speed
10.3 Static Random Access Memory(2)
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126

127. •Very small static power dissipation (limited by leakage current)
•High noise immunity (large noise margin)
•Ability to operate at lower supply
•Disadvantage : cell area slightly larger, latch-up phenomena
Full CMOS SRAM Cell(1)
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127

128. Layout of CMOS SRAM cell Layout of a 4-bit X 4bit SRAM
array, consisting of 16 CMOS
SRAM cells
Full CMOS SRAM Cell(2)
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128

129. •Two basic requirements which dictate W/L ratio
•Non-destructive data read operation
•Modify stored data during write phase
•Read Operation (0 stored)
•M3 and M1 conduct some
current
•V
Cc
drops slightly and V
1
increases
• not to turn on M2
•M3 in Saturation and M1 in
linear
CMOS SRAM Cell Design Strategy(1)1,max ,2T
VV ,3 ,1 22
1 , , 1 1
( ) (2( ) )
22
nn
DD T n DD T n
kk
V V V V V V V     ,3 , , 3
2
,1 ,
1
2( 1.5 )
( 2 )
n DD T n T n
n DD T n
W
k V V VL
Wk V V
L







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Semiconductor Memory
129

130. •Write 0 operation (initially, 1 was stored at node 1)
•V
1must be reduced below V
T,2M2 turns off, V2 rises and V1 falls
•When V
1=V
T,n, M3 in linear
& M5 in saturation
CMOS SRAM Cell Design Strategy(2),5 ,322
, , , ,
(0 ) (2( ) )
22
p n
DD T p DD T n T n T n
k k
V V V V V V     ,5 ,,
2
,3 ,
2( 1.5 )
()
p DD T n T n
n DD T p
k V V V
k V V


 ,,5
2
,
3
2( 1.5 )
()
DD T n T nn
p DD T p
W
V V VL
W VV
L









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130

131. •Word line selected by row
address
•Cell data kept during read
operation
•Boosted voltage not required
•Address multiplexing scheme is
not used (fast access time than
DRAM)
•Depend on applications
•ultra low power : load transistor
turns off during read operation
•high speed : remains on
Memory Structure of SRAM
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131

132. •Read operation
•Word line enable
•One bit line discharge
(voltage change of bit line is very
small)
•Sense amp. detect the voltage
difference on bit line
•Multi-stage amp. is used to improve
read speed
•Write operation
•Word line selected by row address
•Write buffer write data into cell
•Write buffer has larger current
driving capability than cell
•Write is faster than read
Operation of SRAM
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132

133. •TTL level converts into CMOS level signal
•Internal voltage regulator to reduce power
dissipation
to improve reliability
SRAM Read Operation
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133

134. •Major portion of standby current
•Standby power is key parameter for low power design
•High threshold
reduction of leakage degradation of performance
I
j: junction current
data “1” to substrate
I
nsuband I
psub: subthreshold
leakage
turn off NMOS and PMOS
I
tunneling: tunneling current
cross thin gate oxide
Leakage Currents in SRAM Cells
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134

135. •Current-mode sense amp
widely used in SRAM
improve signal sensing
speed independent of bit
line cap.
•Signal line connect to source
of latch transistor
•Current difference appears on
DL and DL
•Open-loop gain
•Current-mode sense amp:
Drawback-larger power
consumption
SRAM Read/Write Circuits( 3) ( 4)
( 1) ( 2)
mm
open loop
mm
g m g m
Gain
g m g m




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135

136. SRAM Cell at Low Supply Voltage
•SRAM cell susceptible to variabilities
•Due to minimum device size to a minimize area
•Threshold voltage variation covered in Ch. 3 plus layout induced
threshold voltage variation
•PMOS pair (M5, M6) in SRAM cell-different V
Tdue to NBTI
•NMOS pair (M1, M2) in SRAM cell-different V
Tdue to PBTI+ Vn -
invL - Vn +
invR
word line
bit line
① ①
bit line
Static noise margin (SNM)
A noise tolerant voltage before
the stored data flip
Equivalent ckt to measure SNM
6-T SRAM cell at low supply
voltage degrades SNM
V
n: DC noise, SNM: min. DC noise which flips
the state of SRAM cell during read operation
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136

137. SNM Variation due to DC Noise
•How to measure SNM graphically
SNM: The length of side of the smaller nested square in the two
openings of butterfly curve
Before two V
ns are fed: SNM=V
S
After V
ns are fed: stable point A and unstable point B meets at D
More V
ns are applied: one common point C & the stored bits are flipped
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137

138. SRAM Cell Writability
•Write-trip point
•A metric for writability
•Max. bit line voltage to flip
the state of the SRAM cell
•Primarily determined by the
pull-up ratio of SRAM cell (Ex:
(W/L)
5/(W/L)
3)
•Variability tolerant 6T
SRAM cell
•Trade off bw. read stability
and writability
•M
3& M
4:
SNM , writability
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138

139. 8T SRAM Cell
•No secondary power
supplies
•Decouples the SRAM cell
nodes from the bit line
which enables balancing the
read & write modes
•Read operation doesn’t
affect the stored data
•6T cell has the worst SNM in
read operation where the
pass gate transistor
increases the voltage at the
‘0’ stored
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139

140. Dynamic RAM
Design Considerations

141. Pin name Definition Function
CLK Clock input
Referencesystem clock for the operation and data
communication
CKE Clock Enable Control the clock input
CS Chip Select Activatethe DRAM device from a memory cluster
RAS Row Address Strobe Latch row address and start the cellcore operation
CAS Column Address Strobe
Latch column address and start the data communication
operation
WE WriteEnable Activate the write operation
A0 to A14 Address input Select a data bit
DQ0 to DQ15 Data input and output Communicatedata with external devices
DQMU/DQML
DQ Mask for Upper (Lower)
Byte
Mask bytedata from the operations
V
DD/V
SS Power pins Power for DRAM core and peripheral circuits
V
DDQ/V
SSQ Power pins Power for DQ circuits
NC No connection
Definition and Function of DRAM Pins
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141

142. Historical Evolution of DRAM Cell(1)
•Four-transistor DRAM cell
•Operations are similar to SRAM cell
•Two storage nodes
•Periodically refresh is required
•Non-destructive read operation
•Three-transistor DRAM cell
•One storage node
•One Tr. each for “read” and “write”
•Non-destructive read operation
•Two bit lines and two word lines
(additional contacts increase area)
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142

143. Historical Evolution of DRAM Cell(2)
•Two-transistor DRAM cell
•Explicit storage cap.
•Destructive read operation
(share with the bit line)
•Two bit lines and one word line
•One-transistor DRAM cell
•Industry-standard DRAM cell
•Destructive read operation
(share with the bit line)
Charge restoring operation required
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143

144. •With only one transistor and one capacitor
•Smallest area of the all DRAM cells.
•Destructive “read” operation
major effort : large cap. cell with minimized area
(a) DRAM cell with a stacked cap. (b) DRAM cell with a trench
cap.
DRAM Cell Types
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144

145. •Typical 3-T DRAM cell and voltage waveforms
Operation of Three-Transistor DRAM Cell
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145

146. •Base on two-phase
non-overlapping clock
scheme
Φ
1: prechargephase
Φ
2: active phase
Prechargesignal PC goes up
MP1 and MP2 are activated
C
2and C
3are charged up
(Steady-state values)
Precharge Events
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146

147. Write “1” and Read “1” Operations
•Write “1”
DATA is low D
inremains
high
M1 turns on (WS is high)
C
2shared with C
1
C
1charge up to high
(M2 is conducting)
•Read “1”
RS is high M3 turns on
M2 and M3 create conducting
path from C
3to GND
C
3discharges
•Non-destructive read operation
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147

148. Write “0” and Read “0” Operations
•Write “0”
DATA is high D
ingoes low
M1 turns on (WS is high)
C
1discharges
(M2 turns off)
•Read “0”
RS is high M3 turns on
No conducting path
C
3does not discharge
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148

149. •One explicit storage cap. and one access
transistor
•The most widely used storage structure
•Bit lines are folded and precharged to half-V
DD
improve noise-immunity & reduce power consumption
•Operation : “read”, “write”, “refresh”
Operation of One-Transistor DRAM Cell
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149

150. •DRAM cell array with control circuits
•Latch amplifier to sense the small signal difference
•Bit lines and sensing nodes set to half-V
DDthrough equalizer
1-T DRAM Structure
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Semiconductor Memory
150

151. •C
Sshared with C
BL(=initially half V
DD)
•C
S : V
DD½V
DD+ΔV (destructive)
•BL and BLB voltage difference amplified
•BLB GND, BL V
DD
storage node is recovered (restoring)
•Column switch is enabled by column
decoder (BL BL_IO, BLB BL_IOB)
•Read Amp. amplifies the voltage
difference
V
PP=V
DD+V
thfor full charge restoration
PSA and PSAB are sequentially activated to
reduce charge injection and short circuit
current
DRAM Read Operation2
S DD
BL S
CV
V
CC

 PEQ/PSAEQ
PISOi/PISOj
Word Line
BL/BLB
PSA
PSAB
Column Select
Dout_IO/
Dout_IOB
Dout_IO
BL_IOB
BL_IO
BLB
S
VDD
VPP
VDD
VPP
VDD
1/2VDD
VDD
VDD
VDD
VDD
VDD
PISOi
PISOj
BL_IO/BL_IOB
BL
charge sharing between the cell and bit line capacitances
activation of
bit line sense amplifier
cell data restoring
(a)
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151

152. •Identical sequence to normal
read operation
•Strong write driver (buffer)
to drive BL_IO, BL_IOB line
cap.
faster than read operation
•Column switch is selected by
column decoder
•Bit line and cell data changed
DRAM Write Operation
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152

153. •single bit access (different row and column addresses)
•Operation uses address multiplexing scheme (RAS and CAS)
reduce the chip package size
•RAS pull down operation start
•Falling edge of CAS data (from same word line) selected
•RAS, CAS prechargebefore new data access
•t
RAC: memory read latency, time to read data from falling of
RAS
•Length of word line is determined by refreshcycle constraint
Asynchronous DRAM Mode(1)
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153

154. •page access
•keep the row address
•read cell of same row address
•faster read operation
•extened data-out(EDO)
•new column address is
captured at rising edge of CAS
•Read data maintain during
precharge time
•Fastest read opertaion
Asynchronous DRAM Mode(2)
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154

155. •Four bit burst read
•Read frequency improve with
use of the system clock
•At falling edge, control signal
and addresses become active
•Pipelined based on clock to
improve throughput
•Use both of edges to improve
bandwidth (Dual Data Rate)
•Serial mode read
•Use small signal swing and
clock recovery scheme to
maximize the frequency
•Send control input as packet
•Send out data in a serial form
Synchronous DRAM Mode
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155

156. •Contact and bit line share
by two adjacent cells
I
sub: leakage through cell transistor
I
tunneling: tunneling through thin
dielectric
I
j: junction leakage at storage node
I
cell-to-cell: leakage across the field oxide
•I
subdepend on V
th
increase V
SBto reduce I
sub
•I
tunnelingis a serious
issue
because thickness of
dielectric is reduced to
increase cell cap.
Leakage Currents in DRAM Cellsleakage sub tunneling j cell to cell
I I I I I

   
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157. •ROR(RAS-only refresh) refresh
•Read and restore operation
•Does not send data out
•similar to normal read
operation
•CBR(CAS-before-RAS) refresh
•row address generated by on-
chip counter
•performed periodically
•Self refresh
•period set according to
operating condition
•row address and control
signal generated by internal
circuit
Refresh Operation
ROR refresh mode
CBR refresh mode
Self refresh mode
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158. •Logic level of system board and memory chip are different
required to convert logic levels input/output buffers
•Input buffers
inverter type latch type differential amp type
DRAM Input/Output Circuits(1)
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159. Characteristic Comparison of Input Buffers
Buffer type
Inverter Latch Differential
Logicthreshold determination
(V
IHand V
IL)
By W
P/W
N
ratio
By V
ref By V
ref
Speed Slow Fastest Fast
Standby current Small Smallest Large
Sensitivity to V
DDandtemperature Large Small Small
Noise immunity Bad Good Good
Constraint None
Prechargeand
activationsignals
needed
None
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160. •Memory output buffers
•Need to drive large cap.
•Keep a high-impedance when chip is not selected
to prevent interference of output
PMOS pull-up structure NMOS pull-up structure
DRAM Input/Output Circuits(2)
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161. •To select cell from 2
2M
memory array, M address bits are
needed
•Practically, M transistors in series is impossible
decoding scheme is composed of pre and main decoder
DRAM Decoder(1)
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162. •V
PPfor full restoration
•Output of predecoder
boosted by level shifter
•Self-bootstrapped driver for
transferring to highly cap.
without signal degradation
•Voltage of C when main
decoder is selected
DRAM Decoder(2)2
2
MN
C PP DD TN PP
MN Cparasitic
C
V V V V V V
CC
     

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163. •To detect signal difference on data lines
•Current-mirror differential
•Popular and good common-mode rejection
ratio
•Large area and large power consumption
•Full CMOS latch type
•High speed, small area and low power
•Prechargesignal required
•operation cannot be reversed
•Semilatchtype
•Between current-mirror type and full CMOS latch
type
Voltage Sense Amplifiers
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164. •Lowering voltage to reduce power consumption
•V
INT(internal voltage generator)
reduce operating current
Internal Voltage Regulator Circuit
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165. •Folded bit line structure with half V
DDsensing
scheme
•Improve noise immunity and low power consumption
•Reduce electric field across thin dielectric
bias ckt driver simulated output
waveforms
Half V
DDVoltage Generator
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166. •Subthreshold current is major source of charge
decay
•Negative voltage substrate increase threshold voltage
reduce load cap. of bit line
Negative Substrate Bias Voltage
Generator(1)T
SB
SB
V
V
V



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167. Timing diagram
Circuit diagram
Simulated waveforms
Negative Substrate Bias Voltage
Generator(2)
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168. •Hysteresis characteristic of a ferroelectric cap.
•Total charge varies as function of applied
voltage
10.6 Ferroelectric Random Access Memory
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169. •Similar to DRAM except plate line
Step-sensing scheme
C
1and C
0: linearly
modeled
ferroelectric cap
Structure and Operation of FRAM1
1
1
0
0
0
DD
BL
DD
BL
C
VV
CC
C
VV
CC




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170. •Step-sensing scheme cause reliability issues
•Pulse sensing scheme also used with read speed penalty
•Fatigue
•Capacitance charge gradually degraded with repeated use
•Imprint
•Ferroelectric cap tends to stay at one state preferably when state
maintained for a long time
Problems of FRAM
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171. Characteristic Summary of Memory Devices
Memory type
DRAM SRAM UV EPROM EEPROM Flash FRAM
Datavolatility Yes Yes No No No No
Data refresh operationRequired No No No No No
Cell structure 1T-1C 6T 1T 2T 1T 1T-1C
Cellsize(F
2
)
(F: min. feature size)
6~8 80~100
4~5(NAND)
9~10(NOR)
Cell density High Low High Low High High
Power consumption High High/low Low Low Low High
Read speed(latency)~50 ns ~10/70 ns ~50 ns ~50 ns ~50ns ~100 ns
Write speed ~40 ns ~5/40 ns ~10 μs ~5 ms ~(10 μs-1ms)~100 ns
Endurance High High High Low High High
Cost Low High Low High Low Low
In-system writabilityYes Yes No Yes Yes Yes
Power supply Single Single Single Multiple Single Single
Application example
Main
memory
Cache/PDAs
Game
machines
ID card
Memory card
solid-state
disk
Smart card,
digital
camera
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172. Thanks!