A low power area efficient paralle adder

ppt

1. Department of Electronics & Communication Engineering PRESENTED BY, Name: RAHUL.S.S 727621MCO004 ME- COMMUNICATION SYSTEM GUIDED BY, Dr.N.SARAVANAKUMAR ASSOCIATE PROFESSOR ECE Mini Project Presentation Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 1 Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022

2. Contents 2 Introduction Literature survey Problems identified Objective of the project Block diagram Tool to be used Results Work plan References Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022

3. Introduction 3 Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 1. Need for fault-tolerant voters in the logical circuits. 2. Among different adder designs, the carry look-ahead-based architectures are considered as one of the fastest adders to be enhanced for multiple-error resilience. 19 July 2022

4. Literature Survey S.No Name of the Author(s) Title of the paper Journal & year of Publications System Description Methodology proposed 1 Mojtaba Valinataj , Mahboobeh Mirshekar , Hamid Jazayeri Novel low-cost and fault-tolerant reversible logic adders International Journal of Computer and Electrical Engineering 2015 Some novel fault-tolerant reversible adders were presented with the aim of being both low-cost and parity preserving New low-cost reversible gate 2 S hailja Shukla, Tarun Verma and Rita Jain Design of 16 Bit Carry Look Ahead Adder Using Reversible Logic International Journal of Electrical, Electronics and Computer Engineering 2 014 carry look ahead adder using reversible logic. 90nm CMOS technology 4 Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022

5. Literature Survey S.No Name of the Author(s) Title of the paper Journal & year of publications System Description Methodology proposed 3 Deepthi Obul Reddy, P.Ramesh Yadav Carry Select Adder with Low Power and Area Efficiency International Journal of Engineering Research and Development 2 012  Reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay  CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture 4 A.Maheshwari , W. Burleson, R. Tessier, IEEE Trans. On Very Large Scale Integ. (VLSI) Syst. 12 (3) (2004) Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits IEEE Trans. On Very Large Scale Integ. (VLSI) Syst. 2004 In this paper a method to estimate fault tolerance in terms of well-known metric is presented Fault tolerance and power dissipation estimation methodology Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 5 19 July 2022

6. Literature Survey S.No Name of the Author(s) Title of the paper Journal name & year of publications System Description Methodology proposed 5 M. Valinataj , Saeed Safari Fault tolerant arithmetic operations with multiple error detection and correction 22th IEEE Int. Symp . on Defect and Fault Tolerance in VLSI Systems (DFT'07), Sep. 2007, pp. 188–196. In this paper a new scheme is presented to design the fault-tolerant arithmetic operators that can tolerate against multiple simultaneous errors. Improved parity prediction scheme logic fault method. 6 D.P. Vasudevan, P.K. Lala, J.P. Parkerson Self checking carry-select adder design based on two-rail encoding IEEE Trans. Circuits Syst . Regul . Pap. 54 (12) (2007) 2 696–2705 Dec. [ A technique for implementing self-checking carry-select adders of arbitrary size using a 2-bit self-checking carry-select adder as the component is proposed 0.5- m CMOS technology. Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 6 19 July 2022

7. Literature Survey S.No Name of the Author(s) Title of the project Journal name & year of publications System Description Methodology proposed 7 V. Ocherenty Self-checking arithmetic logic unit with duplicated outputs 16th IEEE Int. On-Line Testing Symp . (IOLTS'10), 2010, pp. 202–203. In this paper we present a new self checking ALU with duplicated functional outputs fault-tolerant arithmetic operators that can tolerate against multiple simultaneous errors 8 V. Khorasani , B.V. Vahdat, M. Mortazavi Analyzing area penalty of 32-bit fault tolerant ALU using BCH code 14th Euromicro Conf. On Digital System Design (DSD'11), 2011, pp. 409–413. In this paper we have presented a hardware implementation of 32-bit Fault-tolerant ALU (Arithmetic and Logic Unit) which is compared with the current techniques various fault tolerant methods which are used for removing the faulty data in the ALU Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 7 19 July 2022

8. Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 8 S.No Name of the Author(s) Title of the project Journal name & year of publications System Description Methodology proposed 9 R. Parhi , C.H. Kim, K.K. Parhi Fault-tolerant ripple-carry binary adder using partial triple modular redundancy (PTMR) EEE Int. Symp . On Circuits and Systems (ISCAS'15), 2015, pp. 41–44. This paper addresses the design of arithmetic computing systems that can achieve the same reliability as that of TMR systems but with significantly less overhead A novel method of redundancy, referred to as partial triple modular redundancy (PTMR) 10 A. Namazi, Y. Sedaghat , S.G. Miremadi , A. Ejlali , A low-cost fault-tolerant technique for carry look-ahead adder 15th IEEE Int. On-Line Testing Symp . (IOLTS'09), 2009, pp. 217–222. In this paper, a new low-cost fault tolerant technique is proposed which can be applied either as an error correction (LCEC) or an error detection technique (LCED) low-cost fault-tolerant Carry Look-Ahead (CLA) adder Literature Survey 19 July 2022

9. Problems identified Multiple-error occurrence because of multiple transient faults is highly probable in digital circuits. The voters used in existing is multiple-error tolerant carry look-ahead adders only detect single errors and cannot mask any error inside their logic circuit. 9 Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022

10. Objectives of the Project To design the multiple-error tolerant carry look-ahead adders, which detects the multiple errors. To design the new customized voters to reduce the area and power dissipation. 10 Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022

11. PPU CCU SUMMATION C[4:0] Cin C[4] P[ 3:0] P [3:0] G [3:0] A[3:0] B[3:0] Sum[3:0] C[4] = Carry C[3:0] Pi = Ai ^ Bi Gi = Ai & Bi C(i+1) = Gi ^ ( Pi & Ci ) Co = Cin Sum[ i ] = Pi ^ Ci Conventional 4 bit CLA Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 11 19 July 2022

12. CARRY EQUATIONS: For 4 bit CLA: Trad . 4 bit CLA B[3:0] A[3:0] Cout Cin Sum[3:0] PPU Pi = Ai ^ Bi Gi = Ai & Bi B[3:0] A[3:0] P[3:0] G[3:0] C0 = Cin C1 = G0 + P0C0 C2 = G1 + P1G0 + P1P0C0 C3 = G2 + P2G1 + P2P1G0 + P2P1P0C0 C4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0 Symbolic Representation: 12 Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022

13. RTL Schematic of Conventional 4 bit CLA: Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022 13

14. C1[0] Cin =1 A[0] B[0] Actual C1[1] C1[1] = A[0] ^ B[0] 1 1 1 1 1 1 1 1 1 1 1 1 1 As per approximations Cin =0 results in no error ,where as an error in the sum occurs 4 bit adder only when A[0], B[0], Cin = 1. ERROR POSSIBILITIES For 4 bit CLA: Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022 14

15. 30 June 2022 LOW POWER HIGH SPPED PARALLEL ADDER WITH FAITHFUL APPROXIMATION FOR IMAGE BLENDING 15 CARRY GENERATOR: Gi= A.B - Irrespective of Cin if we add A and B it must produce carry. C ARRY PROPOGATOR: Pi= A ⊕ B - Whenever the Cin is 1 if we add A and B it must produce carry. A B Cin Cout TYPE 1 1 1 1 1 P 1 1 1 1 P 1 1 1 G 1 1 1 1 G/P A B Cout 1 1 1 1 Pi= A ⊕ B A B Cout 1 1 1 1 1 1 Gi= A.B

16. 16 Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022 C0 = Cin => C1 = G0 + P0C0 = 0 + 1.0 => C2 = G1 + P1G0 + P1P0C0 = 0 + 1.0 + 0.0.0 => 0 C3 = G2 + P2G1 + P2P1G0 + P2P1P0C0 = 1+0.0+0.1.0+0.1.1.0 => 1 C4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0 = 1+0.1+0.0.0+0.0.1.0+0.0.1.1.0 => 1 Here the Cin is 0 , if we add A3 and B3 it gives carry ,so according to the generator A3.B3 = 1.1 =1 the actual output is also1 so no error occur. P0= A0 ⊕ B0 = 0 ⊕ 1 = 1 P1= A1 ⊕ B1 = 0 ⊕ 1 = 1 P2= A2 ⊕ B2 = 1 ⊕ 1 = 0 P3= A3 ⊕ B3 = 1 ⊕ 1 = 0 A3 A2 A1 A0 A= 1 1 0 0 B3 B2 B1 B0 B= 1 1 1 1 1 0 1 0 When Cin =0 G0= A0 . B0 = 0 .1 = 0 G1= A1 . B1 = 0 .1 = 0 G2= A2 . B2 = 1 .1 = 1 G3= A3 . B3 = 1 .1 = 1 C0 = Cin =0 C1= 0 C2= 0 C3= 1 C4= 1

17. 17 C0 = Cin => 1 C1 = G0 + P0C0 = 0 + 1.1 => 1 C2 = G1 + P1G0 + P1P0C0 = 0 + 1.0 + 1.1.1 => 1 C3 = G2 + P2G1 + P2P1G0 + P2P1P0C0 = 0+ 1.0+1.1.0+1.1.1.1 => 1 C4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0 = 1+0.0+0.1.0+0.1.1.0+0.1.1.1.1 => 1 Here the Cin is 1 if we add A3 and B3 it produce carry ,so according to the propagator A3^B3 = 1^1 =0 ,but the actual output is 1 so error occur. G0= A0 . B0 = 0 .1 = 0 G1= A1 . B1 = 0 .1 = 0 G2= A2 . B2 = 1 .1 = 1 G3= A3 . B3 = 1 . 1 = 1 P0= A0 ⊕ B0 = 0 ⊕ 1 = 1 P1= A1 ⊕ B1 = 0 ⊕ 1 = 1 P2= A2 ⊕ B2 = 1 ⊕ 1 = 0 P3= A3 ⊕ B3 = 1 ⊕ 1 = 0 A3 A2 A1 A0 A= 1 1 0 0 B3 B2 B1 B0 B= 1 1 1 1 1 1 0 0 When Cin =1 C0 = Cin =1 C3= 1 C4= 1 C2= 1 C1= 1 C4= 1 Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022

18. The CCU block entirely depends on the Cin such that the computation for higher order Carry terms are complex. Conven tional CLA Existing CLA COMPARISON BETWEEN CLA conventional 4 bit CLA Existing 4 bit CLA The CCU block computes the Carry by assuming Cin as 1 and 0 with approximations in the Carry equations such that the complexity is reduced. Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022 18

19. 19 When Cin = 0 C0 = 0 C1 = G0 C2 = G1 + G0P1 C3 = G2 + G1P2 + G0P1P2 C4 = G3 + G2P3 + G1P2P3 + G0P1P2P3 When Cin = 1 C0 = 1 C1 = P0 C2 = G1 + P0P1 C3 = G2 + G1P2 + P0P1P2 C4 = G3 + G2P3 + G1P2P3 + P0P1P2P3 Prop. 4 bit CLA B[3:0] A[3:0] Cout Cin FOR 4 BIT CLA: Symbolic Representation: Modifications in CCU Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022

20. PPU CCU CCU MUX 2X1 SUMMATION C[ 3:0] C0[4:0] C1[4:0] Cin C[4] P[ 3:0] P [3:0] G [3:0] Cin =1 Cin =0 A[3:0] B[3:0] Sum[3:0] C[4] = Carry Pi = Ai ^ Bi Gi = Ai & Bi C(i+1) = Gi ^ ( Pi & Ci ) C0 = 0 and C0 = 1 Sum[ i ] = Pi ^ Ci Existing 4 bit CLA Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022 20

21. 21 C0 = 1 C1 = P0 => 0 C0 = 0 C1 = G0 => 1 G0= A0 . B0 = 1 .1 = 1 P0= A0 ⊕ B0 = 1 ⊕ 1 = 0 P0= A0 ⊕ B0 = 0 ⊕ 1 = 1 G0= A0 . B0 = 0 .1 = 0 Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022 A0= 1 B0=1 Cin =1 A0= 1 B0=1 Cin =0 A0 A= 1 B0 B= 1 1 C0 = 1 C1 = 0 A0 A= 1 B0 B= 1 1 C0 =>0 C1 = 1 A0 A= 1 B0 B= 1 1 C0 = 1 C1 = 1 A0 A= 1 B0 B= 1 1 C0 = 0 C1 =1 C0 = Cin => C1 = G0 + P0C0 = 1 + 1.0 => C0 = Cin => 1 C1 = G0 + P0C0 = 1 + 0.1 => 1 P0= A0 ⊕ B0 = 1 ⊕ 1 = 0 P0= A0 ⊕ B0 = 1 . 1 = 1 G0= A0 . B0 = 1 .1 = 1 G0= A0 . B0 = 1 .1 = 1 EXISTING CLA CONVENTIONAL CLA

22. RTL Schematic of Existing 4 bit CLA: Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022 22

23. Tool to be used 23 TOOLS JUSTIFICATION Xilinx To simulate and synthesize the verilog code for the proposed adder. Matlab For reading and partitioning the image into blocks and for obtaining the principle of image addition. System Generator For interconnecting the matlab modules with the designed adder for pixel addition. Cadence Design Tool To analyze the power consumption of the adder by extracting the parasitic components of the circuit. Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022

24. 24 RESULTS for Conventional 4 BIT CLA Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022

25. When Cin = 0 RESULTS for Existing 4 BIT CLA Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022 25

26. Work Plan 26 Week Tasks JUNE JULY AUGUST Literature Survey Design of a customized fault-tolerant voters Image pre- processing & interfacing Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022

27. References 27 1. A. Maheshwari, W. Burleson, R. Tessier, Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits, IEEE Trans. On Very Large Scale Integ. (VLSI) Syst. 12 (3) (2004) 299–311 Mar. 2. M. Valinataj , Saeed Safari, Fault tolerant arithmetic operations with multiple error detection and correction, 22th IEEE Int. Symp . on Defect and Fault Tolerance in VLSI Systems (DFT'07), Sep. 2007, pp. 188–196. 3. D.P. Vasudevan, P.K. Lala, J.P. Parkerson , Self-checking carry-select adder design based on two-rail encoding, IEEE Trans. Circuits Syst. Regul . Pap. 54 (12) (2007) 2696–2705 Dec. 4 .V. Ocherenty , Self-checking arithmetic logic unit with duplicated outputs, 16 th IEEE Int. On-Line Testing Symp . (IOLTS'10), 2010, pp. 202–203. 5. V. Khorasani , B.V. Vahdat, M. Mortazavi, Analyzing area penalty of 32-bit fault tolerant ALU using BCH code, 14th Euromicro Conf. On Digital System Design (DSD'11), 2011, pp. 409–413. 6. M.A. Akbar, J. Lee, Self-repairing adder using fault localization, Microelectron. Reliab . 54 (6–7) (Jun.-Jul. 2014) 1443–1451. 7. A. Mukherjee, A.S. Dhar, Real-time fault-tolerance with hot-standby topology for conditional sum adder, Microelectron. Reliab . 55 (3–4) (Feb.-Mar. 2015) 704–712. Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022

28. References 8. R. Parhi , C.H. Kim, K.K. Parhi , Fault-tolerant ripple-carry binary adder using partial triple modular redundancy (PTMR), IEEE Int. Symp . On Circuits and Systems (ISCAS'15), 2015, pp. 41–44. 9. H. Moradian , J.-A. Lee, A. Hashmi, Self-repairing radix-2 signed-digit adder with multiple error detection, correction, and fault localization, Microelectron. Reliab.63 (8) (2016) 256–266. 10. H. Moradian , J.-A. Lee, J. Yu, Efficient low-cost fault-localization and self-repairing radix-2 signed -digit adders applying the self-dual concept, J. Signal Process. Syst. 88 (3) (2017) 297–309 Sep. Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters 19 July 2022 28

29. Thank you 19 July 2022 29 Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters