Accessing I/O Devices

1. Accessing I/O devices V. Saranya AP/CSE Sri vidya College of Engg & Tech

2. I/O devices accessed through I/O interface. Requirements for I/O interface: CPU communication Device communication Data buffering Control and timing Error detection.

3. CPU Communication: Processor sends commands to the I/O system which are generally the control signals on the control bus. Exchange of data between the processor and the I/O interface over the data bus. Check whether the devices are ready or not.

4. Data Buffering: Data transfer rate is too high . Data from processor and memory are sent to an I/O interface, buffered and then sent to the peripheral device at its data rate. Error Detection: I/O interface is responsible for error detection Used to report errors to the processor. Types of errors: Mechanical, electrical malfunctions, bad disk track, unintentional changes.

5. Data Register Status/Control Register Address Decoder External Device Interface Logic Data Lines Address Lines Control Lines Data Status Control I/O interface Block diagram

6. Data Register: holds the data being transferred to or from the processor. Status/Control Register: contains information relevant to the operation. Data and status/control registers: are connected to the data bus. Address decoder : enables the device to recognize its address.

7. Address Decoder Control Circuits Data & Status Registers Input Device BUS I/O interface I/O interface for Input Device Address Lines Data Lines Control lines

8. I/O interface for Output Device Address Decoder Control Circuits Data & Status Registers Output Device BUS I/O interface Address Lines Data Lines Control lines

9. I/O interface Techniques

10. 10 I/O Ports 4 registers - status, control, data-in, data-out Status - states whether the current command is completed, byte is available, device has an error, etc Control - host determines to start a command or change the mode of a device Data-in - host reads to get input Data-out - host writes to send output Size of registers - 1 to 4 bytes

11. I/O devices can be interfaced to a computer system I/O in 2 ways: Memory Mapped I/O I/O mapped I/O

12. 12 Memory-Mapped I/O (1) (a) Separate I/O and memory space (b) Memory-mapped I/O (c) Hybrid Memory Address Space I/O Address Space

13. Memory Mapped I/O No need of special I/O instructions. Memory related instructions are used for I/O related operations.

14. I/O Mapped I/O Memory Address Space I/O address Space Total Address Space

15. I/O Mapped I/O If we want to reduce the memory address space, we allot a different I/O address space, apart from total memory space. Memory related instructions do not work here Processor use these mode only for I/O Read, I/O Write.

16. Difference between Memory Mapped I/O & I/O mapped I/O Memory Mapped I/O I/O Mapped I/O Memory & I/O share the entire address range of processor Processor provides separate address range for memory & I/O Processor provides more address lines for accessing memory Less address lines for accessing I/O More Decoding is required Less decoding is required Memory control signals used to control Read & Write I/O operations I/O control signals are used to control Read & Write I/O operations

17. Programmed I/O

18. I/O operation means A data transfer between an I/O device & memory or Between I/O device & Processor. If any I/O operations are completely controlled by processor, then the system is said to be using “ Programmed I/O” Processor has to check I/O system periodically until the operation completes  “POLLING” Microprocessor has to check if any device need service.

19. Programmed I/O Address Decoder & & & Int A? Int C? Int Z? Service routine Z Service routine C Service routine A j j j

20. Priority: The Routines assigns priority to the different I/O devices Port A is always checked 1 st . Then Port B Then Port C Order may change by changing routine.

21. When Programmed I/O techniques is used: Processor fetches I/O related instructions from memory and Issues I/O commands to I/O system to execute the instruction. Memory Mapped I/O & I/O mapped I/O technique may apply. Processor has 2 separate instructions IN & OUT for data transfer. When the I/O instruction is encountered by the processor the I/O port is expected to be ready to response. Processor is usually programmed to test the I/O device status before initiating a data transfer.