address decoder.pptx

Cpu

1. 8086 µ p - memory Interface (2) Chapter(7)

2. MEMORY FUNCTIONAL BLOCK DIAGRAM MEMORY ADDRESS DATA WR OE CE MWR MRD CS

3. MEMORY WORD SIZE (DATA BUS) EXPANSION

4. A17 A18 A19 A14 A15 A16 A0 BHE 8KX8 CS A1-A13 D0-D7 8KX8 CS A1-A13 D8-D15 A19 A18 A17 A16 A15 A14 A13 . . . . . . . . A1 A0 BHE BANK 1 1 1 1 1 1 – 8K 0/1 BOTH/LOW 1 1 1 1 1 1 0 – 8K 0/1 BOTH/HIGH FC000-FFFFE FC000-FFFFF LOW BANK HIGH BANK 1 1 1 1 1 1

5. MEMORY FUNCTIONAL BLOCK DIAGRAM WITH RD & WR SIGNALS MEMORY ADDRESS DATA WR OE CE MWR MRD CS M/ IO WR RD 1

6. A17 A18 A19 A14 A15 A16 A0 BHE 8KX8 CS A1-A13 D0-D7 8KX8 CS A1-A13 D8-D15 A19 A18 A17 A16 A15 A14 A13 . . . . . . . . A1 A0/BHE BANK 1 1 1 1 1 1 – 8K 0/1 LOW 1 1 1 1 1 1 0 – 8K 1/0 HIGH FC000-FFFFE FC000-FFFFF LOW BANK HIGH BANK M/ IO WR RD RD RD WR WR

7. A19 A18 A17 A16 A15 A14 A13 . . . . . . . . A1 A0/BHE BANK 1 1 1 1 1 1 – 8K 0/1 LOW 1 1 1 1 1 1 0 – 8K 1/0 HIGH A0 BHE 8KX8 CS A1-A13 D0-D7 8KX8 CS A1-A13 D8-D15 FC000-FFFFE FC000-FFFFF LOW BANK HIGH BANK M/ IO WR RD RD RD WR WR A17 A18 A19 A14 A15 A16 A19 A18 A17 A16 A15 A14 A13 . . . . . . . . A1 A0/BHE BANK – 8K 0/1 LOW 0 – 8K 1/0 HIGH 00000-03FFE 00000-03FFF

8. MEMORY ADDRESS (WORD CAPACITY) EXPANSION

9. 8KX8 CS 8KX8 CS A0 A19 A18 A17 A16 A15 A14 A13 . . . . . . . . A1 A0/BHE BANK 1 – 8K 0/1 LOW 1 0 – 8K 1/0 HIGH BHE 8KX8 CS A1-A13 D0-D7 8KX8 CS A1-A13 D8-D15 LOW BANK HIGH BANK M/ IO WR RD RD RD WR WR A17 A18 A19 A14 A15 A16

10. 8KX8 CS 8KX8 CS 8KX8 CS 8KX8 CS A0 A19 A18 A17 A16 A15 A14 A13 . . . . . . . . A1 A0/BHE BANK 1 – 8K 0/1 LOW 1 0 – 8K 1/0 HIGH BHE 8KX8 CS A1-A13 D0-D7 8KX8 CS A1-A13 D8-D15 LOW BANK HIGH BANK M/ IO WR RD RD RD WR WR A17 A18 A19 A14 A15 A16

11. 8KX8 CS 8KX8 CS 8KX8 CS 8KX8 CS 8KX8 CS A1-A13 D0-D7 8KX8 CS A1-A13 D8-D15 LOW BANK HIGH BANK M/ IO WR RD RD RD WR WR ADDRESS DECODER A14-A19 A0 BHE

12. 1 1 1 1 74LS138 THE 3 to 8 LINE DECODER

13. A1-A13 D0-D7 74LS138 A14 A15 A16 M/ IO A0 G2A G2B G1 A B C 2764 8KX8 2764 8KX8 2764 8KX8 2764 8KX8 2764 8KX8 2764 8KX8 2764 8KX8 8KX8 CS CS CS CS CS CS CS CS A17 A18 A19 RD WR 00000-03FFE 04000-07FFE 08000-0BFFE 0C000-0FFFE 10000-13FFE 14000-17FFE 18000-1BFFE 1C000-1FFFE LOW BANK

14. BHE A1-A13 D8-D15 74LS138 A14 A15 A16 M/ IO G2A G2B G1 A B C 2764 8KX8 2764 8KX8 2764 8KX8 2764 8KX8 2764 8KX8 2764 8KX8 2764 8KX8 8KX8 CS CS CS CS CS CS CS CS A17 A18 A19 RD WR 00000-03FFF 04000-07FFF 08000-0BFFF 0C000-0FFFF 10000-13FFF 14000-17FFF 18000-1BFFF 1C000-1FFFF HIGH BANK

15. 2764 8KX8 2764 8KX8 A1-A13 D0-D7 74LS138 A14 A15 A16 M/ IO A0 G2A G2B G1 A B C 2764 8KX8 2764 8KX8 2764 8KX8 2764 8KX8 2764 8KX8 8KX8 CS CS CS CS CS CS CS CS A17 A18 A19 RD WR LOW BANK A1-A13 D8-D15 74LS138 A14 A15 A16 M/ IO G2A G2B G1 A B C 2764 8KX8 2764 8KX8 2764 8KX8 2764 8KX8 2764 8KX8 2764 8KX8 2764 8KX8 8KX8 CS CS CS CS CS CS CS CS A17 A18 A19 RD WR HIGH BANK BHE

16. HOME WORK Draw The address decoder (using discrete components) for 8KX16 memory starting at 30000h with MRD & MWR cct . Repeat (1) above but using 74138 line decoder. What will be changed (for both 1 &2 of the above) if the start address becomes C0000h? What will be changed (for both 1 &2 of the above) if 16KX16 memory is needed instead of 8KX16 memory ?

17. The END