Advanced Microcontroller bus Architecture

AMBA protocols explanation with interview questions

1. AMBA What is AMBA? The Advanced Microcontroller Bus Architecture, is an open-standard, on-chip interconnect specification for the connection and management of functional blocks in system-on-a-chip ( SoC ) designs. Essentially, AMBA protocols define how functional blocks communicate with each other. Why AMBA? Efficient IP reuse Flexibility Bandwidth

2. APB Protocol

3. APB Operating States

4. APB Write transfer with no wait states APB Read transfer with wait states

5. AHB PROTOCOL BUS INTERCONNECT

6. AHB MASTER AND SLAVE SIGNALS

7. Arbiter and decoder

8. Basic transfers

9. Eight-beat incrementing burst, INCR8

10. AXI Protocol Read and Write Transaction

11. Write address channel signals Signal Source Description AWID[3:0] Master Write address ID. This signal is the identification tag for the write address group of signals. AWADDR[31:0] Master Write address. The write address gives the address of the first transfer in a write burst transaction AWLEN[3:0] Master Burst length. The burst length gives the exact number of transfers in a burst. AWSIZE[2:0] Master Burst size. This signal indicates the size of each transfer in the burst. AWBURST[1:0] Master Burst type. The burst type and the size information, determine how the address for each transfer within the burst is calculated. AWLOCK[1:0] Master Lock type. Provides additional information about the atomic characteristics of the transfer. AWCACHE[3:0] Master Memory type. This signal indicates how transactions are required to progress through a system. AWPROT[2:0] Master Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access. AWQOS Master Quality of Service, QoS. The QoS identifier sent for each write transaction. Implemented only in AXI4. AWREGION Master Region identifier. Permits a single physical interface on a slave to be used for multiple logical interfaces. AWUSER Master User signal. Optional User-defined signal in the write address channel. Supported only in AXI4. AWVALID Master Write address valid. This signal indicates that the channel is signaling valid write address and control information. AWREADY Slave Write address ready. This signal indicates that the slave is ready to accept an address and associated control signals.

12. Write data channel signals Signal Source Description WID[3:0] Master Write ID tag. This signal is the ID tag of the write data transfer. Supported only in AXI3. WDATA[31:0] Master Write data. The write data bus can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide. WSTRB[3:0] Master Write strobes. This signal indicates which byte lanes hold valid data. There is one write strobe bit for each eight bits of the write data bus. WLAST Master Write last. This signal indicates the last transfer in a write burst. WUSER Master User signal. Optional User-defined signal in the write data channel. WVALID Master Write valid. This signal indicates that valid write data and strobes are available. WREADY Slave Write ready. This signal indicates that the slave can accept the write data.

13. Write response channel signals Signal Source Description BID[3:0] Slave Response ID tag. This signal is the ID tag of the write response BRESP[1:0] Slave Write response. This signal indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR. BUSER Slave User signal. Optional User-defined signal in the write response channel. Supported only in AXI4 BVALID Slave Write response valid. This signal indicates that the channel is signaling a valid write response. BREADY Master Response ready. This signal indicates that the master can accept a write response.

14. Read address channel signals Signal Source Description ARID[3:0] Master Read address ID. This signal is the identification tag for the read address group of signals. ARADDR[31:0] Master Read address. The Read address gives the address of the first transfer in a read burst transaction ARLEN[3:0] Master Burst length. The burst length gives the exact number of transfers in a burst. ARSIZE[2:0] Master Burst size. This signal indicates the size of each transfer in the burst. ARBURST[1:0] Master Burst type. The burst type and the size information, determine how the address for each transfer within the burst is calculated. ARLOCK[1:0] Master Lock type. Provides additional information about the atomic characteristics of the transfer. ARCACHE[3:0] Master Memory type. This signal indicates how transactions are required to progress through a system. ARPROT[2:0] Master Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access. ARQOS Master Quality of Service, QoS. The QoS identifier sent for each Read transaction. Implemented only in AXI4. ARREGION Master Region identifier. Permits a single physical interface on a slave to be used for multiple logical interfaces. ARUSER Master User signal. Optional User-defined signal in the Read address channel. Supported only in AXI4. ARVALID Master Read address valid. This signal indicates that the channel is signaling valid read address and control information. ARREADY Slave Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals.

15. Read data channel signals Signal Source Description RID[3:0] Slave Read ID tag. This signal is the ID tag of the read data transfer. Supported only in AXI3. RDATA[31:0] Slave Read data RRESP[1:0] Slave Read response. This signal indicates the status of the read transfer. RLAST Slave Read last. This signal indicates the last transfer in a read burst. RUSER Slave User signal. Optional User-defined signal in the read data channel. RVALID Slave Read valid. This signal indicates that the channel is signaling the required read data. RREADY Master Read ready. This signal indicates that the master can accept the read data and response information .

16. Handshake Dependencies

17. APB AHB Low bandwidth High bandwidth non-pipelined Pipelined No burst Transfer Burst transfers Frequency range is <66MHZ Frequency range is <150MHZ No Split Transactions Split transactions Supports Single Master and Multiple Slaves Supports Multiple Masters and Multiple Slaves Half-duplex Full-duplex operation Low power dissipation High power dissipation APB Vs AHB

18. AHB Vs AXI AHB AXI AHB is a single channel Bus AXI is a Multi-channel Bus AHB support for Single outstanding transaction per bus master AXI supports for multiple outstanding transactions AXI support for out of order transaction completion AHB does not support any out of order transaction Minimum address space assigned for a single slave in AXI is 4 kb The address space assigned for a slave in AHB is 1 kb Does not supports unaligned address Supports aligned and unaligned data transfer Has 1 address channel, 1 read data channel, 1 write data channel Has 1 read address channel, 1 write address channel, 1 read data channel, 1 write data channel. 1 write response channel That is altogether it has 5 parallel channels. (The first AXI version had just 1 address channel) Low power dissipation Higher power dissipation Write Strobes are not supported. Write Strobes are supported

19. Interview Questions What is the use of APB? What are the control signals used for read and write in APB What is the use of bridge in AMBA? How many masters and slaves in APB? How AHB is pipelined architecture? What is the size of the max data that can be transferred in a single transfer? Explain the 1k boundary concept in AHB? Okay, response is a single cycle? but error/split/retry is two cycles, why? Explain the concept of a two-cycle response? What if the slave gets the address out of range? How to connect multiple slaves to a single master? Explain the round robin arbitration concept? Explain the split-retry concept? What is the difference between HREADY and HREADY_OUT signals? What is the slave response for a BUSY transfer? What is the difference between WRAP4 and INCR4? What is the difference between BURST and Beat? How to calculate the size of the burst? Is HREADY is Input or output to/from the slave? What is the aligned and un-align concept? Explain the LOCKED transfer? What is the default Master? Explain the concept of the AXI 4KB boundary condition? How AXI is different from AHB? Explain the valid ready handshake in AXI? Explain the channel concept? Explain the out-of-order concept? What is the fixed burst type? Explain the AXI response types? At what Minimum frequency range AXI will work?