Analog cmos vlsi design Unit 3 2023-24.ppt

Analog CMOS vlsi design unit e

1. Unit -3
Passive and Active Current Mirrors
Current Mirrors
Ch. 2 # 2

2. Basic current mirror
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Differential Amplifiers
Ch. 4 # 2
A current mirror is a circuit designed to build many current
sources in the system from the reference current source
Current mirror means  we have reference current source,
this reference current source copies the current to the other
current sources.

3. Current Mirrors
Ch. 5 # 3
Basic current mirrors

4. I
OUT
u
nC
ox
2
W
L
(
R
2
R
2R
1
V
DDV
TH)
2
•This fig consider the simple resistor
biasing assuming m1 is in saturation.

5. Current Mirrors
Ch. 5 # 5
•This expression reveals varies dependencies of Iout upon the supply,
process & temperature.
•The overdrive v/g is a function of Vdd & Vth.
•The threshold v/g varies by 100mV.
•  exhibits temperature dependencies
•Therefore Iout is poorly defined.
•Note: the process & temperature dependencies  exist if gate v/g is
not a function of supply v/g
•Ie., if gate- source v/g of the mosfet  is precisely defined
•Then drain current is not equal.
•So to design, current source in analog circuits is based on “coping”
current from reference.

6. Current Mirrors
Ch. 5 # 6
•In complex circuit  sometimes requiring external adjustments
•It is used to generate a stable reference current Iref
•Which is copied to many current sources in the system

7. Current Mirrors
Ch. 5 # 7
•For a mosfet,
•Denotes function of Id v/s Vgs
•Then
•Now if a transistor is biased at Iref

8. Current Mirrors
Ch. 5 # 8
if this voltage is applied to the gate and source terminals of a second
MOSFET, the resulting current is

9. Current Mirrors
Ch. 5 # 9
•In fig b, the structure consisting of M1 & M2 is called “current
mirror”
•The device need not to be identical.
•Neglecting channel length modulation,

10. Cascode Current Mirror
Current Mirrors
Ch. 5 # 10
•Till now, we have neglected channel length modulation
•The effects of the results in significant errors in coping currents

11. Cascode Current Mirror
Current Mirrors
Ch. 5 # 11

12. Current Mirrors
Ch. 5 # 12
•Fig 5.9 a,: if Vb is chosen such that Vy=Vx
•Then Iout closely tracks Iref
•The cascode devide “shields” the bottom transistors from variations in
Vp
•W.K.T
•Therefore Vy remains close to Vx
•Hence
•Accuracy  high
•To generate Vb, ensure Vy=Vx
•This result suggests that,
•If gate- source v/g is added to Vx,
•Then Vb is obtained.

13. Current Mirrors
Ch. 5 # 13
•In fig 5.9b, place another diode M0 in series with M1
•Therefore generating a v/g
•Proper choice of dimensions of M0 w.r.t M3  yields
•In fig 5.9 c, connect the node N to M3
•Then
•If
•Then
•

14. Cascode Current Mirror (cont.)
Current Mirrors
Ch. 5 # 14

15. Current Mirrors
Ch. 5 # 15
•In fig 5.11(a): Vb is chosen to allow the lowest possible value of
Vp
•But o/p current doesn’t accurately track Iref
•Because M1 & M2 sustain unequal drain-source v/g
•In fig 5.11(b): accuracy  high
•But minimum level at P is high by 1 threshold v/g

16. Modification cascode mirror for low voltage operation
In the circuit it is a cascode topology where the output of M2 is
connected to input of M1
Now we have to choose Vb (bias voltage of M2) such that M1 and
M2 are in saturation

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Companies, Inc. Permission
required for reproduction or
display. Slides prepared by
Travis N. Blalock, University
of Virginia.
Differential Amplifiers
Ch. 4 # 17

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Companies, Inc. Permission
required for reproduction or
display. Slides prepared by
Travis N. Blalock, University
of Virginia.
Differential Amplifiers
Ch. 4 # 18

19. Copyright © The McGraw-Hill
Companies, Inc. Permission
required for reproduction or
display. Slides prepared by
Travis N. Blalock, University
of Virginia.
Differential Amplifiers
Ch. 4 # 19

20. Headroom means the difference between the output voltage swing
and supply voltage
Or
The limit at which the signal will start to saturate depends on the
supply voltage

21. Cascode Current Mirror Biasing
Current Mirrors
Ch. 5 # 21

22. Current Mirrors
Ch. 5 # 22
•In fig 5.14b, here diode-connected transistor M7  has large W/L
•So that
•Hence
•We requiring no resistor, this circuit suffers from similar error due to
body effect

23. Active Current Mirrors
Current Mirrors
Ch. 5 # 23
•It is the basic pmos circuit which acts
as current mirror
•M1 & M2 are identical
•Whatever the current flowing across
Iin will reflect across Iout
•Current through Iout is given some
active component signal
•Current mirrors can also process
signals Operate as “active elements”
•So it is called as “active current
mirrors”

24. Active Current Mirrors (Cont…..
Current Mirrors
Ch. 5 # 24

25. Fig 5.17(a)differential pair with the current load (explaination)
Here M3 and M4 are in mirror
arrangement
 I1 is the current source.
 therefore current flowing through M3 is
same as current flowing through M4.
From the small signal point of view,
If I1 is increased by ΔI,
then current flowing from M4 also
increases.
M1 and M2 are differential pair transistors,
then the upper portion of the circuit acts
as the load for the below differential pair
circuit.
Therefore current source I1 acts as load
and Iss is the tail current of the
circuit.

26. Figure 5.23 (b) circuit for calculation of Gm
Now we have to derive small signal voltage gain (Av)
• Assuming γ=0 for simplicity
• we have |Av|= Gm.Rout
Figure 5.23 (b) circuit for
calculation of Gm

27. Figure 5.23 (c) circuit for calculation of Rout.
M2 is degenerated by the source output
impedance of M1,
Rdeg = (1/gm1)||rO1,
thereby exhibiting an output impedance
equal to (1 + gm2rO2)Rdeg + rO2a
≈ 2rO2.
It follows that
Rout = (2rO2)rO4, and
|Av| = [gm1/2][(2rO2)rO4]

28. Another explaination
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required for reproduction or
display. Slides prepared by
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of Virginia.
Differential Amplifiers
Ch. 4 # 28

29. Current Mirrors
Ch. 5 # 29
•In fig5.17 a, consider differential pair  M1 & M2
•M3 & M4 current source load.
•In fig 5.17,b:
•In fig 5.17,c: now we have to compute Rout
•M2 is degenerated by the source output impedance
•That is the circuit is similar to common source amplifier with
regenerative circuit
• output impedance equal to

30. Current Mirrors
Ch. 5 # 30
•In the second approach We calculate
•Then multiply the result to obtain Vout/Vp
(from common gate
circuit)

31. Active Current Mirrors (Cont…..
Current Mirrors
Ch. 5 # 32

32. Large Signal Analysis
Current Mirrors
Ch. 5 # 34
•o/p v/g depends on diff b/w Id4 & Id2.
•In fig replace ideal tail current source
 by mosfet
•If Vin1 is much –ve than Vin2
•M1, M3, M4 off
•Since no current flows from Vdd
•M2 & M5  deep triode region
•  carrying 0 current
•Thus Vout=0
•As Vin1 approaches Vin2
•M1on (drawing part of Id5 and from
M3)
•Therefore M4 on

33. Current Mirrors
Ch. 5 # 35
•As Vin1 becomes more +ve than Vin2
•Id1, Id3, Id4 increases
•If Id2  decreases
•Then M4  triode region (0)
•If Vin1 – Vin2 is sufficiently large
•M2  off
•M4 deep triode region with 0 current
•Vout= Vdd
•Then M1 enters triode region

34. Small-Signal Analysis
Current Mirrors
Ch. 5 # 37
•It has small inputs
•v/g swings at node x & y are different
•Because the diode-connected device
M3 yields much lower v/g gain from
the i/p to node x
•As a result, the effects of Vx &Vy at node P do not cancel each other
•This node cannot be considered as virtual ground
•We compute the gain using 2 approaches

35. Small-Signal Analysis 1
st
approach
Calculation of G
m
2/ 2/
2,122,1431 inmDinmDDD
VgIVgIII 
I
out
I
D2
I
D4
g
m1,2
V
in
,G
m
g
m1,2
•Consider the circuit is not quite symmetric
•Node P can be approximately by a virtual ground
•From fig b

36. Current Mirrors
Ch. 5 # 39
•The active mirror operation yields a different value
•Because when a v/g is applied to the o/p to measure Rout
•The gate v/g of M4 does not remain constant
•Rather than draw the entire equivalent circuit

37. Current Mirrors
Ch. 5 # 40
I
X2
V
X
2r
o1,2
1/g
m3

V
X
ro4
R
outr
o2||r
o4 , (2r
o1,2[1/g
m3]||r
o3)
A
vg
m1,2(r
o2||r
o4)
•For small signals Iss is open,
•That is any current flowing into M1 must flow out of M2
•It can be represented

38. Small-Signal Analysis 2
nd
approach
Current Mirrors
Ch. 5 # 41

39. Small-Signal Analysis (Cont….
Current Mirrors
Ch. 5 # 42

40. Small-Signal Analysis (Cont…
Current Mirrors
Ch. 5 # 43

41. Common Mode Characteristics
Current Mirrors
Ch. 5 # 44
A
CM
V
out
V
in,CM
•Change in the i/p cm level leads to
change in bias current of all
transistors

42. Common Mode (cont.)
•Here F & X are shorted that is Vin,cm increases
•Vf and Vout  drops
A
CM

1
2g
m3,4
||
r
o3,4
2
1
2g
m1,2
R
SS

1
12g
m1,2
R
SS
g
m1,2
g
m3,4

43. Common Mode (cont.)
Current Mirrors
Ch. 5 # 46
CMRR
A
DM
A
CM
g
m1,2
(r
o1,2
||r
o3,4
)
g
m3,4(12g
m1,2R
SS)
g
m1,2
g
m3,4(r
o1,2||r
o3,4)(12g
m1,2R
SS)

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Companies, Inc. Permission
required for reproduction or
display. Slides prepared by
Travis N. Blalock, University
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Differential Amplifiers
Ch. 4 # 50

45. Unit3
Frequency Response of Amplifiers

46. •Till now we are focused on low frequency characteristics of amplifier
neglecting the effect of device & load capacitance
•In most analog circuits, we consider the parameter such as noise, PD,
gain
•But it is important to understand the frequency response limitations
•In this chapter we study about single stage & differential amplifiers in
the frequency domain

47. General Considerations
Miller Effect

49. •If the impedance Z forms the only signal B/W X & Y.
•Then the conversion is often invalid in the fig
•For the simple resistive divider, the theorem gives correct i/p but
incorrect gain

50. Current Mirrors
Ch. 5 # 56
•Miller’s theorem proves useful where Z is similar with main signal
•If we apply to obtain , i/p- o/p transfer function, miller’s theorem
cannot be used simultaneously to calculate o/p impedance.
•Therefore to derive transfer function, we apply v/g source to the i/p
circuit for obtaining
•To determine o/p impedance, we apply v/g source to o/p for obtaining

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required for reproduction or
display. Slides prepared by
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Differential Amplifiers
Ch. 4 # 57

52. •Consider simple cascade amplifier
•A1 & A2 are ideal v/g amplifier
•R1 & R2 are o/p resistance of each stage
•Cin & Cn are i/p capacitance of each stage.
•Cp load capacitance
•Overall transfer function is

53. Current Mirrors
Ch. 5 # 59
•The circuit exhibits 3 poles. [each is determined by the total
capacitance from each node to ground, multiplied by total resistance
at the node to ground]
•We can associate each pole with each other
•
•“each node in the circuit contributes one pole to the transfer function”

54. •The location of the poles is difficult to calculate.
•Because R3 & C3 create intersection b/w x & y
•In many circuits to estimating the transfer function.
•We multiply total capacitance by the total incremental resistance.
•Thus obtaining an equivalent time constant & hence a pole
frequency.

55. Common Source Stage
This topology provides high i/p impedance, high v/g gain,
minimal v/g headroom.
In this fig, common source stage driven by a finite resistance Rs
Capacitance Cgs & Cdb are grounded.
Cgd appears b/w i/p & o/p

56. Miller’s Approximation
Assuming that λ = 0 and M1 operates in saturation,
let us first estimate the transfer function by associating one pole
with each node.
The total capacitance seen from X to ground is equal to CGS plus
the Miller multiplication of CGD, namely,
CGS + (1 − Av)CGD, where Av = −gm RD
[Fig. 6.13(b)]. The magnitude of the “input” pole is therefore given
by

57. Another approximation of o/p pole can be obtained if Rs is high.
In the fig Rs is neglected.
therefore

58. Common Source Stage using Equivalent Circuit
We can sum current at each node

59. Current Mirrors
Ch. 5 # 65

61. Common Source Stage using
Equivalent Circuit

62. CS Stage using Feed forward path
•Cgd provides feed forward path, that conducts the i/p signal to the
o/p at very high frequencies
•Therefore a slope in frequency response that is less –ve than

63. Calculation of Zero in a CS Stage
Current through Cgd & M1 = & opposite

64. Calculation of Input Impedance

65. Calculation of Input Impedance

66. Source Followers
•These are occasionally employed as level shifters or buffers.
•In fig, here Cl represents total capacitance at o/p node to
ground
•Strong interaction b/w b/w X & Y through Cgs make it
difficult to associate a pole with each other node.

67. Current Mirrors
Ch. 5 # 73
•In fig neglecting body
effect, using equivalent
circuit
•we sum the current at the
o/p node

69. Source Followers (Input Impedance)
Here M1 (small signal gate source) =

71. Source Followers (Output Impedance)

72. Source Followers (Output Impedance)

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Companies, Inc. Permission
required for reproduction or
display. Slides prepared by
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Differential Amplifiers
Ch. 4 # 81
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