Application Specific Integrated Circuit Module 3 Notes

Design data path elements for ASIC cell libraries and compute optimum path delay.

1. Application –Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech,Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 1
Unit III
Low-Level Design Entry: Schematic entry: Hierarchical design, The cell library,
Names, Schematic Icons & Symbols, Nets, Schematic
Entry for ASICs, Connections, vectored instances &
buses, Edit in place, attributes, Netlist screener.
ASIC Construction: Physical Design, CAD Tools, System partitioning, Estimating
ASIC size. Partitioning: Goals and objectives, Constructive
Partitioning, Iterative Partitioning Improvement, KL, FM and
Look Ahead algorithms.
(05+05)Hrs

2. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 2
Introduction: Low-Level Design Entry: Schematic Entry
•The purpose of design entry is to describe a microelectronicsystem to a set ofElectronic Design
Automation (EDA) tools. Electronic systems were, and many still are, constructed from off-the-shelf
components, such as TTL ICs.
•Design entry for these systems now usually consists of drawing a picture, a schematic. The schematic
illustrates the connection of all components, representing the internal connectivity of an ASIC. This type of
design-entry process is called schematic entry, or schematic capture. A circuit schematic describes an ASIC in the
same way an architect’s plan describes a building.
•The circuit schematic is a picture, an easy format for us to understand and use, but computers need to work
with an ASCII or binary version of the schematic that we call a netlist. The output of a schematic-entry tool
is thus a netlist file that contains a description of all the components in a design and their interconnections.
•Not all the design information may be conveyed in a circuit schematic or netlist, because not all of the
functions of an ASIC are described by the connectivity information. For example, suppose we use a
programmable ASIC for some random logic functions.
•Part of the ASIC might be designed using a text language. In this case, the design entry also includes writing
the code. What if an ASIC in our system contains a programmable memory (PROM)? Is the PROM microcode, the
'1's and '0's, part of design entry? The operation of our system is certainly dependent on the correct programming of
the PROM.

3. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 3
•SoperhapsthePROMcodeoughttobeconsideredpartofdesignentry.
•Ontheotherhand,nobodywouldconsidertheoperating systemcodethatisloadedintoRAM
onanASICtobeapartofthe designentry.
•Obviously,then,thereareseveraldifferentformsofdesignentry.Ineachcase,itisimportantto
makesurethatyouhavecompletelyspecifiedthesystem—notonlysothatitcanbecorrectly
constructed,butsothatsomeoneelsecanunderstandhowthesystemisputtogether.Design
entryisthusanimportantpartofdocumentation.
•Untilrecently,mostASICdesignentryusedschematicentry.AsASICshavebecomemore
complex,otherdesign-entrymethodsarebecomingcommon.Alternativedesign-entrymethodscan
usegraphicalmethods,suchasaschematic,ortextfiles,suchasaprogramminglanguage.
•UsingaHardware Description Language (HDL)fordesignentryallowsustogeneratenetlists
directlyusinglogicsynthesis.

4. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 4
Schematic Entry
•SchematicentryisthemostcommonmethodofdesignentryforASICsandislikelytobeusefulinone form
oranotherforsometime.HDLsarereplacingconventionalgate-levelschematicentry,butnew graphical
toolsbasedonschematicentryarenowbeingusedtocreatelargeamountsofHDLcode. Circuit schematicsare
drawnonschematicsheets.
•Standardschematicsheetsizes(Table9.1)areANSIA–E(morecommonintheUnitedStates)and
ISOA4–A0(morecommoninEurope).
•Usually, a frameorborderisdrawnaroundtheschematic containingboxesthatlistthenameandnumberof
theschematicpage,thedesigner,thedateofthedrawing, andalistofanymodificationsorchanges

5. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 5
•Figureshowsthe“spades”and“shovels”therecognizedsymbolsforAND,NAND,OR,and
NORgates.Oneoftheproblemswiththeserecommendationsisthatthecornerpointsoftheshapes
donotalwayslieonagridpoint(usingareasonablegridsize).
FIGURE:IEEE-recommendeddimensionsandtheirconstructionforlogic-gatesymbols.(a)NANDgate
(b) exclusive-ORgate(anORgateisasubset).

6. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 6
•Figureshowssomepictorialdefinitionsofobjectsyoucanuseinasimpleschematic.Weshall
discussthedifferenttypesofobjectsthatmightappearinanASICschematicfirstandthendiscuss
thedifferenttypesofconnections.
FIGURE:Termsusedincircuitschematics.
•Schematic-entrytoolsforASICdesignaresimilartothoseforprinted-circuitboard(PCB)design.Thebasic
objectonaPCBschematicisacomponentordevice—aTTLICorresistor,forexample.Theremaybe
severalhundredcomponentsonatypicalPCB.IfwethinkofalogicgateonanASICasbeingequivalenttoa
componentonaPCB,thenalargeASICcontainshundredsofthousandsofcomponents.Wecannormally
draweverycomponentonafewschematicsheetsforaPCB,butdrawingeverycomponentonanASIC
schematicisimpractical.

7. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 7
Hierarchical Design
•Hierarchyreducesthesizeandcomplexityofaschematic.Supposeabuildinghas10floorsand
containsseveralhundredofficesbutonlythreedifferentbasicofficeplans.
•Furthermore,supposeeachofthefloorsabovethegroundfloorthatcontainsthelobbyisidentical.
Thentheplansforthewholebuildingneedonlyshowdetailedplansforthegroundfloorandone
oftheupperfloors.
•Theplansfortheupperfloorneedonlyshowthelocationsofeachofficeandtheofficetype.We
canthenuseaseparatesetofthreedetailedplansforeachofthedifferentofficetypes.Allthese
differentplanstogetherformanestedstructurethatisahierarchicaldesign.
•Theplanforthewholebuildingisthetop-levelplan.Theplansfortheindividualofficesareat
thelowestlevel.
•Toclarifytherelationshipbetweendifferentlevelsofhierarchy,wesaythatasub-schematic(an
office)isachildoftheparentschematic(thefloorcontainingoffices).
•Anelectricalschematiccancontainsub-schematics.Thesub-schematic,inturn,maycontainother
sub-schematics.The figureillustratestheprinciplesofschematichierarchicaldesign.

8. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 8
•The alternative to hierarchical design is to draw all of the ASIC components on one giant schematic, with no
hierarchy, in a flat design.
FIGURE:Schematicexample
showinghierarchicaldesign.
(a)Theschematicofahalf-
adder,thesub-schematicof
cellHADD.
(b)Aschematicsymbolfor
thehalfadder.
(c)Aschematicthatusesthe
half-addercell.
(d)Thehierarchyofcell
HADD.

9. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 9
THE CELL LIBRARY
•ComponentsinanASICschematicarechosenfromalibraryofcells.
•LibraryelementsforalltypesofASICsaresometimesalsoknownasmodules.
•Unfortunatelythetermmodulewillhaveaveryspecificmeaningwhenwecometodiscusshardware
descriptionlanguages.
•Toavoid any chanceofconfusion,hereweusethetermcelltomeaneitheracell, amodule, amacro,or
abookfromanASIClibrary.
•Librarycellsareequivalenttotheofficesinourofficebuilding.MostASICcompaniesprovideaschematic
libraryofprimitivegatestobeusedforschematicentry.
•ThefirstproblemwithASICschematiclibrariesisthattherearenonamingconventions.Forexample,a
primitivetwo-inputNANDgateinaXilinxFPGAlibrarydoesnothavethesamenameasthetwo-input
NANDgateinanLSILogicgate-arraylibrary.
•ThismeansthatyoucannottakeaschematicthatyouusedtocreateaprototypeproductusingaXilinxFPGA
andusethatschematictocreateanLSILogicgatearrayforproduction.
•AssoonasyoustartenteringaschematicusingalibraryfromanASICvendor,youare,tosomeextent,
makingacommitmenttousethatvendor’sASIC.MostASICdesignersaremuchhappiermaintainingalarge
degreeofvendorindependence.

10. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 10
•ASecondproblemwithASICschematiclibrariesisthattherearenostandardsforcellbehavior.
•Forexample,atwo-inputMUXinanActellibraryoperatessothattheinputlabeledAisselectedwhentheMUXselect
inputS='0'.Atwo-inputMUXinaVLSITechnologylibraryoperatesinthereversefashion,sothattheinputlabeledBis
selectedwhenS='0’.
•Thesetypesofdifferencescancausehard-to-findproblemswhentryingtoconvertaschematicfromonevendortoanother
byhand.
•Theseproblemsmakechangingorretargetingschematicsfromonevendortoanotherdifficult.Thisprocessissometimes
knownasportingadesign.
•Librarycellsthatrepresentbasiclogicgates,suchasaNANDgate,areknownasprimitivecells,usuallyreferredtojust
ascells.
•InahierarchicalASICdesign,acellmaybeaNANDgate,aflip-flop,amultiplier,orevenamicroprocessor,forexample.
•Tousetheofficebuildinganalogyagain,eachofthethreebasicofficetypesisaprimitivecell.However,theplanforthe
secondfloorisalsoacell.Thesecond-floorcellisasubschematicoftheschematicforthewholebuilding.
•TherearetwotypesofmacrosforMGAsandprogrammableASICs.Themostcommontypeofmacroisahardmacro
thatincludesplacementinformation.Ahardmacrocanchangeinpositionandorientation,buttherelativelocationofthe
transistors,otherlayout,andwiringinsidethemacroisfixed.
•Asoftmacrocontainsonlyconnectioninformation(betweentransistorsforagatearrayorbetweenlogiccellsfora
programmableASIC).Thustheplacementandwiringforasoftmacrocanvary.Thismeansthatthetimingparametersfor
asoftmacrocanonlybedeterminedafteryoucompletetheplace-and-routestep.Forthisreason,thebasiclibrary
elementsforMGAsandprogrammableASICs,suchasNANDgates,flip-flops,andsoon,arehardmacros.

11. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 11
Foryourreference

12. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 12
NAMES
•Eachofthecells,primitiveornot,thatyouplaceonanASICschematichasacellname.
•Eachuseofacellisadifferentinstanceofthatcell,andwegiveeach instanceauniqueinstancename.
•Acellinstanceissomewherebetweena copyandareferencetoa cellina library.
•Ananalogywouldbethepicturesofhamburgersonthewallinafast-foodrestaurant.Thepicturesare
somewherebetweenacopyanda referenceto a realhamburger.
•Werepresenteachcellinstancebyapictureoricon,alsoknownasasymbol.
•Wecanrepresentprimitivecells,suchasNANDandNORgates,withfamiliariconsthatlooklikespades
andshovels.
•Someschematiceditorsoffertheoptionofswitchingbetweenthesefamiliariconsandusingtherectangular
IEEEstandardsymbolsforlogicgates.Unfortunatelythetermiconisalsooftenusedtorefertoanyofthe
picturesonaschematic,includingthosethatrepresentsubschematics.
•Thereisnoacceptedwaytodifferentiatebetweenaniconthatrepresentsaprimitivecellandonethat
representsasubschematicthatmaybeinturnacollectionofprimitivecells.
•Infact,thereisusuallynoeasywaytotellbylookingataschematicwhichiconsrepresentprimitivecellsand
whichrepresentsubschematics.

13. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 13
SCHEMATIC ICONS AND SYMBOLS
•Mostschematic-entryprogramsallowthedesignertodrawspecialorcustomicons.Inaddition,theschematic
entrytoolwillalsousuallycreateaniconautomaticallyforasubschematicthatisusedinahigher-level
schematic.Thisisaderivedicon,orderivedsymbol.Theexternalconnectionsofthesubschematicare
automaticallyattachedtotheicon,usuallyarectangle.
•Figure9.4(c)showswhataderivediconforacell,DLAT,mightlooklike(wecouldalsohavedrawnthisby
hand).ThesubschematicforDLATisshowninFigure9.4(b).Wesaythattheinverterwiththeinstancename
inv1inthesubschematicisasubcell(orsubmodule)ofthecellDLAT.Alternatively,wesaythatcellinstance
inv1isachildofthecellDLAT,andcellDLATisaparentofcellinstanceinv1.
FIGURE9.4Acellanditssubschematic.(a)Aschematiclibrarycontainingiconsfortheprimitivecells.(b)A
subschematicforacell,DLAT,showingtheinstancenamesfortheprimitivecells.(c)AsymbolforcellDLAT.

14. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 14
•Figure9.5(a)showsamorecomplexsubschematicfora4-bitlatch.Eachprimitivecellinstanceinthis
schematicmusthaveauniquename.Thiscangetverytiresomeforlargecircuits.Insteadofcreating
complex,butrepetitive,subschematicsforcomplexcellswecanusehierarchy.
FIGURE9.5A4-bitlatch:
(a)drawn asaflat schematic
fromgate-level primitives,
(b)drawnasfourinstances of
thecellsymbolDLAT,
(c)drawn usingavectored
instanceoftheDLAT cell
symbolwithcardinalityof4,
(d) drawnusinganewcell
symbolwiththe cell nameFour
Bit.

15. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 15
•Figure9.5(b)showsahierarchicalsubschematicforacellFourBit,whichinturnusesfourinstancesofthe
cellDLAT.
•ThefourinstancesofDLATinFigure9.5(b)havedifferentinstancenames:L1,L2,L3,andL4.
•NoticethatwecannotusejustonenameforthefourinstancesofDLATtoindicatethattheyareallthesame
cell.
•Ifwedid,wecouldnotdifferentiatebetweenL1andL2,forexample.TheverticalrowofinstancesinFigure
9.5(b)lookslikeavectorofelements.Figure9.5(c)showsavectoredinstancerepresentingfourcopiesofthe
DLATcell.Wesaythecardinalityofthisinstanceis4.
•Toolsnormallyuseboldlinesorsomeotherdistinguishingfeaturetorepresentavectoredinstance.The
cardinalityinformationisoftenshownasavector.
•ThusL[1:4]representsfourinstances:L[1],L[2],L[3],L[4].Thisisconvenientbecausenowwecanseethat
allsubcellsareidenticalcopiesofL,butwehaveauniquenameforeach.
•Finally,asshowninFigure9.5(d),wecancreateanewsymbolforthe4-bitlatch,FourBit.
•ThesymbolforFourBithasa4-bit wideinputbusforthefourDinputs,anda4-bitwideoutputbusforthe
fourQoutputs.
•ThesubschematicforFourBitcouldbeeitherFigure9.5(a),(b),or(c)(thoughtheexactnamingoftheinputs
andoutputsandtheirattachmenttothebusesmaybedifferentineachcase).

16. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 16
NETS
The schematics shown in Figure 9.4 contain both local nets and external nets. An example of a local
net in Figure 9.4 (b) is n1, the connection between the output terminal of the AND cell and1 to the OR cell
or1. When the four copies of this circuit are placed in the parent cell FourBit in Figure 9.5 (d), four copies of
net n1 are created. Since the four nets named n1 are not actually electrically connected, even though they have
the same name at the lowest hierarchical level, we must somehow find a way to uniquely identify each net.
The usual convention for naming nets in a hierarchical schematic uses the parent cell instance name as
a prefix to the local net name. A special character (':' '/' '$’ '#' for example) that is not allowed to appear in
names is used as a delimiter to separate the net name from the cell instance name. Supposing that we drew the
subschematic for cell FourBit as shown in Figure 9.5 (b), the four different nets labeled n1 might then
become:
FourBit.L1:n1FourBit.L2:n1FourBit.L3:n1FourBit.L4:n1
This naming is usually done automatically by the schematic-entry tool. The schematic DLAT also
contains three external nets: D, EN, and Q. The terminals on the symbol DLAT connect these nets to other
nets in the hierarchical level above. For example, the signal Trigger:flag in Figure 9.4 (c) is also
Trigger.DLAT:Q. Each schematic tool handles this situation differently, and life becomes especially difficult
when we need to refer to these nodes from a simulator outside the schematic tool, for example. HDLs such as
VHDL and Verilog have a very precise and well-defined standard for naming nets in hierarchical structures.

17. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 17
SCHEMATIC ENTRY FOR ASICS AND PCBS
A symbol on a schematic may represent a component, which may contain component parts. You are
more likely to come across the use of components in a PCB schematic. A component is slightly different from
an ASIC library cell. A simple example of a component would be a TTL gate, an SN74LS00N, that contains
four 2-input NAND gates. We call an SN74LS00N a component, and each of the individual NAND gates
inside is a component part. Another common example of a component would be a resistor pack single package
that contains several identical resistors.
In PCB design language, a component label or name is a reference designator. A reference designator
is a unique name attribute, such as R99, attached to each component. A reference designator, such as R99, has
two pieces: an alpha prefix R and a numerical suffix 99. To understand the difference between reference
designators and instance names, we need to look at the special requirements of PCB design.
PCBs usually contain packaged ASICs and other ICs that have pins that are soldered to a board. For
rectangular, dual-in-line (DIP) packages, the pins are numbered counterclockwise from the upper-left corner
looking down on the package.
IC symbols have a pin number for each part in the package. For example, the TTL 74174 hex D flip-
flop with clear contains six parts: six identical D flip-flops. The IC symbol representing this device has six Pin
Number attribute entries for the D input corresponding to the six possible input pins. They are pins 3, 4, 6, 11,
13, and 14.

18. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 18
There is no process in ASIC design directly equivalent to the process of part assignment
described above, and thus no need to use reference designators. The reference-designator naming
convention quickly becomes unwieldy if there are a large number of components in a design. For
example, how will we find a NAND gate named X3146 in an ASIC schematic with 100 pages?
Instead, for ASICs, we use a naming scheme based on hierarchy.
In large hierarchical ASIC designs, it is difficult to provide a unique reference designator to each
element. For this reason, ASIC designs use instance names to identify the individual components.
Meaningful names can be assigned to low-level components and also the symbols that represent
hierarchy. We derive the component names by joining all of the higher-level cell names together. A
special character is used as a delimiter and separates each level.
Examples of hierarchical instance names are:
cpu.alu.adder.and01
MotherBoard:Cache:RAM4:ReadBit4:Inverter2

19. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 19
CONNECTIONS
•Cellinstanceshaveterminalsthataretheinputsandoutputsofthecell.Terminalsarealso
knownaspins, connectorsorsignals.
•Thetermpiniswidelyused,butweshalltrytouseterminal,andreservethetermpinforthemetal
leadsonanASICpackage.Thetermpinisusedinschematicentryandroutingprogramsthatare
primarilyintendedfor PCBdesign.
FIGURE9.6Anexampleoftheuseofabustosimplifyaschematic.(a)Anaddressdecoderwithoutusingabus.(b)A
buswithbusripperssimplifiestheschematicandreducesthepossibilityofmakingamistakeincreatingandreadingthe
schematic.

20. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 20
•Electricalconnectionsbetweencellinstancesusewiresegmentsornets.
•Wecangroupcloselyrelatednets,suchasthe32bitsofa32-bitdigitalword,togetherintoabusor
intobuses(notbusses).
•Ifsignalsonabusarenotcloselyrelated,weusuallyusethetermbundleorarrayinsteadofbus.An
exampleofabundlemightbeabusforaSCSIdisksystem,containingnotonlydatabitsbut
handshakeandcontrolsignalstoo.
•Figure9.6showsanexampleofabusinaschematic.Ifweneedtoaccessindividualnetsina
busora bundle,weuseabreakout(alsoknownasaripper,anEDIFterm,orextractor).
•Forexample,abreakoutisusedtoaccessbits0–7ofa32-bitbus.Ifweneedtorearrangebitsona
bus,some schematiceditorsoffersomethingcalledaswizzle.
•Forexample,wemightuseaswizzletoreorderthebitsonan8-bitbussothattheMSBbecomesthe
LSBandsoondowntotheLSB,whichnowbecomestheMSB.Swizzlescanbeuseful.Forexample,
wecanmultiplyordivideanumberby2byswizzlingallthebitsupordownoneplaceonabus.

21. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 21
•Sofar,thenamingconventionsarefairly
standardandeasytofollow.However,
whenwestarttousevectoredinstancesand
buses(asisnowcommoninlargeASICs),
therearepotentialareasofdifficultyand
confusion.
•Figure9.7(a)showsaschematicfora16-
bitlatchthatusesmultiplecopiesofthe
cellFourBit.Thebusesare labeledwiththe
appropriatebits.Figure9.7(b)showsa
newcellsymbolforthe16-bitlatchwith
16-bitwidebusesfortheinputs,D,and
outputs,Q.
•FIGURE 9.7 A 16-bit latch:
(a) drawn as four instances of cell FourBit;
(b) drawn as a cell named SixteenBit;
(c) drawn as four multiple instances of cell FourBit.
VECTORED INSTANCES AND BUSES

22. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 22
•Figure 9.7 (c) shows an alternative representation of the 16-bit latch using a vectored instance of
FourBit with cardinality 4.
•Suppose we wish to make a connection to expressly one bit, D1 (we have used D1 as the first bit
rather than the more conventional D0, so that numbering is easier to follow).
•We also wish to make a connection to bits D9-D12, represented as D[9:12]. We do this using a
bus ripper. Now we have the rather awkward situation of bus naming shown in Figure 9.7 (c).
•Problems arise when we have “buses of buses” because the numbers for the bus widths do not
match on either side of a ripper. For this reason, it is best to use the single-bus approach shown
in Figure 9.7 (b) rather than the vectored-bus approach of Figure 9.7 (c).

23. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 23
EDIT-IN-PLACE
•FIGURE 9.7 A 16-bit latch:
(a)drawn as four instances of cell FourBit;
(b)drawn as a cell named SixteenBit;
(c)drawn as four multiple instances of cell FourBit.
•Figure 9.7 (b) shows a symbol SixteenBit,
which uses the sub schematic shown in
Figure 9.7 (a) containing four copies of
FourBit, named NB1, NB2, NB3, and NB4
(the NB stands for nibble, which is half of a
word; a nibble is 4 bits for 8-bit words).
•Suppose we use the schematic-entry
program to edit the subcell NB1. L1, which
is an instance of DLAT inside NB1.
Perhaps we wish to change the D latch to a
D latch with a reset, for example. If the
schematic editor supports edit-in-place.
• We can edit a cell instance directly. After
we edit the cell, the program updates all the
DLAT subcells in the currently loaded cell
to reflect the changes made.

24. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 24
•Using edit-in-place we can edit the cell Floor. Suppose we change some of the cell instances of cell
name NoWindowOffice to instances of cell name WindowOffice. When we finish editing and save
the cell Floor , we have effectively changed all of the floors that contain instances of this cell.
•Instead of editing a cell in place, you may really want to edit just one instance of a cell and leave
any other instances unchanged. In this case you must create a new cell with a new symbol and new,
unique cell name. It might also be wise to change the instance name of the new cell to avoid any
confusion.
•For example, we might change the third-floor plan of our office to be different from the other upper
floors. Suppose the third floor is now an instance of cell name FloorVIP instead of Floor. We could
continue to call the third-floor cell instance FloorThree , but it would be better to rename the
instance differently, FloorSpecial for example, to make it clear that it is different from all the other
floors.
•Some tools have the ability to alias nets. Aliasing creates a net name from the highest level in the
design. Local names are net names at the lowest level such as D , and Q in a flip-flop cell. These
local names are automatically replaced by the appropriate top-level names such as Clock1, or
Data2, using a dictionary. This greatly speeds tracing of signals through a design containing many
levels of hierarchy.

25. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 25
ATTRIBUTES
•You can attach a name, also known as an identifier or label, to a component, cell instance, net,
terminal, or connector. You can also attach an attribute, or property, which describes some aspect
of the component, cell instance, net, or connector. Each attribute has a name, and some attributes also
have values. The most common problems in working with schematics and netlists, especially when
you try to exchange schematic information between different tools, are problems in naming.
•Since cells and their contents have to be stored in a database, a cell name frequently corresponds (or
is mapped to) a filename. This then raises the problems of naming conventions including: case
sensitivity, name-collision resolution, dictionaries, handling of special characters (such as embedded
blanks or underscores), other special characters “common” (such as characters in foreign alphabets),
first-character restrictions, name-length problems (only 28 characters are permitted on an NFS
compatible filename), and so on.

26. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 26
NETLIST SCREENER
A surprising number of problems can be found by checking a schematic for obviously fatal errors. A
program that analyzes a schematic netlist for simple errors is sometimes called a schematic screener or netlist
screener. Errors that can be found by a netlist screener include:
•unconnected cell inputs,
•unconnected cell outputs,
•nets not driven by any cells,
•too many nets driven by one cell,
•nets driven by more than one cell.
The screener can work continuously as the designer is creating the schematic or can be run as a separate
program independently from schematic entry. Usually, the designer provides attributes that give the screener the
information necessary to perform the checks. A few of the typical attributes that schematic-entry programs use are
described next.

27. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 27
•A screener usually generates a list of errors together with the locations of the problem on the schematic
where appropriate. Some editors associate an identifier, or handle, to every piece of a schematic,
including comments and every net.
•Most schematic-entry programs work on a grid. The designer can control the size of the grid and
whether it is visible or not. When you place components or wires you can instruct the editor to force
your drawing to snap to grid.
•This simplifies the internal mechanics of the schematic-entry program. It also makes the transfer of
schematics between different EDA systems more manageable.
•More sophisticated options allow more complex searches, perhaps using wildcard matching. For
example, to find all three-input NAND gates (primitive cell name ND3) or three-input NOR gates
(primitive cell name NO3), you could search for cell name N*3, where * is a wildcard symbol standing
for any character.
•For large schematics it is useful to be able to generate a report on the used and unused reference
designators. An example would be:
Reference designator prefix: R
Unused reference designator numbers: 153, 154
Last used reference designator number: 180
•If you need this feature, you probably are not using enough hierarchy to simplify your design.

28. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 28
SCHEMANTIC-ENTRY TOOLS
•Some editors similarly offer icon edit-in-place as schematic edit-in-place for cells.
•Often, you have to toggle editing modes in the schematic-entry program to switch between editing cells and
editing cell icons.
•A schematic-entry program must keep track of when cells are edited. Normally, this is done by using a
timestamp or datestamp for each cell.
•This is a text field within the data file for each cell that holds the date and time that the cell was last
modified. When a new schematic or cell is loaded, the program needs to compare its timestamp with the
timestamps of any subcells. If any of the subcell timestamps are more recent, then the designer needs to be
alerted.
•Usually, a message appears to inform you that changes have been made to subcells since the last time the
cell currently loaded was saved. This may be what you expect, or it may be a warning that somehow a
subcell has been changed inadvertently (perhaps someone else changed it) since you last loaded that cell.
•It is exceedingly painful to move components if you have to rewire connections each time. Most schematic
editors allow you to move the components and drag any wires along with them.
•A cell library or a collection of libraries is a key part of the schematic-entry process. The ability to handle
and control these libraries is an important feature of any schematic editor. It should be easy to select
components from the library to be placed on a schematic.

29. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 29
•Most schematic-entry programs allow you to undo commands. This feature may be restricted
to simply undoing the last command that you entered, or may be an unlimited undo and redo,
allowing you to back up as many commands as you want in the current editing session.
•You can spend a lot of time in a schematic editor placing components and drawing the
connections between them. Features that simplify initial entry and allow modifications to be
made easily can make an enormous difference to the efficiency of the schematic-entry process.
•In large schematics it is necessary to continue large nets and signals across several pages of
schematics. Signals such as power and ground, VDD and GND, can be connected using global
nets or special connectors. Global nets allow the designer to label a net with the same name
at different places on a schematic page or on different pages without having to draw a
connection explicitly. The schematic editor treats these nets as though they were electrically
connected.
•Special connector symbols can be used for connections that cross schematic pages. An off-
page connector or multipage connector is a special symbol that will show and label a
connection to different schematic pages. More sophisticated editors can automatically label
these connectors with the page numbers of the destination connectors.

30. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 30
Back-Annotation
➢After you enter a schematic, you simulate the design to make sure it works as expected.
➢This completes the logical design. Next you move to ASIC physical design and complete the layout.
➢Only after you complete the layout do you know the parasitic capacitance and therefore the delay associated
with the interconnect.
➢This postroute delay information must be returned to the schematic in a process known as back-annotation.
➢Then you can complete a final, postlayout simulation to make sure that the specifications for the ASIC are met.

31. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 31
•Atownplannerworksoutthenumber,types,andsizesofbuildingsinadevelopmentproject.
•Anarchitectdesignseachbuilding,includingthearrangementoftheroomsineachbuilding.
•Thenabuildercarriesouttheconstructionaccordingtothearchitect’sdrawings.
•Electricalwiringisoneofthelaststepsintheconstructionofeachbuilding.
•ThephysicaldesignofASICsisnormally dividedinto
-SystemPartitioning
-Floorplanning
-Placement
-Routing
•Amicroelectronicsystemisthetown,andtheASICsarethebuildings.
•Systempartitioningcorresponds totownplanning,ASICfloorplanningisthearchitect’sjob,
placementisdonebythebuilder,andtheroutingisdonebytheelectrician.Weshalldesignmost,
butnotall,ASICsusingthesedesignsteps.
ASIC Construction

32. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 32
Physical Design
•Figureshowspartofthedesignflow,thephysicaldesign
steps,foranASIC(omittingsimulation,test,andother
logicaldesignstepsthathavealreadybeencovered).
•SomeofthestepsinFiguremight be performed in a different
orderfromthatshown.Forexample,wemight,
dependingonthesizeofthesystem,performsystem
partitioningbeforewedoanydesignentryor synthesis.
Theremaybesomeiterationbetweenthedifferentsteps,too.
•FIGURE:PartofanASICdesignflowshowingthesystem
partitioning,floorplanning,placement,androutingsteps.
•Thesestepsmaybeperformedinaslightlydifferentorder,
iteratedoromitted,dependingonthetypeandsizeofthe
systemand itsASICs.Asthefocusshiftsfromlogicto
interconnect, floorplanning assumes an increasingly important
role.
•Eachofthestepsshowninthefiguremustbeperformed,and
eachdependsonthepreviousstep.However,thetrendis
toward completing thesesteps inaparallelfashionand iterating,
ratherthaninasequentialmanner.

33. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 33
•WemustfirstapplysystempartitioningtodivideamicroelectronicssystemintoseparateASICs.
•Infloorplanning,weestimatesizesandsettheinitialrelativelocationsofthevariousblocksinourASIC
(sometimeswealsocallthischipplanning).Atthesametime,weallocatespaceforthe clockandpowerwiringanddecide
onthelocationoftheI/Oandpowerpads.
•Placement definesthelocationofthelogiccellswithintheflexibleblocksandsetsasidespaceforthe
interconnecttoeachlogiccell.Placementforagate-arrayorstandard-celldesignassignseachlogiccelltoa positionin
arow.
•ForanFPGA,placementchooseswhichofthefixedlogicresourcesonthechipareusedforwhichlogiccells.
FloorplanningandplacementarecloselyrelatedandaresometimescombinedinasingleCADtool.
•Routingmakestheconnectionsbetweenlogiccells.Routingisahardproblembyitselfandisnormallysplit intotwo
distinctsteps,calledglobalandlocalrouting.
•Globalroutingdetermineswheretheinterconnectionsbetweentheplacedlogiccellsandblockswillbe situated.
Onlytheroutestobeusedbytheinterconnectionsaredecidedinthisstep,nottheactuallocationsoftheinterconnections
withinthewiringareas.
•Globalroutingissometimescalledlooseroutingforthisreason.
•Localroutingjoinsthelogiccellswithinterconnections.Informationonwhichinterconnectionareastouse comesfrom
theglobalrouter.
•Onlyathisstageoflayout dowefinallydecideon the width,masklayer,andexactlocationofthe interconnections.Local
routingisalsoknownasdetailedrouting

34. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 34
For your Reference

35. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 35

36. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 36

37. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 37

38. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 38
CAD Tools
• TodevelopaCADtool,itisnecessarytoconverteachofthephysicaldesignstepstoaproblemwith
well-definedgoalsandobjectives.Thegoalsforeachphysicaldesignsteparethethingswemust
achieve.
•Theobjectivesforeachsteparethingswewouldliketomeetonthewaytoachievingthegoals.
SomeexamplesofgoalsandobjectivesforeachoftheASICphysicaldesignstepsareasfollows:
✓Systempartitioning:
-Goal.PartitionasystemintomultipleASICs.
-Objectives.MinimizethenumberofexternalconnectionsbetweentheASICs.KeepeachASIC
smallerthan amaximumsize.
✓Floorplanning:
-Goal.Calculatethesizesofalltheblocksandassignthemto locations.
-Objective.Keepthehighlyconnectedblocksphysicallyclosetogether.
✓Placement:
-Goal.Assigntheinterconnectareasandthelocationofallthelogiccellswithintheflexibleblocks.
-Objectives.MinimizetheASICareaandtheinterconnectdensity.

39. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 39
✓Globalrouting:
-Goal.Determinethelocationofalltheinterconnect.
-Objective.Minimizethetotalinterconnectareaused.
✓Detailedrouting:
-Goal.Completelyroutealltheinterconnectonthechip.
-Objective.Minimizethetotalinterconnectlengthused.
•ThereisnomagicrecipeinvolvedinthechoiceoftheASICphysicaldesignsteps.These
stepshavebeenchosensimplybecause,astoolsandtechniqueshavedevelopedhistorically,
thesestepsprovedtobetheeasiestwaytosplitupthelargerproblemofASICphysical
design.
•Theboundariesbetweenthestepsarenotcastinstone.Forexample,floorplanningand
placementareoftenthoughtofasonestep,andinsometoolsplacementandroutingare
performedtogether

40. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 40
Methods and Algorithms
•ACADtoolneedsmethodsoralgorithmstogenerateasolutiontoeachproblemusingareasonableamountof
computertime.
•Often,thereisnobest solutionpossibletoaparticularproblem,andthetoolsmustuseheuristicalgorithms,
or rulesofthumb,totryandfindagoodsolution.Thetermalgorithmisusuallyreservedforamethod
that alwaysgivesasolution.
•Weneedtoknowhowpracticalanyalgorithmis.WesaythecomplexityofanalgorithmisO(f(n))(read as
orderf(n))ifthereareconstantskandn
0sothattherunningtimeofthealgorithm
T(nislessthan k f(n)foralln> n
0[Sedgewick,1988].
•Herenisameasureofthesizeoftheproblem(numberoftransistors,numberofwires,andsoon).InASIC
design,nisusuallyverylarge.Wehavetobecareful,though.
•Thenotationdoesnotspecifytheunitsoftime.AnalgorithmthatisO(n
2
)nanosecondsmightbebetter
thananalgorithmthatisO (n)seconds,forquitelargevaluesofn.
•ThenotationO(n)referstoanupperlimitontherunningtimeofthealgorithm.Apracticalexamplemay
takelessrunningtime—itisjustthatwecannotproveit.Wealsohavetobecarefuloftheconstantskandn
0.
•Theycanhideoverheadpresentintheimplementation,andmaybelargeenoughtomaskthedependence
onn, uptolargevaluesofn.

41. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 41
The function f (n) is usually one of the following kinds:
✓f(n)=constant.Thealgorithmisconstantintime.Inthiscase,the stepsofthealgorithmarerepeatedonce
orjust afewtimes.Itwouldbeniceifouralgorithmshadthisproperty,butitdoesnotusuallyhappen
inASIC design.
✓f(n)=logn.Thealgorithmislogarithmicintime.Thisusuallyhappenswhenabigproblemis
(possibly recursively)transformedintoasmallerone.
✓f(n)=n.Thealgorithmislinearintime.ThisisagoodsituationforanASICalgorithmthat
works withnobjects.
✓f(n)=nlogn.Thistypeofalgorithmariseswhenalargeproblemissplitintoanumberofsmaller
problems,eachsolvedindependently.
✓f(n)=n
2
.ThealgorithmisquadraticintimeandusuallyonlypracticalforsmallASICproblems.
•Ifthetimeittakestosolveaproblemincreaseswiththesizeoftheproblemataratethatispolynomialbut
fasterthanquadratic(orworseinanexponentialfashion),itisusuallynotappropriateforASICdesign.
•EvenaftersubdividingtheASICphysicaldesignproblemintosmallersteps,eachofthestepsstillresultsin
problemsthatarehardtosolveautomatically.
•Infact,eachoftheASICphysicaldesignsteps,ingeneral,belongstoaclassofmathematicalproblemsknown as
NP-completeproblems.Thismeansthatitisunlikelywecan findan algorithmtosolvethe problemexactly in
polynomialtime.

42. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 42
•Supposewefindapracticalmethodtosolveourproblem,evenifwecanfindasolutionwenow
haveadilemma.
•Howshallweknowifwehaveagoodsolutionif,becausetheproblemisNP-complete,wecannot
findtheoptimumorbestsolutiontowhichtocompareit?Weneedtoknowhowclosewearetothe
optimumsolutiontoaproblem,evenifthatoptimumsolutioncannotbefoundexactly.
•Weneedtomakeaquantitativemeasurementofthequalityofthesolutionthatweareabletofind.
•Often,wecombineseveralparametersormetricsthatmeasureourgoalsandobjectivesinto a
measurementfunctionorobjectivefunction.Ifweareminimizingthemeasurementfunction,itis
acost function.Ifwearemaximizingthemeasurementfunction,wecallthe function again
function(sometimesjustgain).
•NowwearereadytosolveeachoftheASICphysicaldesignstepswiththefollowingitemsinhand:
asetofgoalsandobjectives,awaytomeasurethegoalsandobjectives,andanalgorithmormethod
tofindasolutionthatmeetsthegoalsandobjectives.
•AsdesignersattempttoachieveadesiredASICperformance,theymakeacontinuoustrade-off
betweenspeed,area,power,andseveralotherfactors.
•Presently,CADtoolsarenotsmartenoughtobeabletodothisalone.Infact,currentCADtoolsare
onlycapableoffindingasolutionsubjecttoafew,verysimple,objectives.

43. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 43
System Partitioning
•Microelectronicsystemstypicallyconsistofmanyfunctionalblocks.Ifafunctionalblockistoolargetofit
in oneASIC,wemayhavetosplit,orpartition,thefunctionintopiecesusinggoalsandobjectivesthatwe
need tospecify.
•Forexample,wemightwanttominimisethenumberofpinsforeachASICtominimizepackage cost.We
canuseCADtoolstohelpuswiththistypeofsystempartitioning.
•Figure15.2showsthesystemdiagramoftheSunMicrosystemsSPARCstation1.Thesystemispartitioned
asfollows:thenumbersrefertothelabelsinFigure15.2.
✓NinecustomASICs(1–9)
✓Memorysubsystems(SIMMs,single-in-linememorymodules):CPUcache(10),RAM(11),memorycache
(12,13)
✓SixASSPs(application-specificstandardproducts)forI/O(14–19)
✓AnASSPfortimeofday(20)
✓AnEPROM(21)
✓Videomemorysubsystem(22)
✓Oneanalog/digitalASSPDAC(digital-to-analogconverter)(23)

44. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 44
FIGURE 15.2 The Sun Microsystems
SPARCstation 1 system block diagram.
The acronyms for the various ASICs are
listed in Table 15.1.
•Table 15.1 shows the details of the nine
custom ASICs used in the SPARCstation
1. Some of the partitioning of the system
shown in Figure 15.2 is determined by
whether to use ASSPs or custom ASICs.

45. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 45
•Some of these design
decisionsarebasedon
intangible issues:timeto
market,previous experience
withatechnology,and the
ability toreusepartofa
designfrom a previous
product.
•NoCADtoolscanhelpwith
suchdecisions.Thegoalsand
objectives are toopoorly
defined,andfindingaway
to measurethesefactorsis
very difficult.

46. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 46
•Table 15.2 shows the partitioning of the SPARCstation 10 so you can compare it to the SPARCstation 1.
•Notice that the gate counts of nearly all of the SPARCstation 10 ASICs have increased by a factor of 10, but the pin counts
have increased by a smaller factor.

47. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 47
Estimate ASIC size
•Table15.3showssomeusefulnumbersforestimatingASICdiesize.Supposewewishtoestimatethediesize
ofa40k-gateASICina0.35mmgatearray,three-levelmetalprocesswith166I/Opads.ForthisASICthe
minimumfeaturesizeis0.35mm.
•Thusl(one-halftheminimumfeaturesize)=0.35mm/2=0.175mm.UsingourdataandTable15.3,wecan
derivethefollowinginformation.Weknowthat0.35mmstandard-celldensityisroughly5¥10
–4
gate/l
2
.
Fromthiswecancalculatethegatedensityfora0.35mmgatearray:
gate density = 0.35 mm standard-cell density ¥ (0.8 to 0.9)
= 4 ¥ 10
4
to 4.5 ¥ 10
4
gate/ l
2
. (15.1)
This gives the core size (logic and routing only) as
(4 ¥ 10
4
gates/gate density) ¥ routing factor ¥ (1/gate-array utilization)
= 4 ¥ 10
4
/ (4 ¥ 10
4
to 4.5 ¥ 10
4
) ¥ (1 to 2) ¥ 1/ (0.8 to 0.9) = 10
4
to 2.5 ¥ 10
8
1
2 = 4840 to 11,900 mil
2
.
We shall need to add (0.175/0.5) ¥ 2 ¥ (15 to 20) = 10.5 to 21 mil (per side) for the pad heights (we included the
effects of scaling in this calculation). With a pad pitch of 5 mil and roughly 166/4 = 42 I/Os per side (not counting
any power pads), we need a die at least 5 ¥ 42 = 210 mil on a side for the I/Os. Thus, the die size must be at least 210
¥ 210 = 4.4 ¥ 10
4
mil
2
to fit 166 I/Os. die area only 1.19 ¥ 10
4
/(4.4 ¥ 10
4
) = 27 % (at most) is used by the core logic.
This is a severely pad-limited design and we need to rethink the partitioning of this system.

48. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 48

49. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 49
FPGA Partitioning
•ManydifferentissueshavetobeconsideredwhenpartitioningacomplexsystemintocustomASICs.
•Therearenocommercialtoolsthatcanhelpuswithalloftheseissues—aspreadsheetisthebesttoolinthis
case.ThingsarealittleeasierifwelimitourselvestopartitioningagroupoflogiccellsintoFPGAs—and
restricttheFPGAstobeallofthesametype.
ATM (AsynchronousTransferMode)Simulator
-WeshallexamineahardwaresimulatorforAsynchronousTransferMode(ATM).
-ATMisasignalingprotocolformanydifferenttypesoftraffic,includingconstantbitrates(voicesignals)as
wellasvariablebitrates(compressedvideo).
-TheATMConnectionSimulatorisacardthatisconnectedtoacomputer.Undercomputercontrolthecard
monitorsandcorruptstheATMsignalstosimulatetheeffectsofrealnetworks.
-Anexamplewouldbetotestdifferentvideocompressionalgorithms.Compressedvideoisverybursty(brief
periodsofveryhighactivity),hasverystrictdelayconstraints,andissusceptibletoerrors.
-ATMis based onATMcells(packets).EachATMcell has53bytes:a5-byteheader anda48-byte
payload;Figure15.4showstheformatoftheATMpacket.TheATMConnectionSimulatorlooksattheentire
headerasanaddress

50. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 50
FIGURE 15.4 Theasynchronoustransfermode(ATM)cellformat.
TheATMprotocoluses53-bytecellsor packetsofinformationwithadatapayloadandheaderinformation
forroutinganderrorcontrol

51. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 51
•Figure15.5showsthesystemblockdiagramoftheATMsimulatordesignedbyCraigFujikamiatthe
University ofHawaii.Now produced byAdTech,the simulator emulatesthecharacteristicsofasingle
connectioninanATMnetworkandmodelsATMtrafficpolicing,ATMcelldelays,andATMcellerrors.The
simulatorispartitionedintothethreemajorblocks,showninFigure15.5,andconnectedtoanIBM-
IBM-compatiblePCthroughanIntel80186controllerboardtogetherwithaninterfaceboard.Thesethreeblocks
are
➢The traffic policer, which regulates the input to the simulator.
➢The delay generator, which delays ATM cells, reorders ATM cells, and inserts ATM cells with valid ATM cell
headers.
➢The error generator, which produces bit errors and four random variables that are needed by the other two
blocks.
The error generator performs the following operations on ATM cells:
1.Payload bit error ratio generation. The user specifies the Bernoulli probability, pBER , of the payload bit error
ratio.
2.Random-variable generation for ATM cell loss, misinsertion, reordering, and deletion.
The delay generator delays, misinserts, and reorders the target ATM cells. Finally, the traffic policer performs the
following operations:
1. Performs header screening and remapping.
2. Checks ATM cell conformance.
3. Deletes selected ATM cells.

52. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 52
Table 15.7 shows the partitioning of the ATM board into 12 Lattice Logic FPGAs (ispLSI 1048)
corresponding to the 12 blocks shown in Figure 15.5 . The Lattice Logic ispLSI 1048 has 48 GLBs (generic
logic blocks) on each chip. This system was partitioned by handwith difficulty.
TABLE 15.7 Partitioning of the ATM board using Lattice Logic ispLSI 1048 FPGAs.
Each FPGA contains 48 generic logic blocks (GLBs).
Chip # Size Chip # Size
1 42GLBs 7 36GLBs
2 64k-bit¥8SRAM 8 22GLBs
3 38 GLBs 9 256 k-bit ¥ 16 SRAM
4 38GLBs 10 43GLBs
5 42GLBs 11 40GLBs
6 64k-bit¥16SRAM 12 30GLBs

53. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 53
Partitioning Methods
•Systempartitioningrequiresgoalsandobjectives,methodsandalgorithmstofindsolutions,andwaysto
evaluatethesesolutions.Westartwithmeasuringconnectivity,proceedtoanexamplethatillustratesthe
conceptsofsystempartitioningandthentothealgorithmsforpartitioning.
•AssumethatwehavedecidedwhichpartsofthesystemwilluseASICs.Thegoalofpartitioningistodividethis
part ofthesystemsothat eachpartitionis asingleASIC.Todothis wemay needtotake intoaccount anyorall
ofthefollowingobjectives:
✓AmaximumsizeforeachASIC
✓AmaximumnumberofASICs
✓AmaximumnumberofconnectionsforeachASIC
✓AmaximumnumberoftotalconnectionsbetweenallASICs
•PartitioningMethods
1.ConstructivePartitioning
2.IterativePartitioningImprovement
3.TheKernighan–LinAlgorithm
4.The Ratio-CutAlgorithm
5.TheLook-aheadAlgorithm
6.SimulatedAnnealing

54. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 54
Constructive Partitioning
•Themostcommonconstructivepartitioningalgorithmsuseseedgrowthorclustergrowth.Asimpleseed-
growthalgorithmforconstructivepartitioningconsistsofthefollowingsteps:
1.Startanewpartitionwithaseedlogiccell.
2.Considerallthelogiccellsthatarenotyetinapartition.Selecteachoftheselogiccellsinturn.
3.Calculateagainfunction,g(m),thatmeasuresthebenefitofaddinglogiccellmtothecurrentpartition.
Onemeasureofgainisthenumberofconnectionsbetweenlogiccellmandthecurrentpartition.
4.Addthelogiccellwith thehighestgaing(m)tothecurrentpartition.
5.Repeattheprocessfromstep2.Ifyoureachthelimitoflogiccellsinapartition,startagainatstep1.
•Wemaychoosedifferentgainfunctionsaccordingtoourobjectives(butwehavetobecarefultodistinguish
betweenconnectionsandnets).Thealgorithmstartswiththechoiceofaseedlogiccell(seedmodule,orjust
seed).Thelogiccellwiththemostnetsisagoodchoiceastheseedlogiccell.
•Youcanalsouseasetofseedlogiccellsknownasacluster.Somepeoplealsousethetermclique—borrowed
fromgraphtheory.Acliqueofagraphisasubsetofnodeswhereeachpairofnodesisconnectedbyanedge—
likeyourgroupoffriendsatschoolwhereeveryoneknowseveryoneelseinyourclique.
•Insometoolsyoucanuseschematicpages(attheleaforlowesthierarchicallevel)asastartingpointfor
partitioning.Ifyouuseahigh-leveldesignlanguage,youcanuseaVerilogmodule(differentfromacircuit
module)orVHDLentity/architectureasseeds(againattheleaflevel).

55. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 55
Iterative Partitioning Improvement
•Themostcommoniterativeimprovementalgorithmsarebasedoninterchangeandgroup
migration.The processofinterchanging(swapping)logiccellsinanefforttoimprovethepartitionis
aninterchangemethod. Iftheswapimprovesthepartition,weacceptthetrialinterchange;otherwise,
weselectanewsetoflogiccellstoswap.
•Thereisalimittowhatwecanachievewithapartitioningalgorithmbasedonsimple
interchange.For example,Figure15.7(c)showsapartitioningofthenetworkofpartausinga
constructedpartitioning algorithmwithlogiccellCastheseed.Togetfromthesolutionshownin
partctothesolutionofpartb,whichhasaminimumnumberofexternalconnections,requiresa
complicatedswap.
•Thethreepairs:DandF,JandK,CandLneedtobeswapped—allatthesametime.Itwould
takeavery longtimetoconsiderallpossibleswapsofthiscomplexity.Asimpleinterchange
algorithmconsidersonly onechangeandrejectsitimmediatelyifitisnotanimprovement.
Algorithmsofthistypearegreedy algorithmsinthesensethattheywillacceptamoveonlyifit
providesimmediatebenefit.
•Suchshort-sightednessleadsanalgorithmtoalocalminimumfromwhichitcannotescape.Stuckin
avalley, agreedyalgorithmisnotpreparedtowalkoverahilltoseeifthereisabettersolutioninthe
nextvalley.ThistypeofproblemoccursrepeatedlyinCADalgorithms.

56. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 56
•Group migration consists of swapping groups of logic cells between partitions. The group
migration algorithmsarebetterthansimpleinterchangemethodsatimprovingasolutionbut
aremorecomplex.Almost all group migration methodsare based on the powerful and general
Kernighan–Lin algorithm(K–Lalgorithm)thatpartitionsagraph[KernighanandLin,1970].
•Theproblemofdividingagraphintotwopieces,minimizingthenetsthatarecut,isthemin-
cutproblem—a veryimportantoneinVLSIdesign.Asthenextsectionshows,theK–L
algorithmcanbeappliedtomany differentproblemsinASICdesign.

57. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 57
FIGURE 15.7 Partitioning example.
(a)We wish to partition this network into three ASICs with no
more than four logic cells per ASIC.
(b)A partitioning with five external connections (nets 2, 4, 5, 6,
and 8)the minimum number.
(c)A constructed partition using logic cell C as a seed. It is
difficult to get from this local minimum, with seven external
connections (2, 3, 5, 7, 9,11,12), to the optimum solution of
b.

58. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 58
The Kernighan–Lin Algorithm
•Figure15.8illustratessomeofthetermsanddefinitionsneededtodescribetheK–Lalgorithm.External
edgescrossbetweenpartitions;internaledgesarecontainedinsideapartition.Consideranetworkwith
2mnodes(wheremisaninteger)eachofequalsize.Ifweassignacosttoeachedgeofthenetworkgraph,
wecandefineacostmatrixC=c
ij,wherec
ij=c
jiandc
ii=0.Ifallconnectionsareequalinimportance,
theelementsofthecostmatrixare1or0,andinthisspecialcaseweusuallycallthematrixtheconnectivity
matrix.Costshigherthan1couldrepresentthenumberofwiresinabus,multipleconnectionstoasingle
logiccell,ornetsthatweneedtokeepclosefortimingreasons.
FIGURE 15.8 Terms used by the Kernighan-Lin
partitioning algorithm.
(a)An example network graph.
(b)The connectivity matrix, C; the columns and rows are
labeled to help you see how the matrix entries
correspond to the node numbers in the graph. For
example, C 17 (column 1, row 7) equals 1 because
nodes 1 and 7 are connected. In this example, all edges
have an equal weight of 1, but in general, the edges
may have different weights.

59. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 59
•Supposewealreadyhavesplitanetworkintotwopartitions,AandB,eachwithmnodes(perhapsusinga
constructedpartitioning).OurgoalnowistoswapnodesbetweenAandBwiththeobjectiveofminimizing
thenumberofexternaledgesconnectingthetwopartitions.Eachexternaledgemaybeweightedbyacost,and
ourobjectivecorrespondstominimizingacostfunctionthatweshallcallthetotalexternalcost,cutcost,
orcutweight,W:
•InFigure15.8(a)thecutweightis4(alltheedgeshaveweightsof1).Inordertosimplifythe
measurementofthechangeincutweightwhenweinterchangenodes,weneedsomemoredefinitions.
First,foranynodeainpartitionA,wedefineanexternaledgecost,whichmeasurestheconnectionsfrom
nodeatoB,

60. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 60
•Forexample,inFigure 15.8 (a)E1=1,andE3=0.Second,wedefinetheinternaledgecosttomeasurethe
internalconnectionstoa ,
•So,inFigure 15.8(a),I1=0,andI3=2.Wedefinetheedgecosts forpartitionBina similarway(soE8
=2,andI8= 1).Thecostdifferenceisthedifferencebetweenexternaledgecostsand internaledgecosts,
•Thus,inFigure15.8(a)D1=1,D3=–2,andD8=1.NowpickanynodeinA,andanynodeinB.If
weswapthesenodes,aandb,weneedtomeasurethereductionincutweight,whichwecallthegain,g.
Wecanexpressgintermsoftheedgecostsasfollows:

61. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 61
•Thelasttermaccountsforthefactthataandbmaybeconnected.
•So,inFigure15.8(a),ifweswapnodes1and6,then
g=D
1+D
6–2c
16=1+1.
Ifweswapnodes2and8,then
g=D
2+D
8–2c
28=1+2–2.
•TheK–Lalgorithmfindsagroupofnodepairstoswapthatincreasesthegaineventhoughswapping
individualnodepairsfromthatgroupmightdecreasethegain.Firstwepretendtoswapallofthenodesa
pairatatime.Pretendswapsarelikestudyingchessgameswhenyoumakeaseriesoftrialmovesinyour
head.
•Thisisthealgorithm:.
1.Findtwonodes,aifromA,andbifromB,sothatthegainfromswappingthemisamaximum.Thegain
is
g
i=D
ai+D
bi–2 c
aibi.(15.18)
2.Nextpretendswapaiandbievenifthegaingiiszeroornegative,anddonotconsideraiandbi
eligibleforbeingswappedagain.
3.Repeatsteps1and2atotalofmtimesuntilallthenodesofAandBhavebeenpretendswapped.Weare
backwherewestarted,butwehaveorderedpairsofnodesinAandBaccordingtothegainfrom
interchangingthosepairs.

62. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 62
4.Nowwecanchoosewhichnodesweshallactuallyswap.Supposeweonlyswapthefirstnpairsofnodes
thatwefoundintheprecedingprocess.InotherwordsweswapnodesX=a1,a2,…,anfromAwith
nodesY=b1,b2,…,bnfromB.Thetotalgainwouldbe
5.WenowchoosencorrespondingtothemaximumvalueofG
n.
•IfthemaximumvalueofG
n>0,thenweswapthesetsofnodesXandYandthusreducethecutweight
byG
n.Weusethisnewpartitioningtostarttheprocessagainatthefirststep.IfthemaximumvalueofG
n=
0,thenwecannotimprovethecurrentpartitioningandwestop.Wehavefoundalocallyoptimumsolution.
•Figure15.9showsanexampleofpartitioningagraphusingtheK–Lalgorithm.Eachcompletionofsteps1
through5isapassthroughthealgorithm.KernighanandLinfoundthattypically2–4passeswererequiredto
reachasolution.
•ThemostimportantfeatureoftheK–Lalgorithmisthatwearepreparedtoconsidermoveseventhoughthey
seemtomakethingsworse.ThisislikeunravelingatangledballofstringorsolvingaRubik’scubepuzzle.
•Sometimesyouneedtomakethingsworsesotheycangetbetterlater.

63. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 63
FIGURE 15.9 Partitioning a graph using the
KernighanLin algorithm.
(a) Shows how swapping node 1 of partition A
with node 6 of partition B results
in a gain of g = 1.
(b) A graph of the gain resulting from swapping
pairs of nodes.
(c) The total gain is equal to the sum of the
gains obtained at each step.

64. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 64
•TheK–Lalgorithmworkswellforpartitioninggraphs.However,therearethefollowingproblemsthatwe
needtoaddressbeforewecanapplythealgorithmtonetworkpartitioning:
✓Itminimizesthenumberofedgescut,notthenumberofnetscut.
✓Itdoesnotallowlogiccellstobedifferentsizes.
✓Itisexpensiveincomputationtime.
✓Itdoesnotallowpartitionstobeunequalorfindtheoptimumpartitionsize.
✓Itdoesnotallowforselectedlogiccellstobe fixedinplace.
✓Theresultsarerandom.
✓Itdoesnotdirectlyallowformorethantwo partitions.

65. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 65
The Ratio-Cut Algorithm
•Theratio-cutalgorithmremovestherestrictionofconstantpartitionsizes.ThecutweightWforacutthat
dividesanetworkintotwopartitions,AandB,is givenby
•TheK–LalgorithmminimizesWwhilekeepingpartitionsAandBthesamesize.Theratioofacutisdefined
as
•Inthisequation|A|and|B|arethesizesofpartitionsAandB.Thesizeofapartitionisequaltothenumber
ofnodesitcontains(alsoknownasthesetcardinality).
•ThecutthatminimizesRiscalledtheratiocut.Theoriginaldescriptionoftheratio-cutalgorithmusesratio
cutstopartitionanetworkintosmall,highlyconnectedgroups.Thenyouformareducednetworkfromthese
groups—eachsmallgroupoflogiccellsformsanodeinthereducednetwork.Finally,youusetheF–M
algorithmtoimprovethereducednetwork

66. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 66
The Look-ahead Algorithm
•BoththeK–LandF–Malgorithms consideronlytheimmediategaintobe madebymovinganode.When
thereisatiebetweennodeswithequalgain(as oftenhappens),thereisnomechanism to makethebest
choice.
•Thisislikeplayingchesslookingonlyonemoveahead.Figure15.11showsanexample oftwonodesthat
haveequalgains,butmovingoneofthenodeswillallowamovethathasahighergainlater.
•We call the gain for the initial move the first-level gain. Gains from subsequent moves are then second-level and
higher gains. We can define a gain vector that contains these gains.
•Figure 15.11 shows how the first-level and second-level gains are calculated. Using the gain vector allows us to
use a look-ahead algorithm in the choice of nodes to be swapped. This reduces both the mean and variation in the
number of cuts in the resulting partitions.

67. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 67
▪FIGURE 15.11 An example of network
partitioning that shows the need to look
ahead when selecting logic cells to be moved
between partitions. Partitionings (a), (b), and
(c) show one sequence of moves,
partitionings (d), (e), and (f) show a second
sequence.
▪The partitioning in (a) can be improved by
moving node 2 from A to B with a gain of 1.
▪The result of this move is shown in (b).
▪This partitioning can be improved by moving
node 3 to B, again with a gain of 1.
▪The partitioning shown in (d) is the same as
(a). We can move node 5 to B with a gain of
1 as shown in (e), but now we can move
node 4 to B with a gain of 2.

68. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 68
Simulated Annealing
•Adifferentapproachtosolvinglargegraphproblems(andothertypesofproblems)thatariseinVLSI
layout,includingsystempartitioning,usesthesimulated-annealingalgorithm[Kirkpatricketal.,1983].
Simulatedannealingtakesanexistingsolutionandthenmakessuccessivechangesinaseriesofrandom
moves.
•Eachmoveisacceptedorrejectedbasedonanenergyfunction,calculatedforeachnewtrial
configuration.Theminimumsoftheenergyfunctioncorrespondtopossiblesolutions.
•Thebestsolutionistheglobalminimum.Sofarthedescriptionofsimulatedannealingissimilartothe
interchangealgorithms,butthereisanimportantdifference.Inaninterchangestrategyweacceptthenew
trialconfigurationonlyiftheenergyfunctiondecreases,whichmeansthenewconfigurationisan
improvement.
•However,inthesimulated-annealingalgorithm,weacceptthenewconfigurationeveniftheenergy
functionincreasesforthenewconfiguration—whichmeansthingsaregettingworse.Theprobabilityof
acceptingaworseconfigurationiscontrolledbytheexponentialexpressionexp(–DE/T),whereDEis
theresultingincreaseintheenergyfunction.
•TheparameterTisavariablethatwecontrolandcorrespondstothetemperatureintheannealingofa
metalcooling(thisiswhytheprocessiscalledsimulatedannealing).

69. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 69
•Weacceptmovesthatseeminglytakeusawayfromadesirablesolutiontoallowthesystemtoescapefroma
localminimumandfindother,better,solutions.
•Thenameforthisstrategyishillclimbing.Asthetemperatureisslowlydecreased,wedecreasethe
probabilityofmakingmovesthatincreasetheenergyfunction.
•Finally,asthetemperatureapproacheszero,werefusetomakeanymovesthatincreasetheenergyofthe
systemandthesystemfallsandcomestorestatthenearestlocalminimum.
•Hopefully,thesolutionthatcorrespondstotheminimumwehavefoundisagoodone.Thecriticalparameter
governingthebehaviorofthesimulated-annealingalgorithmistherateatwhichthetemperatureTisreduced.
Thisrateisknownasthecoolingschedule.Oftenwesetaparameterathatrelatesthetemperatures,TiandT
i+1,attheithandi+1thiteration:
•Tofindagoodsolution,alocalminimumclosetotheglobalminimum,requiresahighinitialtemperatureand
aslowcoolingschedule.
•Thisresultsinmanytrialmovesandverylongcomputerruntimes[Rose,Klebsch,andWolf,1990].Ifwe
arepreparedtowaitalongtime(foreverintheworstcase),simulatedannealingisusefulbecausewecan
guaranteethatwecanfindtheoptimumsolution.

70. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 70
Questions
1.Draw the IEEE recommended dimensions and their constructions for logic gate symbols, NAND gate and XOR gate.
2.Explain the Hierarchical design with a suitable example.
3.Describe the schematic entry method in ASIC Design.
4.Explain annotation in ASIC Design.
5.Explain the vectored instances and buses for 16-bit D-latch and draw the diagram for 4-bit D-latch.
6.Discuss the vectored instances for 16-bit D-Latch.
7.Discuss the local nets and external nets in the ASIC design.
8.Explain the Schematic ICONs and Symbols with suitable examples.
9.What is Netlist Screener? List the errors that can be found by netlist screeners and mention the methods to overcome.
10.Explain the following with respect to low-level design entry:
i.Edit in place
ii.Schematic icons and symbols
iii.Hierarchical design
iv.Nets
v.Vectored instances

71. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 71
1.Enumerate the physical design/ASIC design of ASICs.
2.List steps in ASIC Physical Design and describe the goals and objectives of each step.
3.Explain the system partitioning with a proper example
4.Discuss the FPGA Partitioning by taking the example of the ATM simulator cell format
5.Describe the list of partitioning methods and explain any two of them
6.Explain the following partitioning methods
i. Kernighan–Lin Algorithm
ii. Constructive Partitioning
5. Explain the following partitioning methods
i. Iterative partitioning improvement
ii. Ratio-Cut Algorithm
6. Explain the following partitioning methods
i. Look Ahead Algorithm
ii. Simulated Annealing
7.With relevant equations, explain KL algorithm. Construct the connectivity matrix for the network shown in the
figure below. Also, find the gain in the network graph shown if:
i.Nodes 1 and 6 are swapped.
ii.Nodes 2 and 8 are swapped.
Questions

72. Application – Specific Integrated Circuits [ASIC]
Hemanth T S
M.Tech, Assistant Professor, Dept., of E&CE, AIET, Moodbidri. 72
THANK YOU…☺