ARCHITECTURE OF 80386 IN DETAIL SPPU COMPUTER ENGINEERING SEM 4

Course Contents
Introduction to 80386
Brief History of Intel Processors, 80386 DX Features and Architecture, Programmers Model, Operating modes, Addressing modes and data types.
Applications Instruction Set: Data Movement Instructions, Binary Arithmetic Instructions, Decimal Arithmetic Instructions, Logical Instructions, Control Transfer Instructions, String and Character Transfer Instructions, Instructions for Block Structured Language, Flag Control Instructions,
Coprocessor Interface Instructions, Segment Register Instructions, Miscellaneous Instructions.

1. 1
Hope Foundation's
International Institute of Information
Technology, Pune
Department of Computer Engineering
Academic Year : 2024-25, Semester -II
SUBJECT: MICROPROCESSOR
CLASS: SE
PREPAIRED BY
SWATI D. JADHAV
[email protected]
JANUARY 14, 2025

2. UNIT I
INTRODUCTION TO 80386
(07 HOURS)
•CO1:Exhibitskillofassemblylanguage
programmingfortheapplication.
•CO2:ClassifyProcessorarchitectures.
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures. 2JANUARY 14, 2025

3. OUTINE
●80386 MICROPROCESSOR
●FEATURES OF 80386
●OPERATING MODES OF 80386
●ARCHITECTURE OF 80386 MICROPROCESSOR
●VERSIONS
●PROGRAMER MODELS
●OPERATING MODES
●ADDRESSING MODES
●DATA TYPES
●APPLICATION INSTRUCTION SETS
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
3
JANUARY 14, 2025

4. 80386 MICROPROCESSOR
•80386Microprocessor
•A32-bit processor
•Holds the ability to carry out 32-bit operations
in one cycle.
•It has a data and address bus of 32-bit each.
Thus has the ability to address 4 GB (or 2
32
) of
physical memory.
CO1: Exhibit skill of assembly language programming for the application. CO2:
Classify Processor architectures.
4JANUARY 14, 2025

5. KEY FEATURES
•Multitaskinginternaldedicatedhardware
thatpermitsmultitasking.
•Protectioncapabilityarethetwokey
characteristicsofthe80386microprocessor.
80386has
CO1: Exhibit skill of assembly language programming for the application. CO2: Classify
Processor architectures.
5JANUARY 14, 2025

6. WHY 80386?
•8085isa8-bitmicroprocessor.
•8086isa16-bitmicroprocessor.
•80286wasanadvancementof8086withsome
additionalcharacteristics.
•Butwiththeadventoftechnologyintelintroduceda
32-bitmicroprocessorwhoseprocessingspeedwas
twicethatofthe80286microprocessor.
•Thiswasan80386microprocessorthatwasdesigned
byIntelinOctober1985.
•Anupgradedversionofthe80286microprocessor.
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
6JANUARY 14, 2025

7. FEATURES OF 80386
✔32-bit microprocessor.
✔Has ALU 32-bit.
✔Holds data bus of 32-bit.
✔Address bus of 32 bit.
✔Physical memory addressability of 4 GB
✔Virtual memory addressability of 64 TB.
✔Supports a variety of operating clock frequencies-16 MHz,
20 MHz, 25 MHz, and 33 MHz.
✔It offers 3 stage pipeline:
1. Fetch
2. Decode
3. Execute.
✔As it supports simultaneous fetching, decoding, and
execution inside the system.
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
7JANUARY 14, 2025

8. OPERATING MODES OF 80386
•80286supportstwooperatingmodes.
1.Realaddressmode
2.Protectedvirtualaddressmode.
•80386supports3operatingmodes.
1.Real
2.Protected
3.Vrtualrealmode.
•Initially,the80286wasbootedinrealmode.However,to
havebetteroperatingperformance,separatesoftware
commandisusedtoswitchfromtherealmodetothe
protectedmode.
•Butitrequirestheresettingofthemicroprocessorinorder
toswitchtorealmodefromprotectedmode.
•Thisdrawbackiseliminatedin80386thatallowsthe
switchingbetweenthemodesusingsoftwarecommands.
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
8JANUARY 14, 2025

9. OPERATING MODES OF 80386
1.Protectedmode:
Operatesinasimilarwaylike80286butoffershighermemory
addressingability.
2.Virtualmode:
Theoverallmemoryof80386canbedividedintovariousvirtual
machines.
Allofthemactsasaseparatecomputerwith8086microprocessor.
Thismodeisalsocalledvirtual8086modeorV86mode.
3.Virtualrealmode:
Thismodeallowsthesystemtoexecutemultipleprogramsinthe
protectedmemory.
Incaseaprogramataparticularmemorygetscrashedthenitwillnot
causeanyadverseeffectontheotherpartofthememory.
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
9JANUARY 14, 2025

10. ARCHITECTURE OF 80386
MICROPROCESSOR
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
10
5
2
3
4
1
JANUARY 14, 2025

11. ARCHITECTURE OF 80386
MICROPROCESSOR
•Basically, it has 5 functional units which are as
follows:
1.Bus Interface Unit
2.Code Fetch Unit
3.Instruction Decode Unit
4.Execution Unit
5.Memory Management Unit
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
11JANUARY 14, 2025

12. 1. BUS INTERFACE UNIT (BIU)
CO1: Exhibit skill of assembly language programming for the application. CO2: Classify
Processor architectures.
12JANUARY 14, 2025

13. 1. BUS INTERFACE UNIT (BIU)
•BIUholdsa32-bitbidirectionaldatabusaswellasa
32-bitaddressbus.
•Wheneveraneedforinstructionoradatafetchis
generatedbythesystemthentheBIUgenerates
signals(accordingtothepriority)foractivatingthe
dataandaddressbusinordertofetchthedata
fromthedesiredaddress.
•TheBIUconnectstheperipheraldevicesthrough
thememoryunit.
•Controlstheinterfacingofexternalbuseswiththe
coprocessors.
CO1: Exhibit skill of assembly language programming for the application. CO2: Classify
Processor architectures.
13JANUARY 14, 2025

14. 2. CODE PRE-FETCH UNIT
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
14JANUARY 14, 2025

15. 2. CODE PREFETCH UNIT
•ThecodePre-fetchunitfetchesthatinstructionfromthememoryand
storesitina16-bytepre-fetchqueue.
•Sotospeeduptheoperationthisunitfetchestheinstructionsinadvance
andthequeuestorestheseinstructions.
•Thesequenceinwhichtheinstructionsarefetchedandgetsstoredinthe
queuedependsontheordertheyexistinthememory.
•Itistobenotedherethat,codeprefetchingholdslowerprioritythan
datatransferring.
•Aswheneveraneedfordatatransferisgeneratedbythesystemthen
immediatelythecodepre-fetcherleavescontroloverthebuses.
•SothattheBIUcantransfertherequireddata.
•Butprefetchingofinstructionandstoringitinthequeuereducesthewait
forthe upcoming instructionto almost zero.
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
15JANUARY 14, 2025

16. 3. INSTRUCTION DECODE UNIT
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
16JANUARY 14, 2025

17. 3. INSTRUCTION DECODE UNIT
•Weknowthatinstructionsinthememoryare
storedintheformofbits.
•So,thisunitdecodestheinstructionsstoredin
theprefetchqueue.
•Basicallythedecoderchangesthemachine
languagecodeintoassemblylanguageand
transfersittotheprocessorforfurther
execution.
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
17JANUARY 14, 2025

18. 4. EXECUTION UNIT
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
18JANUARY 14, 2025

19. 4. EXECUTION UNIT
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
19JANUARY 14, 2025

20. 4. EXECUTION UNIT
•Thedecodedinstructionsarestoredinthedecoded
instructionqueue.
•So,theseinstructionsareprovidedtotheexecution
unitinordertoexecutetheinstructions.
•Theexecutionunitcontrolstheexecutionofthe
decodedinstructions.
•Thisunithasa32-bitALU,thatperformstheoperation
over32-bitdatainonecycle.
•Also,itconsistsof8generalpurposeaswellas8
specialpurposeregisters.
•Theseareusedfordatahandlingandcalculationof
offsetaddress.
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
20JANUARY 14, 2025

21. 5. MEMORY MANAGEMENT UNIT
•This unit has two separate units within it.
These are
•A. Segmentation Unit and
•B. Paging Unit
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
21JANUARY 14, 2025

22. A. Segmentation unit
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
22JANUARY 14, 2025

23. A. Segmentation unit
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
23JANUARY 14, 2025

24. A. Segmentation unit
•Thesegmentationunitplaysavitalroleinthe80836microprocessor.It
offersaprotectionmechanisminordertoprotectthecodeordata
presentinthememoryfromapplicationprograms.Itgives4level
protectiontothedataorcodepresentinthememory.Everyinformation
inthememoryisassignedaprivilegelevelfromPL0toPL3.
•Here,PL0holdsthehighestpriorityandPL3holdsthelowestpriority.
•Supposeafile(eitherdataorcode)isneededtobeaccessedisstoredin
thememoryatPL0.ThenonlythoseprogramswhichareworkingatPL0
wouldbeabletoaccessthatfile.Whileotherprogramswillnotbeableto
accessthesame.Also,ifafileispresentatPL1,thenprogramsofPL0and
PL1bothcanaccessit.AsPL0hasahigherprioritythanPL1.So,for
protectionpurposes,themainpartoftheOSisstoredinPL0whilePL3
holdstheuserprograms.Providingprotectiontothedataorcodeinside
thesystemisthemostadvantageousfactorthatwasfirstgivenbythe
80386microprocessor.
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
24JANUARY 14, 2025

25. B. PAGING UNIT
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
25JANUARY 14, 2025

26. B. PAGING UNIT
•Thepagingunitoperatesonlyinprotectedmode.
•Itchangesthelinearaddressintoaphysicaladdress.
•Astheprogrammeronlyprovidesthevirtualaddressandnotthephysical
address.Thesegmentationunitcontrolstheactionofthepagingunit,as
thesegmentationunithastheabilitytoconvertthelogicaladdressinto
thelinearaddressatthetimeofexecutinganinstruction.
•Basically,itchangestheoveralltaskmapintopagesandeachpagehasa
sizeof4K.
•Thisallowsthehandlingoftasksintheformofpagesratherthan
segments.
•Thepagingunitsupportsmultitasking.
•Thisissobecausethephysicalmemoryisnotrequiredtoholdthewhole
segmentofanytask.Despitethis,onlythatpartofthesegmentwhichis
neededtobecurrentlyexecutedmustbestoredinthatmemorywhose
physicaladdressiscalculatedbythepagingunit.Thisresultantlyreduces
thememoryrequirementandhencethisfreesthememoryforother
tasks.Thusbythiswegetaneffectivewayformanagingthememoryto
supportmultitasking.
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
26JANUARY 14, 2025

27. 80386 VERSIONS
•1.80386SX:TheSXstandsforsingleexecution
Holdsadatabusof16-bit.
•2.80386DX:TheDXstandsfordoubleexecution
Hasadatabusof32-bit.
•Normally80386is80386DXhaving32-bitdatabus.
•Butsometimesasystemhavingan8086microprocessorneedsto
improveitsperformanceaswellasprotection.Andweknowthat
8086isa16-bitmicroprocessor,thatoperateson2banks.
•80386ingeneralhasa32-bitdatabusthatneeds4banks.
•Toaccesssomeofthefeaturesof80386inasystemhaving8086
processor,weuse80386SXasaprocessorhavingadatabusof16-
bit.
•Thus,inthiscase,asystemcansystembeupgradedtofacilitiesof
80386bysimplychangingtheprocessordespitechangingthe
overall.Thisisthereasonwhywehave80386SXversionofthe
80386microprocessor.
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.
27
JANUARY 14, 2025

28. Programmers Model
Includes the registers, flags, and segments that a programmer interacts with
during coding.
1.General-Purpose Registers:
EAX, EBX, ECX, EDX: 32-bit general-purpose registers used for various
arithmetic, logical, and data manipulation operations.
ESI, EDI: Used for sourceand destinationaddressing during string
operations.
EBP: Base pointer, used for stack framesin procedures.
ESP: Stack pointer, points to the top of the stack.
1.Segment Registers:
CS (Code Segment): Holds the base address for code instructions.
DS (Data Segment): Points to data storage locations.
SS (Stack Segment): Points to the stack.
ES, FS, GS: Additional segment registers for memory management.
28JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

29. Programmers Model
3. Control Registers:
CR0: Controls the processor's operating mode (e.g., protected
mode,paging,andothersystemcontrolfeatures).
CR2:Holdstheaddressofthelastpagefault.
CR3:Pointstothebaseofthepagedirectoryinpaging.
4. Flags Register (EFLAGS):
The EFLAGSregister contains various flags that indicate the results of
arithmeticorlogicoperations(suchastheZeroFlag,CarryFlag,etc.).
Italsocontainscontrolflagsforenablinginterruptsandswitching
betweenoperatingmodes(e.g.,theInterruptFlag,DirectionFlag).
29JANUARY 14, 2025
CO1: Exhibit skill of assembly language
programming for the application. CO2:
Classify Processor architectures.

30. Operating Modes
The80386supportsdifferentoperatingmodes,whichdefinehowtheprocessor
interactswithmemoryandexternaldevices.
1.RealMode:
○InRealMode,theprocessoroperatesasan8086-compatibleprocessor,
addressingonlyupto1MBofmemory(segmentedmemory).
○Thismodedoesnotprovidememoryprotection,paging,or
multitaskingfeatures.
2.ProtectedMode:
○InProtectedMode,the80386canaccessupto4GBofmemoryand
supportsfeatureslikememoryprotection,virtualmemory,and
multitasking.Italsoprovidesmechanismsforhandlingerrorsand
exceptionsmoreefficiently.
3.Virtual8086Mode:
○Virtual8086Modeallowstheprocessortorun16-bitreal-mode
applications(writtenforthe8086or80286)withinaprotectedmode
environment,maintainingbackwardcompatibilitywhileallowing
memoryprotectionandmultitasking.
30JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application. CO2: Classify Processor
architectures.

31. AddressingModesandDataTypesinthe80386
31
Sr.
No.
Addressing Mode
Sr.
No.
Addressing Mode
1
Immediate Addressing
Mode
5Indexed Addressing Mode
2Register Addressing Mode6
Base-Register Plus
Displacement Addressing
3Direct Addressing Mode 7Relative Addressing Mode
4Indirect Addressing Mode8Segmented Addressing Mode
JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

32. AddressingModesandDataTypesinthe80386
32
Immediate
Addressing
Mode
01
Operandisdirectlyspecifiedinthe
instructionitself
(i.e.,theoperandisaconstantvalue).
●Syntax:MOV AX, 5
Here,5istheimmediatevalue
thatgetsloadedintoregister
AX.
●Example: MOV EAX, 0x1234
This instruction moves the
immediate value 0x1234into the
EAXregister.
JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

33. AddressingModesandDataTypesinthe80386
33
Register
Addressing
Mode
02
●Theoperandisstoredina
register.
●Thisisoneofthesimplest
modes,wherethesourceor
destinationoftheoperationisa
register.
●Syntax:MOV AX,BX
ThecontentsofregisterBXare
movedintoregisterAX.
●Example:ADDAX,BX
Thisaddsthecontentsof
registerBXtoAX.
JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

34. AddressingModesandDataTypesinthe80386
34
Direct
Addressing
Mode
03
●Thismodeinvolvesaccessing
amemorylocationdirectly
usinga16-bitor32-bit
address.
●Syntax:MOVAX,[1000h]
Thismovesthecontentsof
thememorylocation0x1000
intoregisterAX.
●Example:MOVAX,[EAX]
Thisaccessesthememoryat
theaddressstoredinEAX
andmovesthecontentsof
thatmemorylocationinto
AX.
JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application. CO2:
Classify Processor architectures.

35. AddressingModesandDataTypesinthe80386
35
Indirect
Addressing
Mode
04
●Theoperandisaccessedviaa
registerthatholdsamemory
address.
Theeffectiveaddressis
computedindirectlybythe
contentsofaregister.
●Syntax:MOVAX,[BX]
Theoperandislocatedatthe
memoryaddresscontainedin
theBXregister.
●Example:MOVAX,[EBX]
Thisinstructionmovesthe
contentsofthememory
locationpointedtobyEBX
intoAX.
JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

36. AddressingModesandDataTypesinthe80386
36
Indexed
Addressing
Mode
05
●Theeffectiveaddressis
calculatedbyaddinga
displacement(oroffset)toa
baseaddress.
●Syntax:MOVAX,[BX+SI]
Theeffectiveaddressisthesum
oftheBXregisterandtheSI
register.
●Example:MOVAX,[EAX+
ECX]
ThisinstructionaddsEAXand
ECXtocomputetheeffective
address,thenmovesthevalue
fromthatmemoryaddressinto
AX.
JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

37. AddressingModesandDataTypesinthe80386
37
Base-Register
Plus
Displacement
Addressing
06
●Thismodeisavariantof
indexedaddressing.
●Syntax:MOVAX,[BX+10]
Thiscalculatestheeffective
addressasthesumofBXand
thedisplacement10,andmoves
thecontentsofthataddressinto
AX.
●Example:MOVAX,[EBX+
0x04]
Thismovesthecontentsofthe
memoryataddressEBX+0x04
intoAX.
JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the
application. CO2: Classify Processor architectures.

38. AddressingModesandDataTypesinthe80386
38
Relative
Addressing
Mode
07
●Thismodeisusedfor
branchingorjumping
instructions.
●Syntax:JMPshortlabel
Here,labelisamemory
addresscomputedbyadding
thedisplacementtothe
currentinstructionpointer.
●Example:JMP [EAX]
Thisinstructionjumpstothe
addresscontainedintheEAX
register.
JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

39. AddressingModesandDataTypesinthe80386
39
Segmented
Addressing
Mode
08
●In80386,memoryisdivided
intosegments,andthe
segmentregisters(CS,DS,
SS,ES,FS,GS)determine
thebaseaddressforeach
segment.
●Theeffectiveaddressofan
operandiscomputedasthe
sumofthesegmentbaseand
theoffset(theactualaddress
withinthesegment).
●Syntax:MOVAX,[ES:BX]
Here,BXistheoffsetwithin
thesegment,andESisthe
segmentbase.
JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

40. Data Types in the 80386
Supports 16-bit and 8-bit data types for backward compatibility and for specific
types of operations.
1. Byte (8 bits)
●A byteis an 8-bit unit of data. It is the smallest addressable unit of memory
and is used for storing values such as characters or small integers.
●Example: MOV AL, [BX]
This moves a byte from the memory location pointed to by BXinto the AL
register.
2. Word (16 bits)
●A wordis a 16-bit unit of data. In the 80386, it is used to handle 16-bit
integers, pointers, or addresses.
●Example: MOV AX, [BX]
This moves a word (16 bits) from the memory location pointed to by BX
into the AXregister.
40JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

41. Data Types in the 80386
3. Double Word (32 bits)
●A double wordis a 32-bit unit of data. The 80386 primarily uses
32-bit dataand 32-bit registers, such as EAX, EBX, ECX, etc.
●Example: MOV EAX, [EBX]
This moves a double word (32 bits) from the memory location
pointed to by EBXinto the EAXregister.
4. Quad Word (64 bits) (Note: Not directly supported by the 80386
as the processor is 32-bit, but the 80386 can handle 64-bit operations
in future processors like x86-64)
●The 80386 itself doesn't directly support 64-bit data types, but in
newer processors (like the x86-64), 64-bit data types can be
processed.
41JANUARY 14, 2025
CO1: Exhibit skill of assembly language
programming for the application. CO2:
Classify Processor architectures.

42. Data Types in the 80386
5.PackedDataTypes(BCDandFloatingPoint):
●The80386alsosupportspackedbinary-codeddecimal
(BCD)andfloating-pointoperations,althoughtheseare
typicallyhandledbyacoprocessor(e.g.,the80387
floating-pointunit).
●BCDisusedforfinancialandbusinesscalculations,where
eachdigitisstoredinabyte.
●Floating-pointnumbersarerepresentedby32-bitor64-bit
valuesinIEEEformatforreal-numberarithmetic.
42JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

43. 43
MOV: Moves data from a source to a destination.Example:
MOV EAX, EBX
PUSH: Pushes data onto the stack. Example: PUSH AX
POP: Pops data from the stack into a register or
memory location.
Example: POP BX
XCHG: Exchanges the values of two operands.Example:XCHG AX,
BX
LEA(Load Effective Address): Loads the effective
address of a memory operand into a register.
Example:
LEA EAX, [EBX + 4]
MOVSB, MOVSW, MOVSD : Used for moving bytes, words, and double
words, respectively, in string operations.
ApplicationsInstructionSetoftheIntel80386
1.DataMovementInstructions
JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

44. 44
ADD:Addstwooperands. Example: ADD AX, BX
SUB:Subtractsthesecondoperandfromthefirst.Example:SUBEAX,EBX
MUL:Multipliestwooperands(unsigned). Example: MUL BX
IMUL:Multipliestwooperands(signed). Example:IMULAX,BX
DIV:Dividestheaccumulatorbytheoperand
(unsigned).
Example:DIVBX
IDIV:Dividestheaccumulatorbytheoperand
(signed).
Example:IDIVBX
INC:Incrementstheoperandby1. Example:INCAX
(Thisadds1toAX.)
2.BinaryArithmeticInstructions
JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

45. 45
DEC: Decrements the operand by 1.Example: DEC BX
This subtracts 1 from BX.
NEG: Negates the operand. Example: NEG AX
This changes the sign of the value
in AX.
CMP: Compares two operands by
subtracting them and setting flags
accordingly.
Example: CMP AX, BX
This subtracts BXfrom AXand
sets the flags based on the result.
ApplicationsInstructionSetoftheIntel80386
2.BinaryArithmeticInstructions
JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

46. 46
●AAA(ASCII Adjust AX After
Addition): Adjusts the value in the
AXregister after a BCD addition.
Example: AAA
This instruction adjusts AXafter adding
two packed BCD digits.
●AAM(ASCII Adjust AX on
Multiply): Adjusts the AXregister
after multiplication of BCD
numbers.
Example: AAM
This performs the necessary adjustments to
AXafter a BCD multiplication.
●AAD(ASCII Adjust AX on
Division): Adjusts AXfor BCD
division.
Example: AAD
This adjusts AXafter a division operation.
●AAS(ASCII Adjust AX for
Subtraction): Adjusts AXafter BCD
subtraction.
Example: AAS
This adjusts AXafter a BCD subtraction.
ApplicationsInstructionSetoftheIntel80386
3.DecimalArithmeticInstructions
JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

47. 47
AND: Performs a bitwise AND
operation between two operands.
Example: AND AX, BX
This performs a bitwise AND between AX
and BX.
OR: Performs a bitwise OR operation
between two operands.
Example: OR AX, BX
This performs a bitwise OR between AX
and BX.
XOR: Performs a bitwise XOR
operation between two operands.
Example: XOR AX, BX
This performs a bitwise XOR between AX
and BX.
NOT: Inverts the bits of the operand.Example: NOT AX
This performs a bitwise NOT on AX.
SHL / SAL(Shift Left): Shifts the
bits of the operand to the left.
Example: SHL AX, 1
This shifts the bits in AXone position to the
left (equivalent to multiplying by 2).
ApplicationsInstructionSetoftheIntel80386
4.LogicalInstructions
JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

48. 48
SHR(Shift Right):
Shifts the bits of the operand to the
right.
Example: SHR BX, 1
This shifts the bits in BXone position
to the right (equivalent to dividing by
2).
ROL(Rotate Left) and ROR
(Rotate Right):
These instructions rotate the bits of
the operand to the left or right.
Example: ROL AX, 1
This rotates the bits of AXone position
to the left.
ApplicationsInstructionSetoftheIntel80386
4.LogicalInstructions
JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

49. 5. Control Transfer Instructions
Control transfer instructions are used to alter the flow of execution in a
program. These instructions include jumps, calls, and returns.
●JMP: Jumps to a specified address (unconditional).
○Example: JMP label
This jumps to the address specified by label.
●JE / JZ: Jumps if the zero flag is set (i.e., if the previous
comparison was equal).
○Example: JE label
This jumps to labelif the zero flag is set.
49JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

50. 5.ControlTransferInstructions
●JNE / JNZ: Jumps if the zero flag is not set (i.e., if the previous
comparison was not equal).
○Example: JNE label
This jumps to labelif the zero flag is not set.
●CALL: Calls a procedure (pushes the return address to the stack).
○Example: CALL procedure
This calls the procedure at procedureand pushes the return
address onto the stack.
●RET: Returns from a procedure (pops the return address from the
stack).
○Example: RET
This pops the return address from the stack and jumps to that
address.
50JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

51. 5.ControlTransferInstructions
●INT: Triggers an interrupt.
○Example: INT 21h
This triggers interrupt 21h.
51JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

52. 6. String and Character Transfer Instructions
String instructions operate on sequences of data (strings) and typically
use registers such as SI(source index) and DI(destination index) for
indexing.
●MOVSB / MOVSW / MOVSD : Move bytes, words, or double
words between memory locations.
Example: MOVSB
This moves a byte from the memory location pointed to by SIto
the memory location pointed to by DI.
●CMPSB / CMPSW / CMPSD: Compare strings of bytes, words,
or double words.
○Example: CMPSB
This compares bytes in the strings at SIand DI.
52JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

53. 6.StringandCharacterTransferInstructions
●SCASB/SCASW/SCASD:Scanastringforaparticularvalue.
○Example: SCASB
This scans a byte at DIand compares it with the value in AL.
●LODSB / LODSW / LODSD: Load a byte, word, or double word
from the string into AL, AX, or EAX.
○Example: LODSB
This loads a byte from the memory location pointed to by SI
53JANUARY 14, 2025
CO1: Exhibit skill of assembly language programming for the application.
CO2: Classify Processor architectures.

54. THANK YOU
54
PREPAIRED BY
SWATI D. JADHAV
[email protected]
JANUARY 14, 2025
CO1: Exhibit skill of assembly language
programming for the application. CO2:
Classify Processor architectures.