Architecture of 8051

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1. Architecture of 8051

2. Block Diagram of 8051 CPU On-chip RAM On-chip ROM for program code 4 I/O Ports Timer 0 Serial Port OSC Interrupt Control External interrupts Timer 1 Timer/Counter Bus Control TxD RxD P0 P1 P2 P3 Address/Data Counter Inputs

3. Features 8 bit CPU 16-bit program counter(PC) and data pointer (DPTR) 8-bit program status word(PSW) 8-bit stack pointer 4 Kbytes of on-chip program memory(ROM) 128 bytes of on-chip data random access memory(RAM)

4. 64Kbytes of program memory address space 64Kbytes of data memory address space Two 16 bit timers/counters 16 bit address bus multiplexed with port 0 and port 2 32 bidirectional I/O lines can be either used as 8 bit ports On-chip clock oscillator Control Registers Serial data receiver/transmitter Interrupt sources

5. Architecture of 8051 Processor includes Arithmetic and logic unit Instruction decoder Timing generation unit Accumulator B register Status register

6. Arithmetic and Logic Unit Performing computing functions Accumulator is 8-bit register Arithmetic and logical operations – one of the operands is in A register Result is stored in only A C(carry), AC(auxiliary carry), O(overflow) and P(Parity) – status register

7. Instruction decoder and control When an instruction is fetched – it is loaded in the instruction register Decoder decodes the instruction and establishes the sequence of events to follow Instruction cycle: Instruction cycle is defined as the time required for completing the execution of an instruction

8. Instruction register is not programmable It cannot be accessed through any instruction Control unit generates control signals necessary for communication between the processor and peripherals

9. CPU Registers A Register(E0H) 8 bit Direct connection with ALU In multiplication- one of 8 bit operands stored in A and after operation it stores lower byte in A In division- holds 8 bit dividend & quotient is stored in A B Register(F0H) 8 bit Used with multiply and divide operations In multiplication- after operation it stores higher byte in B In division- holds 8 bit divisor & reminder is stored in B

10. Registers A B R0 R1 R3 R4 R2 R5 R7 R6 DPH DPL PC DPTR PC Some 8051 16-bit Register Some 8-bitt Registers of the 8051

11. Program status word(D0H) CY AC F0 RS1 RS0 OV -- P CY—PSW.7 Carry flag AC – PSW.6 Auxiliary carry F0– PSW.5 General purpose RS1-PSW.4 Register bank selector bit 1 RS0-PSW.3 Register bank selector bit 0 OV-PSW.2 Overflow flag -- User defined bit P—PSW.0 Parity flag

12. Stack Pointer(81H) 8 BIT Contains data item on the top of stack Incremented before data is stored Initialized to 07H

13. Data Pointer DPTR (Data Pointer) consists of two 8 bit registers – high byte (DPH) and low byte (DPL) 16 bit address To furnish address information for internal and external program memory and for external data memory

14. Program Counter 16 bit register Specifies the address of next instruction to be executed After reset – PC will be set to 0000H 8051 fetches the instruction one byte at a time After increments, it increments PC by 1

15. MEMORY 4k bytes on chip ROM 128 bytes RAM Program memory is used to hold start up program Data random access memory is divided into 4 parts: First 128 bytes : 00H TO 1FH (31) – Register Banks 20H TO 2FH(47) – Bit addressable RAM 30H TO 7FH (127) – General purpose registers Next 128 bytes : 80H TO FFH (255) – Special function registers

16. Register Banks Lowest 32 bytes 4 banks – each having 8 registers RS1 and RS0 (4 TH BIT AND 3 RD BIT) program status word select the bank Each bank contains R0 TO R7 Ex: add A,R2 – adds the value contained in R2 to the accumulator RS1=0 and RS0=0 – BANK 0 IS SELECTED R2 is which memory location? ADD A,02H

17. Internal RAM Organization Special function registers 80 –FF General purpose registers 30-7F Bit addressable space 20-2F BANK 3 (R0-R7) 18-1F BANK 2 (R0-R7) 10-17 BANK 1 (R0-R7) 08-0F BANK 0 (R0-R7) 00-07

18. PSW bits bank selection RS1 – PSW.4 RS0- PSW.3 BANK 0 BANK 1 1 BANK 2 1 Bank 3 1 1