Basics of vlsi
ManishJoshi123
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May 04, 2016
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About This Presentation
VLSI stands for Very Large Scale integration is the art of integrating millions of transistors on a Silicon Chip. Researchers are working to incorporate large scale integration of electronic devices on a single silica chip “Integrated Circuit or IC” to fulfill the market demand. Here, in this pr...
Slide Content
www.ScientechWorld.com
V L S I
WELCOME
Lavesh Kumath
Head, R & D (VLSI Division )
Scientech Technologies Pvt. Ltd., Indore
[email protected]
V L S I
WELCOME
Lavesh Kumath
Head, R & D (VLSI Division )
Scientech Technologies Pvt. Ltd., Indore
[email protected]
www.ScientechWorld.com
THE ART OF VLSIBasics of VLSI
THE ART OF VLSIBasics of VLSI
www.ScientechWorld.com
Semi conductor
Diodes
Transistors
FET
JFET
N Chan P Chan
BJT – TTL,RTL, ECL
MOSFET
N MOS P MOS CMOS
Gates
ICs
endless Journey……
Power
Area Speed
Density
Functionality Features
SSI MSI LSI VLSI
Gates
ICs
SSI
MSI LSI
DTL
Semi conductor
Diodes
Transistors
FET
JFET
N Chan P Chan
BJT – TTL,RTL, ECL
MOSFET
N MOS P MOS CMOS
Gates
ICs
endless Journey……
Power
Area Speed
Density
Functionality Features
SSI MSI LSI VLSI
Gates
ICs
SSI
MSI LSI
DTL
www.ScientechWorld.com
TTL Logic
Design Specification
Truth Table
Boolean Expression
Available
Inventory
Cost and
performance
requirement
Logic minimization
and multilevel
logic optimization
Implementation
General Design Flow….
TTL Logic
Design Specification
Truth Table
Boolean Expression
Available
Inventory
Cost and
performance
requirement
Logic minimization
and multilevel
logic optimization
Implementation
General Design Flow….
www.ScientechWorld.com
Digital Design Process
A B C D X
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
Logic
2 or >2 I/P = 1 then O/P 1
1. Design Specifications
2. Truth Table
0 0 1 0
0 1 1 1
1 1 1 1
0 1 1 1
/CD 00 01 11 10AB
00
01
11
10
Boolean Eq. -> X = AB + CD + BD + BC + AD + AC OR X’ = A’B’C’ + A’B’D’ + A’C’D’ + B’C’D’
3. Reduce
Expression
A
B
C
D
O/P = X
Digital Design Process
A B C D X
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
Logic
2 or >2 I/P = 1 then O/P 1
1. Design Specifications
2. Truth Table
0 0 1 0
0 1 1 1
1 1 1 1
0 1 1 1
/CD 00 01 11 10AB
00
01
11
10
Boolean Eq. -> X = AB + CD + BD + BC + AD + AC OR X’ = A’B’C’ + A’B’D’ + A’C’D’ + B’C’D’
3. Reduce
Expression
A
B
C
D
O/P = X
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Digital Design Process
1. Design Specifications
2. Truth Table
3. Reduction using Boolean
or K Map
Boolean Eq. -> X = AB + CD + BD + BC + AD + AC --> 2 - 7408, 3 - 7432, 3 level of logic
1 - 7474 for synchronization
4. Minimize of Device or No. of Level i.e. Cost Vs Performance (Min Prop. Delay)
5. Examine Available Inventory
6. Eqn Re-written in NAND-
NAND implementation
Few Device and Few logic i.e. Less Cost and Better Performance
Boolean Eq. -> X = {(AB)’. (CD)’ . (BD)’ .(BC)’. (AD)’ .(AC)’ }’ --> 2 - 7400, 1 - 7430, 2 level of logic
1 - 7474 for
synchronization 1
2
Digital Design Process
1. Design Specifications
2. Truth Table
3. Reduction using Boolean
or K Map
Boolean Eq. -> X = AB + CD + BD + BC + AD + AC --> 2 - 7408, 3 - 7432, 3 level of logic
1 - 7474 for synchronization
4. Minimize of Device or No. of Level i.e. Cost Vs Performance (Min Prop. Delay)
5. Examine Available Inventory
6. Eqn Re-written in NAND-
NAND implementation
Few Device and Few logic i.e. Less Cost and Better Performance
Boolean Eq. -> X = {(AB)’. (CD)’ . (BD)’ .(BC)’. (AD)’ .(AC)’ }’ --> 2 - 7400, 1 - 7430, 2 level of logic
1 - 7474 for
synchronization 1
2
www.ScientechWorld.com
Basics of VLSI ………..
•VLSI Introduction
•History of VLSI.
•Why VLSI …. ?
•VLSI Design Styles
•VLSI Design Flows
•VLSI Design Approaches
•Xilinx Vs Altera
Basics of VLSI ………..
•VLSI Introduction
•History of VLSI.
•Why VLSI …. ?
•VLSI Design Styles
•VLSI Design Flows
•VLSI Design Approaches
•Xilinx Vs Altera
www.ScientechWorld.com
VERY LARGE SCALE INTEGRATION
“ Is the art of integrating millions of transistors on a Silicon Chip ”
VERY LARGE SCALE INTEGRATION
“ Is the art of integrating millions of transistors on a Silicon Chip ”
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“ A device called a transistor, which has several applications
In radio where a vacuum tube ordinarily is employed, was
demonstrated for the first time at Bell Telephone
Laboratories, 463 West Street, where it was invented.”
23 December 1947
The First Transistor
First point contact transistor (germanium), 1947
John Bardeen and Walter Brattain
Bell Laboratories
History of IC Design
“ A device called a transistor, which has several applications
In radio where a vacuum tube ordinarily is employed, was
demonstrated for the first time at Bell Telephone
Laboratories, 463 West Street, where it was invented.”
23 December 1947
The First Transistor
First point contact transistor (germanium), 1947
John Bardeen and Walter Brattain
Bell Laboratories
History of IC Design
www.ScientechWorld.com
- Evolution of ICs -
Vacuum tubes
Transistors
Gates
ICs
?
High Performance
High Reliability
High complexity or small Area
High applicability
Low Power Dissipation
Low power consumption
Low Cost
Fast Design time
Simple Design Process
Integrated Circuits
IC is a collection of Electronic Circuits made by simultaneously forming individual
Transistors, Diodes and Resistors on a small chip of Semiconductor material, typically
silicon that are interconnected to one another with a metal, such as aluminum, deposited
on the chip surface.
- Evolution of ICs -
Vacuum tubes
Transistors
Gates
ICs
?
High Performance
High Reliability
High complexity or small Area
High applicability
Low Power Dissipation
Low power consumption
Low Cost
Fast Design time
Simple Design Process
Integrated Circuits
IC is a collection of Electronic Circuits made by simultaneously forming individual
Transistors, Diodes and Resistors on a small chip of Semiconductor material, typically
silicon that are interconnected to one another with a metal, such as aluminum, deposited
on the chip surface.
www.ScientechWorld.com
The Progressive Trend of IC Technology
Integration Level Number of TransistorsYear
SSI - Individual Gates
MSI - Counter, Shift Reg.
LSI - Small Logic Function
VLSI - Large Logic Function
1950s
1960s
1970s
1980s
1990s
2000s
Less than 10^2
10^2 – 10^3
10^3 – 10^5
10^5 – 10^7
10^7 – 10^9
Over 10^9
The Progressive Trend of IC Technology
Integration Level Number of TransistorsYear
SSI - Individual Gates
MSI - Counter, Shift Reg.
LSI - Small Logic Function
VLSI - Large Logic Function
1950s
1960s
1970s
1980s
1990s
2000s
Less than 10^2
10^2 – 10^3
10^3 – 10^5
10^5 – 10^7
10^7 – 10^9
Over 10^9
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Evolution in IC Complexity
Evolution in IC Complexity
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Moore’s Law
http://www.intel.com/technology/silicon/mooreslaw/
In 1965, Intel co-founder
Gordon Moore
saw the future.
His prediction, now popularly
known as Moore's Law,
states that
“The number of transistors on a
chip doubles about every two
years”
Transistor Count – Number of Transistor doubles every 2-3 Yrs
Clock Frequency – Clock Frequency doubles every 2.168 Yrs
Other Trends -
Features Size – Gate Length is divided by 2 every 5.43 Yrs
Moore’s Law
http://www.intel.com/technology/silicon/mooreslaw/
In 1965, Intel co-founder
Gordon Moore
saw the future.
His prediction, now popularly
known as Moore's Law,
states that
“The number of transistors on a
chip doubles about every two
years”
Transistor Count – Number of Transistor doubles every 2-3 Yrs
Clock Frequency – Clock Frequency doubles every 2.168 Yrs
Other Trends -
Features Size – Gate Length is divided by 2 every 5.43 Yrs
www.ScientechWorld.com
VLSI Technology - CMOS Transistors
Key feature:
transistor length L
p+ p+
n substrate
channel
Source
Drain
p transistor
G
S
D
SB
Polysilicon Gate
SiO2
Insulator
L
W
G
substrate connected
to VDD
Polysilicon Gate
SiO2
Insulator
n+ n+
p substrate
channel
Source Drain
n transistor
G
S
D
SB
L
W
G
S
D
substrate connected
to GND
2002: L=130nm
2003: L=90nm
2006: L=65nm
VLSI Technology - CMOS Transistors
Key feature:
transistor length L
p+ p+
n substrate
channel
Source
Drain
p transistor
G
S
D
SB
Polysilicon Gate
SiO2
Insulator
L
W
G
substrate connected
to VDD
Polysilicon Gate
SiO2
Insulator
n+ n+
p substrate
channel
Source Drain
n transistor
G
S
D
SB
L
W
G
S
D
substrate connected
to GND
2002: L=130nm
2003: L=90nm
2006: L=65nm
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2002 and beyond ?
Semiconductor Industry Association (SIA) Road Map, 1998 Update
1999 2002 2014
Technology (nm) 180 130 35
Wafer diameter (mm) 300 300 450
Memory-samples(bits) 1G 4G 1T
Transistors/cm
2
(mP) 6.2M 18M 390M
Wiring levels (maximum) 6-7 7 10
Clock, local (MHz) 1250 2100 10000
Chip size: DRAM (mm
2
) 400 560 2240
Chip size: mP (mm
2
) 340 430 901
Power supply (V) 1.5-1.81.2-1.50.37-0.42
Maximum Power (W) 90 130 183
Number of pins (mP) 700 957 3350
IEEE Spectrum, July
1999
Special report: “The
100-million transistor
IC”
These scaling trends will allow the electronics market to growth at 15% / year
2002 and beyond ?
Semiconductor Industry Association (SIA) Road Map, 1998 Update
1999 2002 2014
Technology (nm) 180 130 35
Wafer diameter (mm) 300 300 450
Memory-samples(bits) 1G 4G 1T
Transistors/cm
2
(mP) 6.2M 18M 390M
Wiring levels (maximum) 6-7 7 10
Clock, local (MHz) 1250 2100 10000
Chip size: DRAM (mm
2
) 400 560 2240
Chip size: mP (mm
2
) 340 430 901
Power supply (V) 1.5-1.81.2-1.50.37-0.42
Maximum Power (W) 90 130 183
Number of pins (mP) 700 957 3350
IEEE Spectrum, July
1999
Special report: “The
100-million transistor
IC”
These scaling trends will allow the electronics market to growth at 15% / year
www.ScientechWorld.com
Power & Clock Frequencies
Power Consumption, Clock frequency, Supply Voltage are related as follows :-
Capacitance Supply Voltage Clock Frequency
Power & Clock Frequencies
Power Consumption, Clock frequency, Supply Voltage are related as follows :-
Capacitance Supply Voltage Clock Frequency
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Why VLSI Design ?
• Large Scale Integration -
Size ….. <<<
Speed …. >>>
Power …. <<<
• Integration reduce manufacturing costs
(almost) no manual assembly
• Money Vs Performance
Why VLSI Design ?
• Large Scale Integration -
Size ….. <<<
Speed …. >>>
Power …. <<<
• Integration reduce manufacturing costs
(almost) no manual assembly
• Money Vs Performance
www.ScientechWorld.com
VLSI Design Styles
Integrated Circuits
Full-Custom
ASICs
Semi-Custom
ASICs
User
Programmable
PLD FPGA
SPLDPLAPAL
LUT
(Look-Up Table)
MUXGates
System-On
CHIP
CPLD
1 2 3 4
VLSI Design Styles
Integrated Circuits
Full-Custom
ASICs
Semi-Custom
ASICs
User
Programmable
PLD FPGA
SPLDPLAPAL
LUT
(Look-Up Table)
MUXGates
System-On
CHIP
CPLD
1 2 3 4
www.ScientechWorld.com
VLSI Design Styles
1.Programmable Logic (PLD, FPGA)
2.Application-Specific Integrated Circuit (ASIC)
3.Full Custom
4.System-on-Chip
VLSI Design Styles
1.Programmable Logic (PLD, FPGA)
2.Application-Specific Integrated Circuit (ASIC)
3.Full Custom
4.System-on-Chip
www.ScientechWorld.com
VLSI Design Styles
Integrated Circuits
Full-Custom
ASICs
Semi-Custom
ASICs
User
Programmable
FPGA
LUT
(Look-Up Table)
MUXGates
System-On
CHIP
PLD
SPLDPLAPAL CPLD
1
2 3
4
VLSI Design Styles
Integrated Circuits
Full-Custom
ASICs
Semi-Custom
ASICs
User
Programmable
FPGA
LUT
(Look-Up Table)
MUXGates
System-On
CHIP
PLD
SPLDPLAPAL CPLD
1
2 3
4
www.ScientechWorld.com
1. Programmable Logic (PLDs, FPGAs)
•Pre-manufactured components with programmable interconnect
•CAD tools greatly reduce design effort
•Low Design Cost
•Low NRE Cost
•High Unit Cost
•Lower Performance as compared to ASIC better than General digital design
1. Programmable Logic (PLDs, FPGAs)
•Pre-manufactured components with programmable interconnect
•CAD tools greatly reduce design effort
•Low Design Cost
•Low NRE Cost
•High Unit Cost
•Lower Performance as compared to ASIC better than General digital design
www.ScientechWorld.com
Logic Circuits
Standard Logic Circuits Programmable Logic Circuits
•Realize single function or set of
functions
•No possibility of changing.
•More Debugging Time
•More Interconnections and I/Os
•High Standby and Switching current
•No Design Security
•Not Flexible
•No Tools for Automation
•More NRE & Time to Market
Single Change require – redesign
•Possibility of realizing various
functions
•Re-configurable
•Less Debugging Time
•Fewer total I/Os & Switching O/P-
•Lower Standby & Switching Currents
•Design Security
•Flexibility …….. Greatest Advantage
•Automation is Possible
•Less NRE & Less Time to market
only reprogramming is required
……
FPLD
Logic Circuits
Standard Logic Circuits Programmable Logic Circuits
•Realize single function or set of
functions
•No possibility of changing.
•More Debugging Time
•More Interconnections and I/Os
•High Standby and Switching current
•No Design Security
•Not Flexible
•No Tools for Automation
•More NRE & Time to Market
Single Change require – redesign
•Possibility of realizing various
functions
•Re-configurable
•Less Debugging Time
•Fewer total I/Os & Switching O/P-
•Lower Standby & Switching Currents
•Design Security
•Flexibility …….. Greatest Advantage
•Automation is Possible
•Less NRE & Less Time to market
only reprogramming is required
……
FPLD
www.ScientechWorld.com
• PLA - Programmable Logic Arrays
• PAL - Programmable Array Logic
• CPLD - Complex Programmable Logic Devices
• FPGA - Field Programmable Gate Arrays
PLD
FPLD Representatives
• PLA - Programmable Logic Arrays
• PAL - Programmable Array Logic
• CPLD - Complex Programmable Logic Devices
• FPGA - Field Programmable Gate Arrays
PLD
FPLD Representatives
www.ScientechWorld.com
What is a CPLD ?
Complex Programmable Logic Devices (CPLD) are another way to extend
the density of the simple PLD.
CPLD uses less board space, improve reliability, and reduce cost.
CPLD contains multiple logic block, which communicate with one another
using Signals routed via a programmable interconnect.
Easily Routed.
CPLDs are great at handling wide and complex gating at blistering
speeds
e.g. 5ns which is equivalent to 200MHz.
What is a CPLD ?
Complex Programmable Logic Devices (CPLD) are another way to extend
the density of the simple PLD.
CPLD uses less board space, improve reliability, and reduce cost.
CPLD contains multiple logic block, which communicate with one another
using Signals routed via a programmable interconnect.
Easily Routed.
CPLDs are great at handling wide and complex gating at blistering
speeds
e.g. 5ns which is equivalent to 200MHz.
www.ScientechWorld.com
CPLD Architecture
CPLD Architecture
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CPLD Architecture
Complex Programmable Logic Devices
CPLD Architecture
Complex Programmable Logic Devices
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Why use a CPLD ?
Ease of Design
Lower Development Costs
More Product Revenue
Reduced Board Area
Reconfigurable
Flexible
Why use a CPLD ?
Ease of Design
Lower Development Costs
More Product Revenue
Reduced Board Area
Reconfigurable
Flexible
www.ScientechWorld.com
Evolution of PLD: FPGA
•Difficult extending CPLDs architectures to higher densities
-
a different approach is needed
•FPGAs comprise an array of uncommited circuit elements,
called logic blocks, and interconnect resources
•FPGA configuration is performed through
programming by the end user.
Xilinx FPGA Configuration
contains a set of
basic functions
(gates, FFs,
memory cells)
Evolution of PLD: FPGA
•Difficult extending CPLDs architectures to higher densities
-
a different approach is needed
•FPGAs comprise an array of uncommited circuit elements,
called logic blocks, and interconnect resources
•FPGA configuration is performed through
programming by the end user.
Xilinx FPGA Configuration
contains a set of
basic functions
(gates, FFs,
memory cells)
www.ScientechWorld.com
29
General FPGA Architecture
•Field Programmable Gate Array
29
General FPGA Architecture
•Field Programmable Gate Array
www.ScientechWorld.com
FPGAs -- Pros
•Reasonably Cheap at low volume
–Good for low-volume parts, more expensive than IC for high-volume parts
–Can migrate from SRAM based to fuse based when volume ramps up
•Short Design Cycle (~1sec programming time)
•Reprogrammable
–Can download bug fix into units you’ve already shipped
•Large capacity (100 million gates or so .….
•More flexible than PLDs -- can have internal state
•More compact than MSI/SSI
FPGAs -- Pros
•Reasonably Cheap at low volume
–Good for low-volume parts, more expensive than IC for high-volume parts
–Can migrate from SRAM based to fuse based when volume ramps up
•Short Design Cycle (~1sec programming time)
•Reprogrammable
–Can download bug fix into units you’ve already shipped
•Large capacity (100 million gates or so .….
•More flexible than PLDs -- can have internal state
•More compact than MSI/SSI
www.ScientechWorld.com
FPGA’s -- Cons
•Lower capacity, speed and higher power consumption than building an ASIC
–Sub-optimal mapping of logic into CLB’s – often 60% utilization
–Much lower clock frequency
–Less dense layout and placement and slower operation due to
programmability
•Overhead of configurable interconnect and logic blocks
•PLDs may be faster than FPGA for designs they can handle
•Need sophisticated tools to map design to FPGA
FPGA’s -- Cons
•Lower capacity, speed and higher power consumption than building an ASIC
–Sub-optimal mapping of logic into CLB’s – often 60% utilization
–Much lower clock frequency
–Less dense layout and placement and slower operation due to
programmability
•Overhead of configurable interconnect and logic blocks
•PLDs may be faster than FPGA for designs they can handle
•Need sophisticated tools to map design to FPGA
www.ScientechWorld.com
Key Factors For Comparing FPGAs
• Logic density
• Clock management
• On-chip memory
• DSP capabilities
• I/O compatibility
• Software support & other design services
Key Factors For Comparing FPGAs
• Logic density
• Clock management
• On-chip memory
• DSP capabilities
• I/O compatibility
• Software support & other design services
www.ScientechWorld.com
Programmable Logic (PLDs, FPGAs)
•Pre-manufactured components with programmable interconnect
•CAD tools greatly reduce design effort
•Low Design Cost / Low NRE Cost / High Unit Cost
•Lower Performance
Medium Type Design, Combinational CLB – LUT, MUX, FF, I/Os, PI, DLL, Sequential
Programmable Logic (PLDs, FPGAs)
•Pre-manufactured components with programmable interconnect
•CAD tools greatly reduce design effort
•Low Design Cost / Low NRE Cost / High Unit Cost
•Lower Performance
Medium Type Design, Combinational CLB – LUT, MUX, FF, I/Os, PI, DLL, Sequential
www.ScientechWorld.com
ADVANTAGES OF PROGRAMMABLE LOGICS
•Save Valuable Board Space
•Power Requirement is low
•Increases Performance
•Design Security
•Lower Standby and Switching Current
•Integration increases Design Reliability
•I/Os Delay Reduces
•Flexibility
•No NRC Cost
•Low Time to market
•Process Automation
•High Density ……… or Complex Design
ADVANTAGES OF PROGRAMMABLE LOGICS
•Save Valuable Board Space
•Power Requirement is low
•Increases Performance
•Design Security
•Lower Standby and Switching Current
•Integration increases Design Reliability
•I/Os Delay Reduces
•Flexibility
•No NRC Cost
•Low Time to market
•Process Automation
•High Density ……… or Complex Design
www.ScientechWorld.com
How to Cope with Complexity ?
Electronic Design Automation (EDA)
• Computer Aided Design (CAD) …. Front - end
• Computer Aided Engineering (CAE) …. Back - end
Simulation –
H-Spice (Synopsis), Spector (Cadance), Spector RF, H-Sim (Synopsis for Digital), DA
(Design Architect Mentor), Co-Sim (Synopsis for Mixed), FineSim SPICE, Fine Wave (Megma)
Synthesis & Implementation - DC
(Synopsis), ISE (Xilinx), Quartus (Altera), Blast – Integrated RTL-to-GDSII Flow (Megma)
Timing Analysis & Verification –
Prime Time, Formality – (Synopsis), DRC & LVS (Magma), Modelsim – Mentor,
Physical Design – Astro, Layout – Vertuoso (Cadance), Magic, L-Edit
How to Cope with Complexity ?
Electronic Design Automation (EDA)
• Computer Aided Design (CAD) …. Front - end
• Computer Aided Engineering (CAE) …. Back - end
Simulation –
H-Spice (Synopsis), Spector (Cadance), Spector RF, H-Sim (Synopsis for Digital), DA
(Design Architect Mentor), Co-Sim (Synopsis for Mixed), FineSim SPICE, Fine Wave (Megma)
Synthesis & Implementation - DC
(Synopsis), ISE (Xilinx), Quartus (Altera), Blast – Integrated RTL-to-GDSII Flow (Megma)
Timing Analysis & Verification –
Prime Time, Formality – (Synopsis), DRC & LVS (Magma), Modelsim – Mentor,
Physical Design – Astro, Layout – Vertuoso (Cadance), Magic, L-Edit
www.ScientechWorld.com
Design Entry
Synthesis
Implementation
Bit Stream
Configurable
Logic
Configurable
Switch Matrix
Configuration
Memory
Software PLD Chip
Volatile
Non-volatile
Transistor
Switch Muxes
LUT’s or Gates
Flip-flop
User Constraint file
Gate Level circuit
Device Type,
Constraints
Floor Planning
Device type ,
Constraint
VHDL or Verilog code
Device independent
Download cable
General Tool Flow for PLDs
Design Entry
Synthesis
Implementation
Bit Stream
Configurable
Logic
Configurable
Switch Matrix
Configuration
Memory
Software PLD Chip
Volatile
Non-volatile
Transistor
Switch Muxes
LUT’s or Gates
Flip-flop
User Constraint file
Gate Level circuit
Device Type,
Constraints
Floor Planning
Device type ,
Constraint
VHDL or Verilog code
Device independent
Download cable
General Tool Flow for PLDs
www.ScientechWorld.com
VLSI Design Styles
Integrated Circuits
Full-Custom
ASICs
Semi-Custom
ASICs
User
Programmable
PLDFPGA
SPLDPLAPAL
LUT
(Look-Up Table)
MUXGates
System-On
CHIP
CPLD
1 2 3
4
VLSI Design Styles
Integrated Circuits
Full-Custom
ASICs
Semi-Custom
ASICs
User
Programmable
PLDFPGA
SPLDPLAPAL
LUT
(Look-Up Table)
MUXGates
System-On
CHIP
CPLD
1 2 3
4
www.ScientechWorld.com
2. Application-Specific Integrated Circuit (ASIC)
•Constrained design using pre-designed (and sometimes pre-
manufactured) components
•Also called semi-custom design
•CAD tools greatly reduce design effort
•Low Design Cost / High NRE Cost / Med. Unit Cost
•Medium Performance
2. Application-Specific Integrated Circuit (ASIC)
•Constrained design using pre-designed (and sometimes pre-
manufactured) components
•Also called semi-custom design
•CAD tools greatly reduce design effort
•Low Design Cost / High NRE Cost / Med. Unit Cost
•Medium Performance
www.ScientechWorld.com
• Designs must be sent
for expensive and time
consuming fabrication
in semiconductor foundry
• Bought off the shelf
and reconfigured by
designers themselves
Two competing implementation approaches
ASIC
Application Specific
Integrated Circuit
FPGA
Field Programmable
Gate Array
• Designed all the way
from behavioral description
to physical layout
• No physical layout design;
design ends with
a bitstream used
to configure a device
• Designs must be sent
for expensive and time
consuming fabrication
in semiconductor foundry
• Bought off the shelf
and reconfigured by
designers themselves
Two competing implementation approaches
ASIC
Application Specific
Integrated Circuit
FPGA
Field Programmable
Gate Array
• Designed all the way
from behavioral description
to physical layout
• No physical layout design;
design ends with
a bitstream used
to configure a device
www.ScientechWorld.com
Balance ……….
FPGAs
Off-the-shelf
Low development cost
Short time to market
Re-configurability
High performance
ASICs
Low power
Low cost in
high volumes
Balance ……….
FPGAs
Off-the-shelf
Low development cost
Short time to market
Re-configurability
High performance
ASICs
Low power
Low cost in
high volumes
www.ScientechWorld.com
ASICASIC == AApplicationpplication SSpecificpecific IIntegratedntegrated CCircuitsircuits
tailor-made on demand for specific applicationstailor-made on demand for specific applications
FPGAFPGA == FFieldield PProgrammablerogrammable GGateate AArrayrray
flexibility of software + speed of hardware designflexibility of software + speed of hardware design
Which way to Go
ASICASIC == AApplicationpplication SSpecificpecific IIntegratedntegrated CCircuitsircuits
tailor-made on demand for specific applicationstailor-made on demand for specific applications
FPGAFPGA == FFieldield PProgrammablerogrammable GGateate AArrayrray
flexibility of software + speed of hardware designflexibility of software + speed of hardware design
Which way to Go
www.ScientechWorld.com
3. Full Custom Design
•Each circuit element carefully “handcrafted”
•NO use of any Library.
•Huge design effort.
•High Design & NRE Costs
•High Performance
•Typically used for high-volume applications
•Design Productivity is Very Low
3. Full Custom Design
•Each circuit element carefully “handcrafted”
•NO use of any Library.
•Huge design effort.
•High Design & NRE Costs
•High Performance
•Typically used for high-volume applications
•Design Productivity is Very Low
www.ScientechWorld.com
4. System-on-a-chip (SOC)
•Idea: combine several large
blocks
–Predesigned custom cores
(e.g., microcontroller) -
“intellectual property” (IP)
–ASIC logic for special-purpose
hardware
–Programmable Logic (PLD,
FPGA)
–Analog
•Open issues
–Keeping design cost low
–Verifying correctness of
design
4. System-on-a-chip (SOC)
•Idea: combine several large
blocks
–Predesigned custom cores
(e.g., microcontroller) -
“intellectual property” (IP)
–ASIC logic for special-purpose
hardware
–Programmable Logic (PLD,
FPGA)
–Analog
•Open issues
–Keeping design cost low
–Verifying correctness of
design
www.ScientechWorld.com
VLSI Design Flow & Tools
VLSI Design Flow & Tools
www.ScientechWorld.com
Front-end & Back-end
Front-end
Back-end
• Logic design (RTL)
• Simulation
• Synthesis
• Implementation
• Floorplanning
• Placement
• Routing
• GDSII (final Output, Foundary)
Verification
Front-end & Back-end
Front-end
Back-end
• Logic design (RTL)
• Simulation
• Synthesis
• Implementation
• Floorplanning
• Placement
• Routing
• GDSII (final Output, Foundary)
Verification
www.ScientechWorld.com
•Microelectronic system
•ASICs
•System partitioning
•ASIC floorplanning
•Placement
•Routing
•A City
•Buildings
•City planner
•Architect
•Builder
•Electrician
Physical design vs. Building a City
•Microelectronic system
•ASICs
•System partitioning
•ASIC floorplanning
•Placement
•Routing
•A City
•Buildings
•City planner
•Architect
•Builder
•Electrician
Physical design vs. Building a City
www.ScientechWorld.com
Programmable Logic Vendors
Xilinx - Xilinx Foundation Series.
Altera - Max Plus – II
Lattice - ISP Expert Compiler
Actel - Actel’s Designer Series FPGA Development System
Lucent - ORCA Foundry Development System
Cypress - Warp2
Atmel - FPGA Integrated Development System ( IDS )
QuickLogic- QuickWorks
Gatefield - ASIC master
Programmable Logic Vendors
Xilinx - Xilinx Foundation Series.
Altera - Max Plus – II
Lattice - ISP Expert Compiler
Actel - Actel’s Designer Series FPGA Development System
Lucent - ORCA Foundry Development System
Cypress - Warp2
Atmel - FPGA Integrated Development System ( IDS )
QuickLogic- QuickWorks
Gatefield - ASIC master
www.ScientechWorld.com
XILINX Vs ALTRA
Design Flow, Tools and Files
•Key players: Xilinx, Altera, Lattice, Actel
•PLD market estimated at $57 billion and rapidly growing
•The goal is to expand the market:
–by lowering per-unit cost to attack the low-end market
–by increasing speed capabilities to attack the high-end market
PLD market sharePLD market share
XILINX Vs ALTRA
Design Flow, Tools and Files
•Key players: Xilinx, Altera, Lattice, Actel
•PLD market estimated at $57 billion and rapidly growing
•The goal is to expand the market:
–by lowering per-unit cost to attack the low-end market
–by increasing speed capabilities to attack the high-end market
PLD market sharePLD market share
www.ScientechWorld.com
• Virtex and Stratix families are direct opponents, as are Spartan and CycloneVirtex and Stratix families are direct opponents, as are Spartan and Cyclone
XILINX Vs ALETRA
Altera Xilinx
Cyclone Spartan
Stratix Virtex
Stratix Kintex
Max10 Artix
• Virtex and Stratix families are direct opponents, as are Spartan and CycloneVirtex and Stratix families are direct opponents, as are Spartan and Cyclone
XILINX Vs ALETRA
Altera Xilinx
Cyclone Spartan
Stratix Virtex
Stratix Kintex
Max10 Artix
www.ScientechWorld.com
FPGA Design Flow – Xilinx - ISE
Design Entry
Design
Synthesis
Design
Implementation
Download to
Device
Functional
Simulation
Static Timing
Analysis
Timing
Simulation
In Circuit
Verification
Design Verification
*Translate
*Mapping
*P & R
*Fitting
*Bit stream
Generation
•Schematic editor
•HDL (.v or .vhd)
Text – (EDIF, XNF)
XST + GUI = NGC
UCF
Net list + Constraints
= NGD
NCD – Native Circuit
Description
VM6 -------- CPLD
.BIT or .JED
Library
FPGA Design Flow – Xilinx - ISE
Design Entry
Design
Synthesis
Design
Implementation
Download to
Device
Functional
Simulation
Static Timing
Analysis
Timing
Simulation
In Circuit
Verification
Design Verification
*Translate
*Mapping
*P & R
*Fitting
*Bit stream
Generation
•Schematic editor
•HDL (.v or .vhd)
Text – (EDIF, XNF)
XST + GUI = NGC
UCF
Net list + Constraints
= NGD
NCD – Native Circuit
Description
VM6 -------- CPLD
.BIT or .JED
Library
www.ScientechWorld.com
Xilinx Devices at a Glance
FPGAs
CPLDs
Vertex
Spartan
Cool
Runner
XC9500
XC9500, 5V, 36 to 288 Macrocells
Low Cost
XC9500XL, 3.3V, 36 to 288 Macrocells
XC9500XV, 2.5V, 36 to 288 Macrocells
XCR3000XL, 3.3V, 36 to 512 Macrocells
XC2Cxxx, 1.8V, 32 to 512 Macrocells
Low Power, High
Speed, Low Cost
Spartan, 5V, 5000 to 40000 Max System Gates
Spartan II E, 1.8V, 50000 to 300000 Max System Gates
Vertex, 2.5V, 50000 to 1 Mil. Max System Gates
VertexII, 1.5V, 40000 to 10 Mil. Max System Gates
VertexE, 1.8V, 50000 to 3.2 Mil. Max System Gates
Spartan II , 2.5V, 15000 to 200000 Max System Gates
Spartan XL, 3.3V, 5000 to 40000 Max System GatesLow Cost
Feature Rich, High
Density
Xilinx Devices at a Glance
FPGAs
CPLDs
Vertex
Spartan
Cool
Runner
XC9500
XC9500, 5V, 36 to 288 Macrocells
Low Cost
XC9500XL, 3.3V, 36 to 288 Macrocells
XC9500XV, 2.5V, 36 to 288 Macrocells
XCR3000XL, 3.3V, 36 to 512 Macrocells
XC2Cxxx, 1.8V, 32 to 512 Macrocells
Low Power, High
Speed, Low Cost
Spartan, 5V, 5000 to 40000 Max System Gates
Spartan II E, 1.8V, 50000 to 300000 Max System Gates
Vertex, 2.5V, 50000 to 1 Mil. Max System Gates
VertexII, 1.5V, 40000 to 10 Mil. Max System Gates
VertexE, 1.8V, 50000 to 3.2 Mil. Max System Gates
Spartan II , 2.5V, 15000 to 200000 Max System Gates
Spartan XL, 3.3V, 5000 to 40000 Max System GatesLow Cost
Feature Rich, High
Density
www.ScientechWorld.com
Altera Devices at a Glance
•Programmable Logic Families
–High & Medium Density FPGAs
•Stratix
™
II, Stratix, APEX
™
II,
APEX 20K, & FLEX
®
10K
–Low-Cost FPGAs
•Cyclone
™
& ACEX
®
1K
–FPGAs with Clock Data Recovery
•Stratix GX & Mercury
™
–CPLDs
•MAX
®
7000 & MAX 3000
–Embedded Processor Solutions
•Nios
™
, Excalibur
T™
Altera Devices at a Glance
•Programmable Logic Families
–High & Medium Density FPGAs
•Stratix
™
II, Stratix, APEX
™
II,
APEX 20K, & FLEX
®
10K
–Low-Cost FPGAs
•Cyclone
™
& ACEX
®
1K
–FPGAs with Clock Data Recovery
•Stratix GX & Mercury
™
–CPLDs
•MAX
®
7000 & MAX 3000
–Embedded Processor Solutions
•Nios
™
, Excalibur
T™
www.ScientechWorld.com
TTL Logic
Design Specification
Truth Table
Boolean Expression
Available
Inventory
Cost and
performance
requirement
Logic minimization
and multilevel
logic optimization
Implementation
Design Specification
Design Description
Design Software
Fuse Map
Programmable Logic
Compare Design Process ….
Device
TTL Logic
Design Specification
Truth Table
Boolean Expression
Available
Inventory
Cost and
performance
requirement
Logic minimization
and multilevel
logic optimization
Implementation
Design Specification
Design Description
Design Software
Fuse Map
Programmable Logic
Compare Design Process ….
Device
www.ScientechWorld.com
The Goal of IC Designer
Meet the market requirement
Satisfying the customers needs
- Beating the competition
- Increasing the functionality
- Reducing the cost
Achieved by
- using the next generation Silicon Technologies
- new design concepts & tools
- high level integration
The Goal of IC Designer
Meet the market requirement
Satisfying the customers needs
- Beating the competition
- Increasing the functionality
- Reducing the cost
Achieved by
- using the next generation Silicon Technologies
- new design concepts & tools
- high level integration
www.ScientechWorld.com
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Categories
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