btech minor projectppt.pptx nanowire fet

nanowire fet

1. DESIGN OF NANOWIRE FeFET BASED NON-VOLATILE MEMORY CELL FOR LOW POWER APPLICATIONS Ph.D. COMPREHENSIVE Presentation Presented by:   SUPERVISOR: Dr. TARUN CHAUDHARY Department of Electronics and Communication Engineering Dr. B. R. Ambedkar National Institute of Technology, Jalandhar Punjab, 144011

2. Outline Introduction Literature Review Research Gaps Motivations Objectives Research Methodology Work Done so far Simulation Results Work Plan Publications References Department of Electronics and Communication Engineering 2

3. Introduction For over 50 years the semiconductor industry has marched at the pace of Moore’s Law. Moore’s Law Gordon E. Moore predicted that number of transistors in a dense IC continue to grow exponentially. Device scaling is facing challenges such as: Power Dissipations Short Channel Effect Hard to have an “always-on” feature in portable electronics.- Requires frequent recharging Researchers have investigated a number of methods to lower the off-state current of CMOS devices in order to reduce total power consumption. MOSFETs have been scaled down to the nano regime in the past few decades. Fig.1 Courtesy of Intel Corporation [1] Department of Electronics and Communication Engineering 3

4. Problems faced by MOSFET in nanoscale regime High leakage current S ubthreshold swing (SS) limitation to 60mV/decade Power supply and threshold voltage Low Switching Speed Short Channel Effects such as DIBL Power Dissipation Low reliability Solutions Partially Depleted Silicon on Insulator (PDSOI) Fully Depleted Silicon on Insulator (FDSOI) FinFETs Nanowire Field Effect Transistor Tunnel Field Effect Transistor (TFET) Gate all around Nanowire TFET Junctionless Transistors Nanowire Ferroelectric Field effect Transistor (NW FeFET) Fig. 2 Practical Migration of transistor structure from FinFET to GAA to fully vertical [7] Department of Electronics and Communication Engineering 4

5. Department of Electronics and Communication Engineering 5 Nanowire Nanowire is a nanostructure,  with the diameter of the order of a nanometre (10 −9  metres) Length varies from a few atoms to many microns Different name of nanowires in literature: Whiskers, fibbers: 1D structures ranging from several nanometres to several hundred microns Nanowires: Wires with large aspect ratios (e.g. >20), Nanorods: Wires with small aspect ratios. Nano Contacts: short wires bridged between two larger electrodes.

6. Department of Electronics and Communication Engineering 6 Fig 3. Types of Nanowires

7. Department of Electronics and Communication Engineering 7 Fig. 4 . Classification of semiconductor Memory Types of eNVM

8. Research Gaps As MOSFET technology is facing many severe problems as a memory such as low retention time, high power dissipations etc. So FeFET replaces MOSFET technology Following research gaps are observed after survey of literature. Scaling of MOSFET introduce various shortcoming Abrupt junctions are essential for efficient FeFET. The main challenge in Nanowire FET is to realize high ON currents compared with MOSFET counterparts. Dielectric Modulated FET has few shortcomings, which limits the use of memory such as high cost, low retention time, high power dissipations, large area From literature survey, it has been found that the research work related to Nanowire based Non Volatile Memory is needed to be explored. So by applying various performance enhancement techniques, the device needs to be explored further for betterment and use in memory applications Department of Electronics and Communication Engineering 8

9. Motivation Best Possible Electrostatic Control To resolve the problem of higher doping concentration because it can lead to higher RDF and variability of threshold voltage in MOSFET Cost-effective development High retention time To explore FeFET for future Non-volatile Memory ( FeRAM ). Department of Electronics and Communication Engineering 9

10. Device Design (Si NW FET) Department of Electronics and Communication Engineering 10 Fig . 12 (a) Represent the Cross Sectional View of Si Nanowire FET (b) 3 Dimensional Structure of Si Nanowire FET (a) (b)

11. Device Parameters and Dimensions Parameters Si NW FET Ge NWFET MOSFET [26] Gate Length(L G ) 50nm 50nm 100nm Source Length(L S ) 50nm 50nm 100nm Drain Length(L D ) 50nm 50nm 100nm Gate Oxide thickness(T OX ) 5nm 5nm 3nm Channel Radius(R) 18nm 18nm Channel Doping 10 16 cm -3 Intrinsic 10 17 cm -3 Source Doping 10 20 cm -3 10 17 cm -3 10 20 cm -3 Drain Doping 10 20 cm -3 10 17 cm -3 10 20 cm -3 Work Function(ø) 4.8eV 4.8eV 4.6eV Department of Electronics and Communication Engineering 11