cache_memory_presentation_for_computer_archieture.pptx

Computer Architecture Programing syllabus

1. What is Cache Memory? Definition: Cache is a small, high-speed memory component built using SRAM (Static RAM) that stores copies of data and instructions from Main Memory. Goal: To provide data to the CPU with minimum latency. Core Principle: Locality of Reference - Temporal Locality: If an item is accessed now, it will likely be accessed again soon. - Spatial Locality: If an item is accessed now, items nearby in memory will likely be accessed soon.

2. The Memory Hierarchy Pyramid Concept: Organizing storage levels based on speed, size, and cost. Cache is at the top (fastest). Structure (Top to Bottom): - Registers (Fastest, Smallest) - L1 Cache (On-chip, small, split I/D) - L2 Cache (On-chip, larger) - L3 Cache (Shared, largest on-chip cache) - Main Memory (DRAM) - Secondary Storage (SSD/HDD) (Slowest, Largest) Key Trend: Moving down the pyramid: Speed decreases, Size increases, and Cost per bit decreases.

3. How Data is Retrieved Process Flow: 1. CPU issues a read request for an address. 2. The cache is checked first. Cache Hit: - The requested data is found in the cache. - Data is returned to the CPU quickly. (Goal: High Hit Rate, e.g., > 95%). Cache Miss: - The requested data is not found in the cache. - CPU stalls. - The data block is fetched from the next lower level (L2 or Main Memory). - The block is stored in the cache (and sent to the CPU).

4. CPU-Cache-Memory Interaction

5. Where Does the Data Go? (Mapping)

6. Set-Associative Mapping (The Standard) Set-Associative Cache: - Compromise between Direct Mapped and Fully Associative. - Memory blocks map to a specific set, can be placed in any line within the set. - Example: 4-way Set-Associative has 4 lines per set. - Pros: Reduces conflict misses, manageable complexity. Address Breakdown: Memory Address = Tag | Index | Block Offset - Tag: Identifies block in set. - Index: Identifies set. - Block Offset: Identifies byte in block.

7. Data Management Policies

8. Cache Performance