Ch 8 FET Amplifiers Input impedance of all commercially available JFET being sufficiently large we can assume an open circuit at input terminal .pptx

Input impedance of all commercially available JFET being sufficiently large we can assume an open circuit at input terminal

1. Introduction Excellent Voltage Gain although less on a comparative scale with BJT High Input Impedance. Better than BJT. Output impedance comparable to BJT Low Power consumption Good operational frequency response Voltage controlled Device : Output current controlled by input voltage ( V gs ) Whereas the BJT has an amplification factor, β (beta), the FET has a transconductance factor, g m . Enhancement MOSFET is very popular in Digital IC Most Common Configuration is Common source configuration providing the inverted gain Common drain configuration is used as source follower with unity non-inverted gain. And Common gate provides non-inverting gain Due to very high input impedance the input current is assumed to be 0 µA implying the current gain is unidentified quantity In this chapter we will focus to determine input impedance, output impedance and voltage gain

2. JFET small-signal model Model should reflect a voltage at input (gate-to-source) controlling the current (drain-to-source). Just as dc gate-to source voltage controls DC current expressed by shockleys equation Change in drain current influenced by change in gate to source voltage g m is trans-conductance factor: prefix “Trans” represents a relationship that g m establishes between input and output. And conductance is due to the dimension of ratio I/V

3. Graphical determination of g m Graphically gm is the slope of the characteristic at point of operation Q. Note slope increase between V P to I DSS where V GS =0

4. M athematical definition of g m Graphical method is limited in accuracy Derivative at a point is the slope of the tangent line drawn at that point can represent g m mathematically We take derivative between I d and V GS using shockleys equ Absolute V P to ensure positive value @ VGS=0 we should have maximum slope So that Data sheet specification

5. Sufficiently close enough to graphical value

6. Plotting g m versus V GS

7. E ffect of I D on g m Rearranging the Shockley's equation Substitute it in equation for g m determining g m for a few specific values

8. JFET I nput impedance Zi Input impedance of all commercially available JFET being sufficiently large we can assume an open circuit at input terminal Typically

9. Output Impedance For e.g of g os =10µS, then R=1/G=1/10µS=100K Ω Typically similar in magnitude to the BJT’s Graphically Defined on drain characteristics A slope at the point of operation More horizontal means a closer to ideal of infinite

10. JFET A C equivalent Circuit Voltage controlled current source Current direction consistent with 180 degrees out of phase b/w input and output Open Circuit @ input r d @ output b/w drain and source. If sufficiently large then may be ignored Source common to both Input and Output Where as G and D are connected only through the current source

11. Fixed-bias Configuration In parallel to the BJT’s, we’ll be seeking Z i , Z O , and A V Will act as short circuit for ac analysis Once g m and r d are determined dc biasing arrangement Specification sheet O r characteristics Circuit is replaced with AC equivalent model Coupling Capacitors short circuited DC batteries VDD and VGG grounded or set to 0

12. AC analysis for fixed bias Polarity of V gs defines the direction of the current source g m V gs , consistent with 180 O out of phase signal of output V O across ,w.r.t input V i   Because of infinite impedance @ the input terminal of JFET Setting Vi=0, V gs =0V, g m V gs =0A, Open circuit r d >>R D typically and so Solving For V O So that

13. SELF-BIAS CONFIGURATION Unlike the fixed-biased the self-bias has only 1 DC supply to establish the required Operating point Open circuit for DC and short circuit for AC AC Equivalent Note the AC equivalent circuit of self-biased bypassed case is exactly the same as fixed-bias AC equivalent case (Since for AC analysis R S is bypassed considering C S as short circuit path). Equations similar to fixed bias case

14. SELF-BIAS ( Unbypassed ) C S removed so R S not shorted Due to open circuit condition b/w the gate and output network Going by Definition with Vi=0V Gate is effectively shorted to ground value. Voltage across RG is zero By KCL Voltage @ RS Since R earranging

15. SELF-BIAS ( Unbypassed with r d ) By KCL with Voltage @ RS

16. Voltage gain KVL @ Input

17. Voltage-divider Configuration   With open circuit we have a parallel network expressed as Input impedance of the network Output impedance Same gain and Z seen for previous two configurations (Fixed bias and self bias). Only Input impedance is different

18. Common-Gate Configuration Common Gate configuration in JFET parallels common base configuration of BJT’s The isolation between the input and out has been lost as the isolation comes from the gate side which is now not the input side. Note the controlling voltage Vgs now appears directly across RS connected between input terminal

19. Input Impedance of the Network Rs is directly across the terminals defining Zi . We’ll find     Rearranging Applying KCL @ node a Rearranging and substituting for Ird Using Vrd from above in ohms law or as   Rearranging for the ratio or Now finding Zi as  

20. Output Impedance and Gain of the Network Applying KCL @ node b  

21. Source-Follower ( Common-drain) Configuration The JFET equivalent of the BJT emitter-follower configuration is the source-follower configuration Output is taken from the source Terminal when the dc supply is replaced by its short-circuit equivalent, the drain is grounded (hence, the terminology common - drain) Tied to the drain terminal at one end And R S Terminal on the other end Output driven out from R S Since g m V gs , r d , and R S are connected to the same terminal and ground, they can all be placed in parallel

22. Input Impedance Vgs is still defined between G and S terminals

23. Output Impedance Setting V i = 0 V results in the gate terminal being connected directly to the ground Applying KCL @ node S Solving for I

24. Voltage Gain By KVL Denominator is greater than Numerator Gain < 1

25. Effect o f R L and R sig In line with earlier discussion on BJT’s we have once again two approaches Model Based approach with AC model used with R L and R sig and then doing AC analysis. Two port approach which has universality and so equally applicable with FET device as relies on the important parameters at the outer ports. i.e. All of the two-port equations developed for the BJT transistor apply to FET networks also because the quantities of interest are defined at the input and output terminals and not the components of the system. So these equation are still relevant Also the earlier conclusion still hold for the unloaded, loaded and overall gain

26. Example of the two approaches: AC model based approach let us examine the self-bias configuration Loaded Gain, as R L appears in parallel to R D Unchanged as per defined location Once again unchanged For Overall Gain As R G appears in series with R sig and

27. Example of the two approaches: Two Port Approach   The above derivation was included to demonstrate that the same result will be obtained using either approach If numerical values for Ri , Ro , and A v NL were available, it would simply be a matter of substituting the values into equ

28. Cascade Configuration The cascade configuration for BJTs can also be used with FET’s O utput of one stage appears as the input for the following stage . The input impedance for the second stage is the load impedance for the first stage . For each stage the loading effect of the following stage must be included in the gain calculations. This looks like a multistage amplifier in self bias configuration. Loaded gain of each stage is multiplied to get overall loaded gain. This is the way to include the loading effect.