Chapt12Processor Structure and Function.ppt

Processor Structure and Function

1. Computer Organization and
Architecture
Designing For Performance
William Stallings
Seventh Edition

2. Team #5
 -12.1 Processor Organization
 -12.2 Register Organization
 -12.3 Instruction Cycle
 -12.4 Instruction Pipelining/ Dealing with
Branches

3. 12.1 Processor Organization
Fetch Instruction
Interpret instruction
Fetch Data
Process Data
Write Data

4. Remember….
The processor needs to store some data
temporally.
It must remember the location of the last
instruction so that it can know where to get
the next instruction.
It needs to store instructions and data
temporally while an instruction is being
executed.

5. CPU with System Bus

6. CPU Internal Structure

7. Register Organization
User-visible registers
Control and status registers

8. User Visible Registers
General Purpose
Data
Address
Condition Codes

9. General Purpose Registers
Data
Accumulator
Addressing
Segment pointers
Index registers
Stack Pointer

10. Control & Status Registers
Program Counter
Instruction Decoding Register
Memory Address Register
Memory Buffer Register

11. Program Status Word
Sign
Zero
Carry
Equal
Overflow
Interrupt enable/disable
Supervisor

12. Example Register Org.

13. Instruction Cycle
It is the time in which a single
instruction is fetched from memory,
decoded, and executed
An Instruction Cyclerequires the
following subcycle:

14. Instruction Cycle
Fetch
Read next instruction from memory into the
processor
Indirect Cycle (Decode Cycle)
May require memory access to fetch operands,
therefore more memory accesses.
Interrupt
Save current instruction and service the interrupt
Execute
Interpret the opcode and perform the indicated
operation

15. Instruction Cycle
Fetch
Execute
Fetch
Execute
Indirect
Fetch
Execute
Interrupt
Fetch
Execute
IndirectInterrupt

17. Data Flow (Fetch Diagram)
PC
Control
Unit
PC MARMAR
MemoryMemory
Control
Unit
MBR
Memory
IR MBR

18. Data Flow (Indirect Diagram)
MBR
MARMAR
Memory
Control
Unit
Memory
MBR
Memory

19. Data Flow (Execute)
May take many forms
Depends on instruction being executed
May include
Memory read/write
Input/Output
Register transfers
ALU operations

20. Data Flow (Interrupt Diagram)
Control
Unit
PC
MBR
PC
Control
Unit
MARMAR
Memory
MBR
MemoryMemory
Control
Unit
Control
Unit
PC

21. 12.4 Instruction Pipelining
Instruction processing is subdivided:
-Fetch/ Execute instruction
Pipeline has two independent stages:
1
st
Stage –Fetch an instruction and buffers it.
2
nd
Stage –Temporarily free until first stage passes it the
buffered instruction.
While the second stage is executing the instruction, the
first stage fetches and buffers the next instruction.
Instruction prefetch or fetch overlap.
-Purpose? To speed up instruction execution.

22. Two-Stage Instruction Pipeline

23. Instruction Processing
Fetch instruction (FI)
Decode instruction (DI)
Calculate operands (CO)
Fetch operands (FO)
Execute instruction (EI)
Write operand (WO)
Successive instructions in a program sequence
will overlap in execution.

24. Timing Diagram for Instruction
Pipeline Operation

25. Six-Stage CPU
Instruction
Pipeline
The logic needed for
pipelining to
account for
branches, interrupts,
and arising
problems.

26. Alternative Pipeline Depiction

27. RISC
Pipeline
1.Instruction fetch
2.Instruction decode and register fetch
3.Execute
4.Memory Access
5.Register write back

28. Branches
Branch-group of instructions
Branch Instructions –(Jump Instruction)
One of it’s operands is the address of the
next instruction to be executed.

29. Branches
Two Types of Branch Instructions
Unconditional –Branch always happens
Conditional –Branch only happens if certain
condition is met.
The PC is updated to the address specified in
the operand of the conditional branch
instruction.
A conditional branch instruction is similar
to an if statement.

30. Conditional Branch Instructions
Condition Codes
BRP X
Branch to location X if result is positive
BRZ X
Branch to location X if result is zero
BRE R1,R2,X
Branch to location X if contents of R1 = R2

31. Conditional Branch Instructions

32. Dealing with Branches
A major problem in designing an instruction
pipeline is assuring a steady flow of
instructions to the initial stages of the
pipeline.
Since conditional branches alter the steady
flow of instructions, we must come up with
ways to execute them efficiently.

33. Dealing with Branches
5 Approaches to Dealing with Conditional
Branches
Multiple Streams
Delayed Branch
Prefetch Branch target
Loop Buffer
Branch Prediction

34. Dealing with Branches
•Multiple Streams (IBM 370/168 and IBM 3033)
Pipeline fetches both instructions.
Leads to contention delays, and branches
can lead to too many streams.
•Delayed Branch
Branch Instruction occurs later than desired.
•Prefetch Branch Target (360/91 IBM)
The target of the branch is prefetched, along
with the instruction following the branch, so if
the branch is taken this will speed up
performance.

35. Dealing with Branches
Loop buffer ( Motorola 68010)
Memory containing the n most recently fetched
instructions.
Useful with if-then and if-then-else statements,
as well as loops
Branch Prediction
Different techniques are used to predict whether
the branch will be taken or not
If the prediction is correct this will speed up
performance

36. Dealing with Branches

37. Intel Pentium Branch
The prediction of whether a jump will
occur or not, is based on the branch’s
previous behavior. There are four
possible states that depict a branch’s
disposition to jump:
Stage 0: Very unlikely a jump will
occur
Stage 1: Unlikely a jump will occur
Stage 2: Likely a jump will occur
Stage 3: Very likely a jump will occur

38. Intel Pentium Branch
It is actually believed
that Pentium’s original
algorithm for branch
prediction was
incorrect. (Left)

39. Research
http://www.it.jcu.edu.au/Subjects/cp1300/resources/lectno
tes/system/fde.html
http://dr-pisit.com/csc331/Lec10-CPU&Pipeline.pdf
http://en.wikipedia.org/wiki/Instruction_pipelining
http://www.itreviews.co.uk/hardware/h738.htm

40. Review Questions
1. What are the major components of a processor?
2. What is the function of the ALU?
3. What is the function of the control unit?
4. What are the two roles that registers in the processor
perform?
5. What are bits set by the processor hardware as a result
of operations?
6. What is an instruction cycle?
7. What are the four subcycle of an instruction cycle?

41. 8. Is the fetch or execute cycle the same for all CPU?
9. What is the sequence of an interrupt cycle?
10. What is the main purpose for instruction pipelining?
11. How can you make the pipelining more efficient?
12. What is a condition code?
13. What is another name for a branch instruction?

42. Answers
1.Arithmetic and Logic Unit (ALU) and the Control Unit (CU).
2.The ALU does the actual computation or processing of data.
3.The control unit controls the movement of data and
instructions into and out of the processor and controls the
operations of the ALU.
4.User-visible registers, and control and status registers.
5.Condition codes.
6.It is the time in which a single instruction is fetched from
memory, decoded, and executed.
7.Fetch, Indirect (if any) , execute, and interrupt (if any).

43. 8.No, it depends on the CPU’s design.
9.PC MBR
Address of Stack MAR
MAR Memory
PC Memory
Control Unit request memory write via Control Bus
PC is loaded with address of Interrupt handler
10.To speed up the instruction execution rate.
11.To gain further speedup, the pipeline must have more stages
for decomposition.
12.A statement that if true will allow the branch to be
executed.
13.A jump instruction.