Characteristics of cmos ic series

MOS technology,MOSFET switch, CMOS LOGIC, CMOS SERIES CHARACTERISTICS, NOR NAND AND NOT gates,types of CMOS IC's

1. CHARACTERISTICS OF CMOS IC SERIES

2. Nithyapriya . S Prashanna.R Praveen kumar .S Preethi.A Sathish Kumar.S Shagari DONE BY

3. Metal oxide semiconductor Advantages: Relatively simple, inexpensive to fabricate, small, consumes little power Occupy less space on chip High packing density. So well suited for microprocessor and memory chips. Disadvantage Susceptibility to static electricity damage. Less durable than TTL devices MOS TECHNOLOGY

4. MOS digital IC’s use enhancement MOSFET’s. THE MOSFET

5. N Channel Basic MOSFET Switch

6. P Channel MOSFET

7. CMOS uses both P-MOS and N-MOS transistors in the same logic circuit. So this is referred as complementery MOS, or CMOS. CMOS LOGIC

8. CMOS INVERTER

9. CMOS NOR GATE

10. CMOS NAND GATE

11. Pin compatible Functionally compatible Electrically compatible CMOS SERIES CHARACTERISTICS

12. 4000-oldest CMOS series, introduced by RCA. 4000’s equivalent 14000 series introduced by Motorola. Low power dissipation cooperate over wide range of power supply voltages(3V – 15 V) Very slow Low output current capability. Not pin compatible, Electrically compatible. 4000/14000 Series

13. 10 fold increase in switching speed High output current capability. Pin compatible, fuctionally equivalent to TTL IC’s with same device number. 74HCT are electrically compatible with TTL IC’s, but 74HC are not. 74 HC/HCT (High speed CMOS)

14. Functionally equivalent but not pin compatible with TTL to I prove noise immunity. 74 AC are not electrically compatible with TTL. 74 ACT devices can be connected directly to TTL. 74 AC/ ACT ( A dvanced CMOS)

15. Offers a natural migration path from the HC series to faster, lower power, low drive application. Three times faster. used as direct replacement of HC 74 AHC/AHCT (Advanced High Speed CMOS)

16. Combine the features of bi polar and CMOS . Low power charecteristics of CMOS and high power charecteristics of bipolar circuits are integrated in BiCMOS . BiCMOS IC used in microprocessors and bus interfacing applications such as latches, buffers, drivers and transceivers. It offers 74% reduction in power consumptions over74 F family. Pin compatible with TTL Operates on standard 5V logic levels. BiCMOS

17. Stray electric and magnetic fields may induce unwanted voltages, known as noise, on the connecting wires between logic circuits. This may cause the voltage at the input to a logic circuit to drop below V IH (min) or rise above V IL (max), which could produce unpredictable operation. The circuit’s ability to tolerate noise signals is referred to as the noise immunity. Noise immunity

18. Noise margin is the amount of noise that a CMOS circuit could withstand without compromising the operation of circuit. Noise margin does makes sure that any signal which is logic '1' with finite noise added to it, is still recognised as logic '1' and not logic '0'. It is basically the difference between signal value and the nosie value. Noise margin

19. The high-state noise margin V NH is given by V NH = V OH (min) - V IH (min) The low-state noise margin V NL is given by V NL = V IL (max) - V OL (max) Noise margin levels

20. Noise margins for CMOS chips are usually much greater than those for TTL because the VOH min is closer to the power supply voltage and VOL max is closer to zero. The difference would be even greater if the CMOS devices were operated at a supply voltage greater than 5 V. Advancement over TTL

21. Invalid Voltage Levels For proper operation the input voltage levels to a logic circuit must be kept outside the indeterminate range. That is, they must be either lower than V I L or higher than V IL . In normal operation, a logic input voltage will not fall into the invalid region because it comes from a logic output that is within the stated specifications . However, when this logic output is malfunctioning or is being overloaded (i.e., its fan-out is being exceeded), then its voltage may be in invalid region. Invalid voltage levels in a digital circuit can also be caused by power-supply voltages that are outside the acceptable range. Logic Voltage Levels

22. The input and output voltage levels will be different for the different CMOS series. The values listed in the table assume that all devices are operating from a supply voltage of 5 V and that all device outputs are driving inputs of the same logic family. From the table it is clear that V OL for the CMOS devices is very close to 0 V, and V OH is very close to 5 V. The reason why is that the CMOS outputs do not have to source or sink any significant amount of current when they are driving CMOS inputs with their extremely high input resistance(10 12 ). Logic Voltage Levels

23. Input output voltage levels

24. Graphical representation of voltage levels

25. When a CMOS logic circuit is in a static state (not changing), its power dissipation is extremely low . CMOS dissipates power only when switching ("dynamic power"). Typical CMOS dc power dissipation of only 2.5 nW per gate when VDD = 5V ; even at VDD=10V this power increases to only 10 nW. Thus CMOS is ideally suited for applications using battery power or battery backup power. Power dissipation

26. Types of PD

27. Dynamic power: due to charging and discharging of output capacitances. I n one complete charge/discharge cycle, a total of Q=C L V DD is thus transferred from VDD to ground. I= C L V DD *f P= C L V 2 DD *f Short-circuit power: due to finite rise/fall times for both P & N MOS in which both the transistors will be on for a small period of time. Leakage power: (important with decreasing device sizes). Typically between 0.1nA -0.5nA at room temperature Where Does Power Go in CMOS?

28. FAN OUT Like N-MOS and P-MOS, CMOS inputs have an extremely large resistance that draws essentially no current from the signal source. This input capacitance limits the number of CMOS inputs that one CMOS output can drive The CMOS output must charge and discharge the parallel combination of all of the input capacitances, so that the output switching time will be increased in proportion to the number of loads being driven.

29. FAN OUT Thus, CMOS fan-out depends on the permissible maximum propagation delay. Typically, CMOS outputs are limited to a fan-out of 50 for low frequency operation (1 MHz). Each CMOS input adds to the total load capacitance seen by the driving gate’s output.

30. SWITCHING SPEED The output resistance of CMOS is low in both the states (0 or 1) of output. So eventhough it has to drive large capacitive loads ,the switching speed can be somewhat faster than the NMOS or PMOS devices. The NAND gate of 4000 series has following values of propagation delays, Average tpd =50ns…..at Vdd =5V Average tpd =25ns…..at Vdd =10V

31. UNUSED INPUTS CMOS inputs should never be left disconnected. All CMOS inputs must be tied either to a fixed voltage level (0 V or V DD) or to another input. This rule applies even to the inputs of extra unused logic gates on a chip. An unconnected CMOS input is susceptible to noise and static charges that could easily bias both the P-channel and the N-channel MOSFETs in the conductive state, resulting in increased power dissipation and possible overheating.

32. FAN OUT FOR INTERFACING 74AS TO 74AS I 0H = -2m I 0L = 20m I 1H = 0.02m I 1L = -0.5m Fan-out (high) = I 0H (min) / I 1H (min) = 2m/0.02m = 100 Fan-out (low) = I 0L (max) / I 1L (max) = 20m/0.5m = 40.

33. 74F-74F I 0H = -1m I 0L = 20m I 1H = 20m I 1L = -0.6m Fan-out (high) = I 0H (min) / I 1H (min) = 1m/20m = 50 Fan-out (low) = I 0L (max) / I 1L (max) = 20m/-0.6m = 33.33

34. 74AHC TO 74AS 74AHC 74AS I 0H = -8m I 1H = 0.02m I 0L = 8m I 1L = -0.5m Fan-out (high) = I 0H (min) / I 1H (min) = -8m/0.02m = 400 Fan-out (low) = I 0L (max) / I 1L (max) = 8m/-0.5m = 16

35. 74HC TO 74ALS 74HC 74ALS I 0H = -4m I 1H = 20µ I 0L = 4m I 1L = -0.1m Fan-out (high) = I 0H (min) / I 1H (min) = -4m/20µ = 200 Fan-out (low) = I 0L (max) / I 1L (max) = 4m/-0.1m = 40

36. Electrostatic sensitive device An electronic sensitive device (ESD) is any component which can be damaged by common static charges which build up on people,tools and other non conductors or conductors Common ESD devices include: 1. MOSFET transistors 2. CMOS Ics 3. Computer cards 4. TTL chips 5. Laser diodes STATIC SENSITIVITY

37. The CMOS Ics are susceptible to the damages due to static electricity(voltages upto about 30KV) gets generated by our simple day to day actions. For eg . if a person walks on a carpet,then it will generate a voltage of 30KV. If the person touches the gate of a MOSFET then the oxide layer will breakdown, due to large voltage and the device will be permanently damaged.

38. Such a damage is called as damage due to electrostatic discharge (ESD) , and we have to use a resistor diode protection network for protection. Prevention: 1. Using a resistor diode protection network 2. Do not place the chips on carpet,fabric or any other fibrous surface

39. Latchup is the generation of a low-impedance path in CMOS chips between the power supply and ground This is due to the interaction of two parasitic PNP and NPN bipolar transistors This causes excessive current flow and permanent damage to the device LATCH-UP

40. LATCHUP

41. Surrounding PMOS and NMOS transistors with an insulating oxide layer (trench). Latchup Protection Technology circuitry which shuts down the chip and holds it powered down when latchup is detected . Most silicon on insulator devices are inherently latch up resistant Prevention

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