Clock triggering, Flip Flop(RS and JK)

Flip Flop and its 2 type

1. Clock Triggering, Flip Flop(RS, JK diagram) Amshal Ejaz

2. Clock Triggering Clock signal: Clock signal is a periodic signal and its ON time and OFF time need not be the same. We can represent the clock signal as a  square wave , when both its ON time and OFF time are same. This clock signal is shown in the following figure. 5V 0V High low

3. The clocked flip flop are triggered during the positive edge of the pulse rate, and the state transition start as soon as the pulse reaches. Positive pulse Negative pulse

4. Flip Flops A flip flop is a binary storage device. It can store binary bit either 0 or 1. It has two stable states HIGH and LOW i.e. 1 and 0. The basic formation of flip flop is to store data. It is also called bistable multivibrator.

5. Type of Flip Flops 1. R-S Flip Flop: The RS( Reset-Set ) is one of the simplest sequential circuits and consists of two gates connected. It has two inputs, one is called  “SET”  which will set the device (output = 1) and is labelled S and another is known as  “RESET”  which will reset the device (output = 0) labelled as R. 

6. The output of each gate connected to one of the inputs of the other gate. The circuit has two active low inputs marked S and R, as well as two outputs, Q and Q’.

7. Diagram:

8. 2. J K Diagram: The  JK Flip Flop  is the most widely used flip flop. It is considered to be a universal flip-flop circuit. The sequential operation of the JK Flip Flop is the same as for the RS flip-flop with the same  SET  and  RESET  input. The difference is that the JK Flip Flop does not the invalid input states of the RS Latch (when S and R are both 1). The JK Flip Flop name has been kept on the inventor name of the circuit known as  Jack Kilby. 

9. Diagram: