CMOS fabrication.pptx

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1. TOPICS: CMOS Fabrication process using N-well Latch up

2. CMOS Fabrication Process CMOS can be obtained by integrating both NMOS and PMOS transistors over the same silicon wafer. Fabrication of CMOS is described using the P-substrate, in which the NMOS transistor is fabricated on a P-type substrate and the PMOS transistor is fabricated in N-well.

3. Step 1: Substrate Primarily, we choose a substrate as a base for fabrication. For N-well, a P-type silicon substrate is used. Step 2: Oxidation The oxidation process is done by high-purity oxygen and hydrogen, which are exposed in an oxidation furnace approximately at 1000 degree centigrade. Step 3: Photoresist A light -sensitive polymer that softens whenever exposed to light is called as Photoresist layer.

4. Layout versus Schematic: Step 4: Masking The Photoresist is exposed to UV rays through the N-well mask o n ly verifies that the given layout satisfies the design rules provided by the fabricatio n unit. It doesnot ensure the functionality of layout. Because of this ,idea of LVS is originated. INPU Step 5: Photoresist removal A part of the photoresist layer is removed by treating the wafer with the basic or acidic solution. Step 6: Removal of SiO2 using acid etching The SiO2 oxidation layer is removed through the open area made by the removal of photoresist using hydrofluoric acid. TS: 1. LVS rule deck 2. Verilog netlist 3. Layout data base(GDS) 4. Spice Netlist ( extracted by tool from GDS) The LVS flow is as follows: 1. Extract schematic netlist 2. Extract the layout netlist 3. Compare the layout and schematic netlists

5. Step 7: Removal of photoresist The entire photoresist layer is stripped off. Step 8: Formation of the N-Well By using ion implementation or diffusion process N-well is formed. Step 9: Removal of SiO2 Using the Hydrofluoric acid, the remaining SiO2 is removed. nly verifies that the given layout satisfies the design rules provided by the fabrication unit. It doesnot ensure the functionality of layout. Because of this ,idea of LVS is originated. INPU

6. Step 10: Deposition of poly silicon Chemical Vapour Deposition (CVD) process is used to deposit a very thin layer of gate oxide . Step 11: Removing the layer barring a small area for the Gates Except the two small regions required for forming the Gates of NMOS and PMOS, the remaining layer s stripped off. Step 12: Oxidation process Next, an oxidation layer is formed on this layer with two small regions for the formation of the gate terminals of NMOS and PMOS. nly verifies that the given layout satisfies the design rules provided by the fabrication unit. It doesnot ensure the functionality of layout. Because of this ,idea of LVS is originated. INPU

7. Step 13: Masking and N-diffusion By using the masking process small gaps are made for the purpose of N-diffusion. The n-type (n+0 dopants are diffused or ion implanted, and the three n+ are formed for the formation of the terminals of NMOS. Step 14: Oxide stripping The remaining oxidation layer is stripped off. Step 15: P-diffusion Similar to the above N-diffusion process, the P-diffusion regions are diffused to form the terminalsof the PMOS . nly verifies that the given layout satisfies the design rules provided by the fabrication unit. It doesnot ensure the functionality of layout. Because of this ,idea of LVS is originated. INPU

8. Step 16: Laying of thick field oxide A thick- field oxide is formed in all regions except the terminals of the PMOS and NMOS. Step 17: Metallization Aluminium is sputtered on the whole wafer. Step 18: Removal of excess metal The excess metal is removed from the wafer layer nly verifies that the given layout satisfies the design rules provided by the fabrication unit. It doesnot ensure the functionality of layout. Because of this ,idea of LVS is originated. INPU

9. Step 19: Terminals The terminals of the PMOS and NMOS are made from respective gaps. Step 20: Assigning the names of the terminals of the NMOS and PMOS n layout satisfies the design rules provided by the fabrication unit. It doesnot ensure the functionality of layout. Because of this ,idea of LVS is originated. INPU

10. LATCHUP Latch-up is a phenomenon of activation of parasitic BJTs in CMOS circuit which form a low impedence path beween power supply and ground. This low impedence path draw large current which heat up the IC and cause permanent damage While manufacturing CMOS device we can see formation of PN junctions which results in the form of parasitic(unwanted & unavoidable) elements like diodes or transistors. P subtrate and Nwell has its own resistances Rs and Rw

11. By suddenly switch ON or OFF/noise/temperature/heating/ESD, the current impulse strikes at Drain. There will be enough charge particles to carry out the current particles which will slip through the well towards the substrate and collector of NPN trasistor is connected to base of PNP transistor and collector of PNP transistor is connected to base terminal of NPN transistor. Hence a feedback loop is formed. Current impulse is enough to form NPN trasistor forward biased and short circuit is formed. Collector current of NPN transistor finds a path thorough a substrate towards Nwell Parasitic BJTs are normally on OFF stage with minimal current flow but once it get triggered by Gate signal, it continue to flow large current even if the triggered gate signal has been removed. This phenomenon is actually called latched up. Rwell , Rsub are quite high. If the value of these resistances are reduced, the collector current of PNP transistor will not flow into Base terminal of NPN transistor as it finds an alternate low resistance path Rsub. In this way the other transistor will never turn ON and prevents latchup in CMOS circuits.

12. Well tap cell: Well tapping is a way to prevent latch-up, & it is nothing but connecting N+well and P+substrate to VDD and VSS respectively. Instead of minority carriers forming a transistor well contacts absorb the minority carriers & connect to VSS, by this substrate resistance is reduced and triggering point will not happen. Tap cells are placed at regular intervals in a standard cell row and distance between 2 tap cells is given in design rule manual. Tap cells absorbs noise and maintain constant bulk potential.

13. GUARD RINGS: Introduce some regions between NMOS and PMOS where the charge carriers find the least resistor path to go to respective sink it could be holes or electrons , then the current which is getting to the base of Qp would not be large enough to make the transistor ON, loop would be blocked and will not have a low impedence path. By introducing GR it finds the low resistance paths whether holes or electrons they find their respective sink.