CMOS Fabrication: Step-by-Step Device Processing for ICs — Dr. G. S. Virdi

This lecture, prepared and delivered by Dr. G. S. Virdi (Ex-Chief Scientist, CSIR-Central Electronics Engineering Research Institute, Pilani), is a comprehensive, practical guide to CMOS device fabrication intended for engineering and science students at the undergraduate and postgraduate level.
Starting from a blank silicon wafer, the presentation walks the learner through each core step of CMOS manufacturing: oxidation, photoresist and lithography, etching, n-well formation, gate oxide growth and polysilicon deposition, self-aligned gate processing, diffusion and ion implantation for n+ and p+ regions, contact formation, metallization and patterning. Mask sets, top-views and cross-sections are used to illustrate how transistors and interconnects are defined. The lecture also explains common yield and material issues encountered in modern CMOS processing, limitations of optical lithography, and emerging directions such as high-k dielectrics, SOI, FinFET/double-gate structures and twin-tub processes.
Designed from decades of R&D experience in microelectronic device design and fabrication, this lecture emphasizes conceptual clarity supported by detailed process steps and diagrams. It is especially useful for students, researchers and practicing engineers who want a clear, process-level understanding of how CMOS devices — the building blocks of integrated circuits — are fabricated.

1. FABRICATIONOFCMOS
CSIR -Central Electronics Engineering Research Institute
Pilani-333031,India

2. Outline
•OverviewofCMOS
•CMOSFabricationProcessOverview
•CMOSFabricationProcess
•ProblemswithCurrentCMOSFabrication
•FutureChangesinCMOSFabrication
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3. WhatisCMOS?
CMOStechnologyusesbothnMOSandpMOS
transistors.Thetransistorsarearrangedina
structureformedbytwocomplementarynetworks
•Pull-upnetworkiscomplementofpull-down
•Parallel->series,series->parallel
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4. CMOSFabrication
•CMOStransistorsarefabricatedonsiliconwafer
•Wafersdiameters(200-300mm)
•Lithographyprocesssimilartoprintingpress
•Oneachstep,differentmaterialsaredeposited,
orpatternedoretched
•Easiesttounderstandbyviewingbothtopand
cross-sectionofwaferinasimplified
manufacturingprocess
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5. InverterCross-section
•Typicallyusep-typesubstratefornMOS
transistors
•Requirestomakeann-wellforbodyofpMOS
transistors
n+
n+
psubstrate
p+
nwell
A
Y
GND V
DD
p+
SiO
2
n+diffusion
p+diffusion
polysilicon
metal1
nMOStransistor pMOStransistor
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n+

6. InverterMaskSet
•Topview
•Transistorsandwiresaredefinedbymasks
•Cross-sectiontakenalongdashedline
GND V
DD
Y
A
substrate tap welltap
nMOStransistor pMOStransistor
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7. DetailedMaskViews
•Sixmasks
–n-well
–Polysilicon
–n+diffusion
–p+diffusion
–Contact
–Metal
Metal
Polysilicon
Contact
n+Diffusion
p+Diffusion
nwell
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8. FabricationSteps
•Startwithblankwafer(typicallyp-typewhereNMOSiscreated)
•Buildinverterfromthebottomup
•Firststepwillbetoformthen-well(wherePMOSwouldreside)
–CoverwaferwithprotectivelayerofSiO
2(oxide)
–Removeoxidelayerwheren-wellshouldbebuilt
–Implantordiffusendopantsintoexposedwafertoformn-well
–StripoffSiO
2
psubstrate
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9. Oxidation
•GrowSiO
2ontopofSiwafer
–900–1200CwithH
2OorO
2inoxidation
furnace
psubstrate
SiO
2
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10. Photoresist
•Spinonphotoresist
–Photoresistis alight-sensitiveorganicpolymer
–Propertychangeswhereexposedtolight
•Twotypesofphotoresists(positiveornegative)
–PositiveresistscanberemovedifexposedtoUVlight
–NegativeresistscannotberemovedifexposedtoUVlight
psubstrate
Photoresist
SiO
2
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11. Lithography
•ExposephotoresisttoUltra-violate(UV)light
throughthen-wellmask
•Stripoffexposedphotoresistwithchemicals
psubstrate
Photoresist
SiO
2

12. Etch
•Etchoxidewithhydrofluoricacid(HF)
–Seepsthroughskinandeatsbone;nastystuff!!!
•Onlyattacksoxidewhereresisthasbeenexposed
•N-wellpatternistransferredfromthemaskto
silicon-di-oxidesurface;createsanopeningtothe
siliconsurface
psubstrate
Photoresist
SiO
2
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13. StripPhotoresist
•Stripoffremainingphotoresist
–Usemixtureofacidscalledpiranahetch
•Necessarysoresistdoesn’tmeltinnextstep
psubstrate
SiO
2
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14. n-well
•n-wellisformedwithdiffusionorionimplantation
•Diffusion
–Placewaferinfurnacewitharsenic-richgas
–HeatuntilAsatomsdiffuseintoexposedSi
•IonImplanatation
–BlastwaferwithbeamofAsions
–IonsblockedbySiO
2,onlyenterexposedSi
•SiO
2shields(ormasks)areaswhichremainp-type
nwell
SiO
2
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15. StripOxide
•StripofftheremainingoxideusingHF
•Backtobarewaferwithn-well
•Subsequentstepsinvolvesimilarseriesofsteps
nwell
psubstrate
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16. Polysilicon(self-alignedgatetechnology)
•Depositverythinlayerofgateoxide
–<20Å(6-7atomiclayers)
•ChemicalVaporDeposition(CVD)ofsiliconlayer
–PlacewaferinfurnacewithSilanegas(SiH
4)
–Formsmanysmallcrystalscalledpolysilicon
–Heavilydopedtobegoodconductor
nwell
psubstrate
Polysilicon
Thingateoxide
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17. PolysiliconPatterning
•Usesamelithographyprocessdiscussedearlier
topatternpolysilicon
Polysilicon
psubstrate
Polysilicon
Thingateoxide
nwell
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18. Self-AlignedProcess
•Usegate-oxide/polysiliconandmaskingto
exposewheren+dopantsshouldbediffusedor
implanted
•N-diffusionformsnMOSsource,drain,andn-
wellcontact
psubstrate
nwell
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19. N-diffusion/implantation
•Patternoxideandformn+regions
•Self-alignedprocesswheregateblocksn-dopants
•Polysiliconisbetterthanmetalforself-alignedgates
becauseitdoesn’tmeltduringlaterprocessing
n+Diffusion
p substrate
n well
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20. N-diffusion/implantationcont.
•Historicallydopantswerediffused
•Usuallyhighenergyion-implantationused
today
•Butn+regionsarestillcalleddiffusion
nwell
psubstrate
n+n+ n+
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21. N-diffusioncont
•Stripoffoxidetocompletepatterningstep
nwell
psubstrate
n+n+ n+
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22. P-Diffusion/implantation
•Similarsetofstepsformp+“diffusion”regions
forPMOSsourceanddrainandsubstrate
contact
p+Diffusion
psubstrate
n+n+ p+ p+ n+
nwell
p+
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23. Contacts
•Nowweneedtowiretogetherthedevices
•Coverchipwiththickfieldoxide(FO)
•Etchoxidewherecontactcutsareneeded
Contact
p substrate
Thickfieldoxide
n well
n+n+ n+p+p+p+
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24. Metalization
•Sputteronaluminumoverwholewafer
•Copperisusedinnewertechnology
•Patterntoremoveexcessmetal,leavingwires
Metal
psubstrate
Metal
Thickfieldoxide
nwell
n+n+ n+p+p+p+
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25. ProblemswithCurrentCMOS
Fabrication
•Opticallithographyislimitedbythelight
frequency.
•Materiallimitations
•Yieldlimitations
•Spacelimitations
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26. FutureChangesinCMOSFabrication
•Materialchangeslikeusinghigh-kmaterials.
•Designchanges
–SOI(SiliconOnInsulator)
–DoubleGate(Finfet)
–Twin-TubProcess
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