CMOS integrated Fundamentals technology .ppt
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Oct 02, 2025
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About This Presentation
CMOS (Complementary Metal-Oxide-Semiconductor) is a widely used digital logic technology that employs both NMOS and PMOS transistors to implement logic functions with very low static power consumption. In a CMOS inverter, the basic building block, the PMOS transistor connects to Vdd and conducts whe...
Slide Content
CMOS FUNDAMENTALS
IDEALIZED MOS STRUCTRE
•The application of a voltage across the MOS capacitor establishes an
electric field ξ
o between the plates. By Gauss’ Law, the density of
induced charge
- Q
s = K
o
o
o = K
s
o
s
A1
V
G
S
iO
2 Si
p type
x
o
q
m q
s
Ec
Ei
Ev
Ef
•The application of a voltage across the MOS capacitor establishes an
electric field ξ
o between the plates. By Gauss’ Law, the density of
induced charge
- Q
s = K
o
o
o = K
s
o
s
A1
V
G
S
iO
2 Si
p type
x
o
q
m q
s
Ec
Ei
Ev
Ef
•Where
o
= free space permitivity
K
o = dielectric constant of oxide
s = field at semiconductor surface.
K
s = dielectric constant of semiconductor.
•The voltage applied at the gate V
G equals the potential
drop across the oxide layer and the surface potential
s
.
V
G
= V
o
+
s
•According to voltage applied on the gate terminal, MOS
device operates in three different modes.
IDEALIZED MOS STRUCTRE
o
= free space permitivity
K
o = dielectric constant of oxide
s = field at semiconductor surface.
K
s = dielectric constant of semiconductor.
•The voltage applied at the gate V
G equals the potential
drop across the oxide layer and the surface potential
s
.
V
G
= V
o
+
s
•According to voltage applied on the gate terminal, MOS
device operates in three different modes.
IDEALIZED MOS STRUCTRE
CARRIER ACCUMULATION
•When a small negative voltage is applied on the gate. The
minority carriers present in the bulk gets attracted towards
the gate terminal. The surface charge density below the
silicon surface is greater than the equilibrium-carrier
density in the bulk.
E
fm
E
C
Ei
E
F
E
V
V
G<0
-Q
s
Q
s
Energy Band Diagram
Charge Distribution
•When a small negative voltage is applied on the gate. The
minority carriers present in the bulk gets attracted towards
the gate terminal. The surface charge density below the
silicon surface is greater than the equilibrium-carrier
density in the bulk.
E
fm
E
C
Ei
E
F
E
V
V
G<0
-Q
s
Q
s
Energy Band Diagram
Charge Distribution
CARRIER DEPLETION
•When a small positive VG is applied, the surface potential
is positive and the energy bands bends downward. It
indicates that the holes are depleted, thus establishing a
space charge region consisting of stationery acceptor ions.
E
C
E
i
E
f
E
V
V
G
>0
E
fm
Q
s x
d
•When a small positive VG is applied, the surface potential
is positive and the energy bands bends downward. It
indicates that the holes are depleted, thus establishing a
space charge region consisting of stationery acceptor ions.
E
C
E
i
E
f
E
V
V
G
>0
E
fm
Q
s x
d
CARRIER INVERSION
•If a large positive V
G
is applied, the downward band
bending will cause the mid gap energy Ei to cross over the
constant Fermi-Level at or near the silicon surface. When
this happens an inversion layer is formed in which the
electron density is greater than the hole density.
–The surface is inverted as soon as Ef becomes greater
than Ei. If the density of electrons in the surface is less
than the density of holes in the bulk then the inversion
is called weak inversion.
–When the electron density per unit volume at the
surface becomes equal to the hole density in the bulk
then it is called strong inversion.
•If a large positive V
G
is applied, the downward band
bending will cause the mid gap energy Ei to cross over the
constant Fermi-Level at or near the silicon surface. When
this happens an inversion layer is formed in which the
electron density is greater than the hole density.
–The surface is inverted as soon as Ef becomes greater
than Ei. If the density of electrons in the surface is less
than the density of holes in the bulk then the inversion
is called weak inversion.
–When the electron density per unit volume at the
surface becomes equal to the hole density in the bulk
then it is called strong inversion.
CARRIER INVERSION
–The mid gap potential should be below Ef at the surface
by ask much as it is above Ef in the bulk.
E
C
E
i
E
F
E
V+V
G
E
fm
q
s
Large
Q
s x
dm
x
I
0
x
–The mid gap potential should be below Ef at the surface
by ask much as it is above Ef in the bulk.
E
C
E
i
E
F
E
V+V
G
E
fm
q
s
Large
Q
s x
dm
x
I
0
x
MOS CAPACITANCE
•ACCUMULATION
–C
o = (
sio
2
o / t
ox)A,
•Where
–A = area of gate
sio
2
o= dielectric constant (or relative permittivity
of SiO
2
, taken as 3.9).
o = permittivity of free space
gate
tox
gate
C
o
p-substrate
+ + + + + + + + + +
+
+ +
+
V
g<0
•ACCUMULATION
–C
o = (
sio
2
o / t
ox)A,
•Where
–A = area of gate
sio
2
o= dielectric constant (or relative permittivity
of SiO
2
, taken as 3.9).
o = permittivity of free space
gate
tox
gate
C
o
p-substrate
+ + + + + + + + + +
+
+ +
+
V
g<0
MOS CAPACITANCE
•Depletion region
–C
gb = C
o.C
dep / (C
o+C
dep)
•Where
–C
dep = (
o
si / d)A,
d = depletion layer with
gate
tox
gate
C
o
p-substrate
+
+ +
+
V
g
=0
C
dep
depletion layer
+
+
+
d
•Depletion region
–C
gb = C
o.C
dep / (C
o+C
dep)
•Where
–C
dep = (
o
si / d)A,
d = depletion layer with
gate
tox
gate
C
o
p-substrate
+
+ +
+
V
g
=0
C
dep
depletion layer
+
+
+
d
MOS CAPACITANCE
•Inversion region
C
gb = C
o; low frequency (<100 Hz)
Cgb = C
o.C
dep / (C
o+C
dep) = C
min, high frequency
+ + + + + + + + + + + + +
gate
tox
gate
C
o
p-substrate
+
+ +
+
V
g
=0
C
dep
depletion layer d
channel
•Inversion region
C
gb = C
o; low frequency (<100 Hz)
Cgb = C
o.C
dep / (C
o+C
dep) = C
min, high frequency
+ + + + + + + + + + + + +
gate
tox
gate
C
o
p-substrate
+
+ +
+
V
g
=0
C
dep
depletion layer d
channel
STRUCTURE OF MOS TRANSISTOR
•N-channel enhancement-type
oxide
Channel
Width (W)
S
gate
d
Source
(n
+
)
Drain (n
+
)Channel length (L)
Substrate (p-Si)
B
•N-channel enhancement-type
oxide
Channel
Width (W)
S
gate
d
Source
(n
+
)
Drain (n
+
)Channel length (L)
Substrate (p-Si)
B
NMOS TRANSISTOR
•Four terminal device consists of p-type substrate two n+
diffusion regions.
•Surface of the substrate region between the drain and the
source is covered with a thin oxide layer.
•A metal or polysilicon gate is deposited on top of this
dielectric oxide layer
D
G
S
B
D
G
S
D
G
S
•Four terminal device consists of p-type substrate two n+
diffusion regions.
•Surface of the substrate region between the drain and the
source is covered with a thin oxide layer.
•A metal or polysilicon gate is deposited on top of this
dielectric oxide layer
D
G
S
B
D
G
S
D
G
S
•The principle of operation of the device is as follows :
–Control the current conduction between the source and the
drain, using the electric field generated by gate voltage as a
control variable.
•Current flow in the channel is also controlled by the drain to
source voltage and by the substrate voltage, the current can
be considered as a function of these variables also.
•Channel of the device passes through all regions viz.
accumulation, depletion and inversion. The inversion region
is caused as soon as surface potential in the channel region
reaches -
Fp, and a conducting n-type layer is created
between the source and drain diffusion regions.
•It allows current flow as long as there is a potential
difference between the source and the drain terminal
voltages.
–Control the current conduction between the source and the
drain, using the electric field generated by gate voltage as a
control variable.
•Current flow in the channel is also controlled by the drain to
source voltage and by the substrate voltage, the current can
be considered as a function of these variables also.
•Channel of the device passes through all regions viz.
accumulation, depletion and inversion. The inversion region
is caused as soon as surface potential in the channel region
reaches -
Fp, and a conducting n-type layer is created
between the source and drain diffusion regions.
•It allows current flow as long as there is a potential
difference between the source and the drain terminal
voltages.
CALCULATION OF THRESHOLD VOLTAGE
•Considering the ideal case
•Threshold voltage is the voltage required to create a strong
inversion channel in the device. In the ideal case its given
by :
V
TO
= Voltage required to create a strong inversion +
the voltage drop across the oxide.
V
TO
= V
o
+
s
•We know the surface charge is twice the Fermi potential
when strong inversion occurs.
V
TO = Vo + 2
F
•Thus V
GS > V
TO
•Considering the ideal case
•Threshold voltage is the voltage required to create a strong
inversion channel in the device. In the ideal case its given
by :
V
TO
= Voltage required to create a strong inversion +
the voltage drop across the oxide.
V
TO
= V
o
+
s
•We know the surface charge is twice the Fermi potential
when strong inversion occurs.
V
TO = Vo + 2
F
•Thus V
GS > V
TO
THRESHOLD VOLTAGE
•Vo is the potential across the oxide,
V
O =
od = |Q
s|d /
ox = |Q
s| / C
o
Where
o
is the field in the oxide
Qs is the charge per unit area in the semiconductor
C
o
is the capacitance per unit area in the oxide.
We know that Qs = qN
AW
m.
Thus V
TO can be rewritten as V
T = qN
AW
m/ C
o + 2
F
Above equation gives the metal plate voltage at the on set
of strong inversion and is called the threshold voltage.
•Vo is the potential across the oxide,
V
O =
od = |Q
s|d /
ox = |Q
s| / C
o
Where
o
is the field in the oxide
Qs is the charge per unit area in the semiconductor
C
o
is the capacitance per unit area in the oxide.
We know that Qs = qN
AW
m.
Thus V
TO can be rewritten as V
T = qN
AW
m/ C
o + 2
F
Above equation gives the metal plate voltage at the on set
of strong inversion and is called the threshold voltage.
Practical situation
•The following omissions were made in the previous
discussions
–The work function difference between the gate and channel.
–The gate voltage component to change the surface potential.
–The gate voltage component to off set the depletion region
charge.
–The voltage component required to off set the fixed charges
in the gate oxide and in the silicon-silicon oxide interface.
Analysis will be carried out for n-channel device but the results
are application for p-channel device with slide difference
•The following omissions were made in the previous
discussions
–The work function difference between the gate and channel.
–The gate voltage component to change the surface potential.
–The gate voltage component to off set the depletion region
charge.
–The voltage component required to off set the fixed charges
in the gate oxide and in the silicon-silicon oxide interface.
Analysis will be carried out for n-channel device but the results
are application for p-channel device with slide difference
Work function difference
–Work function difference of the metal semiconductor
interface is given by
ms
=
m
-
s
–Almost equal to the contact potential developed.
Charges in the Oxide and Surface States
–An oxide fixed charge exists very close to the oxide
semiconductor interface due to the mechanisms of
oxide formation at the time such formation is
completed. This charge is found to be rather
independent of oxide thickness, doping type (n or p),
and doping concentration
–Work function difference of the metal semiconductor
interface is given by
ms
=
m
-
s
–Almost equal to the contact potential developed.
Charges in the Oxide and Surface States
–An oxide fixed charge exists very close to the oxide
semiconductor interface due to the mechanisms of
oxide formation at the time such formation is
completed. This charge is found to be rather
independent of oxide thickness, doping type (n or p),
and doping concentration
–An oxide trapped charge can exist throughout the
oxide, but usually close to either of its interfaces to the
substrate or the gate. This charge can be acquired
through radiation, photo-emission, or the injection of
high energy carriers from the substrate.
–A mobile ionic charge can exist within the oxide due to
contamination by alkali ions (often sodium) introduced
by the environment. This charge can move within the
oxide under the presence of an electric field.
–An interface trap charge (also called fast surface state
charge) exists at the oxide semiconductor interface. It
is caused by defects at that interface, which give rise to
charge “traps”; these can exchange mobile carriers with
the semiconductor, acting as donors or acceptors.
oxide, but usually close to either of its interfaces to the
substrate or the gate. This charge can be acquired
through radiation, photo-emission, or the injection of
high energy carriers from the substrate.
–A mobile ionic charge can exist within the oxide due to
contamination by alkali ions (often sodium) introduced
by the environment. This charge can move within the
oxide under the presence of an electric field.
–An interface trap charge (also called fast surface state
charge) exists at the oxide semiconductor interface. It
is caused by defects at that interface, which give rise to
charge “traps”; these can exchange mobile carriers with
the semiconductor, acting as donors or acceptors.
•The total charge which exists across the oxide is
Q
o
= Q
M
/ C
ox
+ Q
IT
/ C
ox
+ Q
T
/ C
ox
+ Q
F
/ C
ox
= (Q
M + Q
IT + Q
T + Q
F) / C
OX
+++ ++
Na+
K
+
Mobile ionic charge, Q
M
+++
Oxide trapped charge (Q
T
)
Fixed Oxide Charge (Q
F
)
x x xx
Interface trapped charge (Q
IT
)
Q
o
= Q
M
/ C
ox
+ Q
IT
/ C
ox
+ Q
T
/ C
ox
+ Q
F
/ C
ox
= (Q
M + Q
IT + Q
T + Q
F) / C
OX
+++ ++
Na+
K
+
Mobile ionic charge, Q
M
+++
Oxide trapped charge (Q
T
)
Fixed Oxide Charge (Q
F
)
x x xx
Interface trapped charge (Q
IT
)
FLAT BAND VOLTAGE
•Is the voltage required to keep the semiconductor every
where neutral by canceling effects of contact potentials
and oxide charges.
–The total oxide charge or the potential drop across the
oxide is given by
ox = -Q
o / C
ox
–Oxide capacitance per unit area is given by C
ox
=
ox
/ d
ox
d
ox - thickness of the insulator.
ox
- permitivity of the insulator.
Thus flat band voltage is given by
V
FB =
ms - Q
o / C
ox
•Is the voltage required to keep the semiconductor every
where neutral by canceling effects of contact potentials
and oxide charges.
–The total oxide charge or the potential drop across the
oxide is given by
ox = -Q
o / C
ox
–Oxide capacitance per unit area is given by C
ox
=
ox
/ d
ox
d
ox - thickness of the insulator.
ox
- permitivity of the insulator.
Thus flat band voltage is given by
V
FB =
ms - Q
o / C
ox
•Threshold Voltage considering all the existing charges and
work function difference between the materials used as
gate and substrate is given by
V
T
= qN
A
W / C
ox
+ V
FB
+ 2
F
•For reliable operation of devices a critical control over the
threshold voltage is necessary. Threshold voltage can be
controlled by
–By varying the oxide thickness
–By Ion implantation in the channel region
work function difference between the materials used as
gate and substrate is given by
V
T
= qN
A
W / C
ox
+ V
FB
+ 2
F
•For reliable operation of devices a critical control over the
threshold voltage is necessary. Threshold voltage can be
controlled by
–By varying the oxide thickness
–By Ion implantation in the channel region
MOSFET OPERATION
Electrons in an NMOS Transistor enter the structure
through the source contact, leave through the drain and are
subject to the control of the gate voltage.
•Cutoff Region
–When V
GS < V
T and V
DS = 0, where the current flow is
essentially zero, since the source and drain regions are
effectively insulated from each other by the two reverse
biased PN junctions.
–I
ds ~ 0
•Linear Region
–V
GS > V
T (weak inversion layer is formed)
–V
DS
> 0
Electrons in an NMOS Transistor enter the structure
through the source contact, leave through the drain and are
subject to the control of the gate voltage.
•Cutoff Region
–When V
GS < V
T and V
DS = 0, where the current flow is
essentially zero, since the source and drain regions are
effectively insulated from each other by the two reverse
biased PN junctions.
–I
ds ~ 0
•Linear Region
–V
GS > V
T (weak inversion layer is formed)
–V
DS
> 0
•A drain current proportional to V
DS
will flow from source to drain
through the conducting channel. The current flow in the linear region
is dependent on gate and drain voltage. Thus in linear region the
device acts as a voltage controlled resistor.
I
ds = [(V
gs- V
t) V
ds - V
ds
2
/2] 0<V
ds < V
gs - V
t
Source
(n
+
)
Drain (n
+
)
Substrate (p-Si)
V
B
Oxide
V
S=0
V
D
small
Channel
Depletion Region
I
D
V
G
>V
T
DS
will flow from source to drain
through the conducting channel. The current flow in the linear region
is dependent on gate and drain voltage. Thus in linear region the
device acts as a voltage controlled resistor.
I
ds = [(V
gs- V
t) V
ds - V
ds
2
/2] 0<V
ds < V
gs - V
t
Source
(n
+
)
Drain (n
+
)
Substrate (p-Si)
V
B
Oxide
V
S=0
V
D
small
Channel
Depletion Region
I
D
V
G
>V
T
•Saturation Region
–If V
DS > V
gs-V
t, the channel no longer reaches the drain. In this case
conduction is brought about by a drift mechanism due to the positive
drain voltage. This condition is called the saturation state in which
the channel current is controlled by the gate voltage and is
independent of drain voltage. The drain current is given by
I
ds
= [(V
gs
- V
t
)
2
/2 , 0<V
gs
- V
t
< V
ds
–Where is a MOS transistor gain factor given by
= /t
ox
(W/L)
Saturation Region
Linear region
I
ds
V
ds
V
GS1
V
GS2
V
GS3
–If V
DS > V
gs-V
t, the channel no longer reaches the drain. In this case
conduction is brought about by a drift mechanism due to the positive
drain voltage. This condition is called the saturation state in which
the channel current is controlled by the gate voltage and is
independent of drain voltage. The drain current is given by
I
ds
= [(V
gs
- V
t
)
2
/2 , 0<V
gs
- V
t
< V
ds
–Where is a MOS transistor gain factor given by
= /t
ox
(W/L)
Saturation Region
Linear region
I
ds
V
ds
V
GS1
V
GS2
V
GS3
CONDUCTION CHARACTERISTICS
Vtn0
Drain
Current
(I
ds)
N channel enhancement
-Vtn0
Drain
Current
(I
ds)
N channel depletion
(Vgs)
0-Vtp
P channel enhancement
0
P channel depletion
Vtp
(Vgs)
(-Vgs)(-Vgs)
Drain
Current
(I
ds)
Drain
Current
(I
ds)
Vtn0
Drain
Current
(I
ds)
N channel enhancement
-Vtn0
Drain
Current
(I
ds)
N channel depletion
(Vgs)
0-Vtp
P channel enhancement
0
P channel depletion
Vtp
(Vgs)
(-Vgs)(-Vgs)
Drain
Current
(I
ds)
Drain
Current
(I
ds)
•Body Effect
–Till the discussions we have assumed that the source to
substrate voltage is zero, but in practical devices the
source to substrate voltage of devices may not be equal
to zero. As a substrate bias Vsb is increased, the width
of the channel substrate depletion layer also increases.
This inturn will increase the density of the trapped
carriers in the depletion layer. Vsb gets added to the
substrate junction potential. This increases the gate
channel voltage drop, thus reducing the drain current.
–In modeling the MOS device the effect of body effect is
described by a parameter which is the body effect co-
efficient.
= 2q.N
A
. si / C
ox
–Till the discussions we have assumed that the source to
substrate voltage is zero, but in practical devices the
source to substrate voltage of devices may not be equal
to zero. As a substrate bias Vsb is increased, the width
of the channel substrate depletion layer also increases.
This inturn will increase the density of the trapped
carriers in the depletion layer. Vsb gets added to the
substrate junction potential. This increases the gate
channel voltage drop, thus reducing the drain current.
–In modeling the MOS device the effect of body effect is
described by a parameter which is the body effect co-
efficient.
= 2q.N
A
. si / C
ox
EFFECT ON THRESHOLD VOLTAGE
•The threshold voltage VT is not constant with respect to the
voltage between the substrate and the source of the
transistor. This is known as substrate bias effect or body
effect. The threshold voltage equation will be modified to
accommodate the changes in substrate bias as
V
TB = V
FB + 2
F + 2
SiqN
A(2
F+|V
SB|) / C
ox
= V
T
+ [ (2
F
+ |VSB|) - 2
F
where V
SB is a substrate bias and V
T is the threshold voltage
when the substrate bias is 0.
•The threshold voltage VT is not constant with respect to the
voltage between the substrate and the source of the
transistor. This is known as substrate bias effect or body
effect. The threshold voltage equation will be modified to
accommodate the changes in substrate bias as
V
TB = V
FB + 2
F + 2
SiqN
A(2
F+|V
SB|) / C
ox
= V
T
+ [ (2
F
+ |VSB|) - 2
F
where V
SB is a substrate bias and V
T is the threshold voltage
when the substrate bias is 0.
•The Sub-threshold region
When the gate voltage is below the threshold voltage
and the semiconductor surface is only weakly inverted,
the corresponding drain current is called sub threshold
current.
–Important when the MOS device is used as a low
voltage low power device.
–Drain current is dominated by diffusion instead of drift
10
-12
10
-10
10
-8
10
-6
10
-4
-0.4-0.6 -0.2 0.20.40 0.6
When the gate voltage is below the threshold voltage
and the semiconductor surface is only weakly inverted,
the corresponding drain current is called sub threshold
current.
–Important when the MOS device is used as a low
voltage low power device.
–Drain current is dominated by diffusion instead of drift
10
-12
10
-10
10
-8
10
-6
10
-4
-0.4-0.6 -0.2 0.20.40 0.6
•Short Channel & Narrow Channel Effects
–Channel Length Modulation
–Velocity Saturation
–Drain Induced Barrier Lowering
–Channel Length Modulation
–Velocity Saturation
–Drain Induced Barrier Lowering
•CHANNEL LENGTH MODULATION
–When a MOS device saturation the effective channel
length will reduce to L
eff
= L-L
short
The reduction in channel length increases the W/L ratio,
thus increasing as a drain voltage increases
Since the drain current is inversely proportional to the
electrical channel length,
I
D 1 / L-L
short= 1 / L(1+L
short / L), four small pinch of
regions
L
short / L = V
D
where is the channel link modulation parameter.
–When a MOS device saturation the effective channel
length will reduce to L
eff
= L-L
short
The reduction in channel length increases the W/L ratio,
thus increasing as a drain voltage increases
Since the drain current is inversely proportional to the
electrical channel length,
I
D 1 / L-L
short= 1 / L(1+L
short / L), four small pinch of
regions
L
short / L = V
D
where is the channel link modulation parameter.
This is achieved by implanting an anti punch through layer
through out the channel or by a localized implant in the
source drain regions.
•Threshold voltage roll-off
–for the discussions till now we have assume that the
charges contained in the surface depletion region of the
substrate are induced solely from the field created by
gate voltage. As the channel length is reduced, the
fields originating from the source drain regions may
influence the charge distribution.
–When the device is operating in the linear region, the
depletion region width for the drain and source will
become almost equal.
through out the channel or by a localized implant in the
source drain regions.
•Threshold voltage roll-off
–for the discussions till now we have assume that the
charges contained in the surface depletion region of the
substrate are induced solely from the field created by
gate voltage. As the channel length is reduced, the
fields originating from the source drain regions may
influence the charge distribution.
–When the device is operating in the linear region, the
depletion region width for the drain and source will
become almost equal.
–The channel depletion region over laps the source and
drain depletion regions.
–Thus the threshold voltage becomes less positive for
the n MOS and less negative for the p channel
V
S
V
G
V
D
W
m
n+ n+
L
r
j
L
drain depletion regions.
–Thus the threshold voltage becomes less positive for
the n MOS and less negative for the p channel
V
S
V
G
V
D
W
m
n+ n+
L
r
j
L
Drain Induced Barrier Lowering
•When the drain voltage of a short channel MOSFET
increases from linear region to saturation region, its
threshold voltage roll-off will become larger. This is
called drain induced barrier lowering.
S G D
n+n+
p
•When the drain voltage of a short channel MOSFET
increases from linear region to saturation region, its
threshold voltage roll-off will become larger. This is
called drain induced barrier lowering.
S G D
n+n+
p
•As the drain biased is increased, the conduction band edge
in the drain is pulled down and the drain channel depletion
with increases. The source channel potential barrier is
lowered. This effect is known as DIBL.
•The drain depletion region expands and merge with the
source depletion region and cause heavy current flow in
between the electrons. It should be kept in mind that
DIBL is caused by the lowering of the source junction
potential barrier below the built in potential.
•Solutions
–Source drain junctions must be made shallow as the
length of the channel reduces.
–Channel doping must be sufficiently high to prevent the
drain from being able to control the source junction.
in the drain is pulled down and the drain channel depletion
with increases. The source channel potential barrier is
lowered. This effect is known as DIBL.
•The drain depletion region expands and merge with the
source depletion region and cause heavy current flow in
between the electrons. It should be kept in mind that
DIBL is caused by the lowering of the source junction
potential barrier below the built in potential.
•Solutions
–Source drain junctions must be made shallow as the
length of the channel reduces.
–Channel doping must be sufficiently high to prevent the
drain from being able to control the source junction.
•Bulk Punch Through
Drain induced barrier lowering causes the formation of a
leakage path at SiO2 - Si interface. If the drain voltage is
large enough, significant leakage current may flow from
drain to source via the bulk.As the length of the channel is
less,depletion region of the drain merges with source
depletion region when drain voltage is increased.the gate
will lose control over the the device and will be unable to
turn off the device completely and the drain current will
become independent of gate voltage.
Drain induced barrier lowering causes the formation of a
leakage path at SiO2 - Si interface. If the drain voltage is
large enough, significant leakage current may flow from
drain to source via the bulk.As the length of the channel is
less,depletion region of the drain merges with source
depletion region when drain voltage is increased.the gate
will lose control over the the device and will be unable to
turn off the device completely and the drain current will
become independent of gate voltage.
Velocity Saturation
•The lateral electric field alongwith channel increases as the
effective channel length is decreased. While the electron
drift velocity in the channel is proportional to the electric
field for lower field values, the velocity tends to saturate at
high electric fields. For electric fields above 10
5
v/cm, the
electron drift velocity in the channel reaches a saturation
value of above 10
7
cm / sec.
•Effects
–Reduces the saturation mode current.
–The current is no longer a function of gate to source
voltage and is independent of channel link.
•The lateral electric field alongwith channel increases as the
effective channel length is decreased. While the electron
drift velocity in the channel is proportional to the electric
field for lower field values, the velocity tends to saturate at
high electric fields. For electric fields above 10
5
v/cm, the
electron drift velocity in the channel reaches a saturation
value of above 10
7
cm / sec.
•Effects
–Reduces the saturation mode current.
–The current is no longer a function of gate to source
voltage and is independent of channel link.
•Other scaling effects
–Fowler Nordheim Tunneling
When the gate oxide is very thin, a current can flow from
the gate to source or drain by electron tunneling
through the gate oxide.
I
FN
= C
1
WLE
ox
2
e
Eox/-Eo
where Eox = V
gs
/ t
ox
This effect limits the scaling down of the gate oxide
thickness in MOS
Degrades the high input impdance.
This effect is made use in floating gates of electrically
alterable programmable logic device.
–Fowler Nordheim Tunneling
When the gate oxide is very thin, a current can flow from
the gate to source or drain by electron tunneling
through the gate oxide.
I
FN
= C
1
WLE
ox
2
e
Eox/-Eo
where Eox = V
gs
/ t
ox
This effect limits the scaling down of the gate oxide
thickness in MOS
Degrades the high input impdance.
This effect is made use in floating gates of electrically
alterable programmable logic device.
•Drain Punch Through
–When the drain is at high enough voltage with respect
to the source, the depletion region around the drain may
extend to the source, thus causing current to flow
irrespective of the gate voltage. This is known as
Punch Through condition.
–Occurs in devices with long as well as short channels.
–This effect is used in IO protection circuits to limit the
voltage across internal nodes and also in ESD
protection circuit.
–When the drain is at high enough voltage with respect
to the source, the depletion region around the drain may
extend to the source, thus causing current to flow
irrespective of the gate voltage. This is known as
Punch Through condition.
–Occurs in devices with long as well as short channels.
–This effect is used in IO protection circuits to limit the
voltage across internal nodes and also in ESD
protection circuit.
•Impact Ionization - Hot Electrons
–As the length of the gate is reduced,the electric field at
the drain in saturation increases.when the field becomes
very high,the electrons are imparted with enough
energy so that they become “hot”. These hot electrons
impact the drain,dislodging the holes that are then
swept towards the negatively charged substrate and
appear as substrate current.This effect is known as
Impact Ionization.
–Degrades threshold voltage,sub-threshold current and
transconductance.
–As the length of the gate is reduced,the electric field at
the drain in saturation increases.when the field becomes
very high,the electrons are imparted with enough
energy so that they become “hot”. These hot electrons
impact the drain,dislodging the holes that are then
swept towards the negatively charged substrate and
appear as substrate current.This effect is known as
Impact Ionization.
–Degrades threshold voltage,sub-threshold current and
transconductance.
•Mobility Degradation
Mobility of carriers in the channel is lower than in
bulk,because of scattering.This mobility degradation
increases with gate bias.
Also dependent on the drain bias or the
longitudinal electric field .The carrier drift velocity
increases linearly with electric field until saturation.After
this velocity saturation happens and thus cannot be
described with mobility.
In short channel devices,because of mobility
degradation,the saturation drain current does not increase
quadratically with VG-VT.
Mobility of carriers in the channel is lower than in
bulk,because of scattering.This mobility degradation
increases with gate bias.
Also dependent on the drain bias or the
longitudinal electric field .The carrier drift velocity
increases linearly with electric field until saturation.After
this velocity saturation happens and thus cannot be
described with mobility.
In short channel devices,because of mobility
degradation,the saturation drain current does not increase
quadratically with VG-VT.
MOSFET CAPACITANCES
•When the MOS device operates in the regions of cut-off,
linear and saturation regions, a number of parasitic
capacitances will come into existence.
gate
t
ox
drain
depletion layer
C
db
source
substrate
C
sb
C
gs
C
gb
C
gd
•When the MOS device operates in the regions of cut-off,
linear and saturation regions, a number of parasitic
capacitances will come into existence.
gate
t
ox
drain
depletion layer
C
db
source
substrate
C
sb
C
gs
C
gb
C
gd
•Cgs, Cgd = Gate to channel capacitances which are lumped
at the source and drain regions of the channel.
•Csb, Cdb = source and drain diffusion capacitances to bulk.
•Cgb = Gate to bulk capacitance.
•The total gate capacitance of the MOS device is given by Cg
= Cgb + Cgs + Cgd.
•The gate capacitance of a MOS device will vary from region
to region of operation.
–Cut-off region.
Where Vgs < V
T
, there exists no channel and hence Cgs
= Cgd = 0. Cgb can be modeled as a series combination
of the oxide capacitance and the depletion layer
capacitance.
at the source and drain regions of the channel.
•Csb, Cdb = source and drain diffusion capacitances to bulk.
•Cgb = Gate to bulk capacitance.
•The total gate capacitance of the MOS device is given by Cg
= Cgb + Cgs + Cgd.
•The gate capacitance of a MOS device will vary from region
to region of operation.
–Cut-off region.
Where Vgs < V
T
, there exists no channel and hence Cgs
= Cgd = 0. Cgb can be modeled as a series combination
of the oxide capacitance and the depletion layer
capacitance.
–Cg at off region is C
o . C
dep / C
o+C
dep
•Non Saturated Region
–Where Vgs - VT > Vds. Here the channel exists and thus
Cgs and Cgd become significant. These capacitances are
dependent on gate voltage.
Cgd = Cgs = 1/2 Co
= 1/2 (
sio2 .
0 / t
ox) . A
Cgb = 0
•Saturation Region
–Where V
gs
- V
T
< V
ds
, the channel is heavily inverted.
Cgd = 0.
o . C
dep / C
o+C
dep
•Non Saturated Region
–Where Vgs - VT > Vds. Here the channel exists and thus
Cgs and Cgd become significant. These capacitances are
dependent on gate voltage.
Cgd = Cgs = 1/2 Co
= 1/2 (
sio2 .
0 / t
ox) . A
Cgb = 0
•Saturation Region
–Where V
gs
- V
T
< V
ds
, the channel is heavily inverted.
Cgd = 0.
•The gate to source capacitance increases,
Cgs = 2/3 Co
= 2/3 (
sio2
.
0
/ t
ox
) . A
•Diffusion capacitance
–Diffusion capacitance is the capacitance of the source
and drain regions.
Poly Gate
b
Source
Diffusion
Area
Drain
Diffusion
Area
a
Source diffusion Drain diffusion
Cgs = 2/3 Co
= 2/3 (
sio2
.
0
/ t
ox
) . A
•Diffusion capacitance
–Diffusion capacitance is the capacitance of the source
and drain regions.
Poly Gate
b
Source
Diffusion
Area
Drain
Diffusion
Area
a
Source diffusion Drain diffusion
•Diffusion Capacitance
–Consist of area capacitance as well as periphery
capacitances. The total diffusion capacitance can be
estimated by
Cd = Cja (ab) + Cjp(2a+2b)
Cja = junction capacitance per
2
.
Cjp = periphery capacitance
a = width of diffusion region ()
b = length of diffusion region ()
–Consist of area capacitance as well as periphery
capacitances. The total diffusion capacitance can be
estimated by
Cd = Cja (ab) + Cjp(2a+2b)
Cja = junction capacitance per
2
.
Cjp = periphery capacitance
a = width of diffusion region ()
b = length of diffusion region ()
•Routing Capacitance
–Single Wire capacitance
Routing capacitances between metal and poly layers
and substrate can be estimated as parallel plate
capacitors. C = (/t)A
This approximation neglects the fringing fields
capacitances arising from the edges of conductor. The
effect of fringing field capacitances is that it will
increase the area of the estimation.
–Multiple Conductor Capacitances
Modern CMOS processes have multiple routing layers
and there exists parasitic interactions between these
layers
–Single Wire capacitance
Routing capacitances between metal and poly layers
and substrate can be estimated as parallel plate
capacitors. C = (/t)A
This approximation neglects the fringing fields
capacitances arising from the edges of conductor. The
effect of fringing field capacitances is that it will
increase the area of the estimation.
–Multiple Conductor Capacitances
Modern CMOS processes have multiple routing layers
and there exists parasitic interactions between these
layers
•The capacitance of the middle layer is divided into three
components.
–The line to ground capacitance.
–The line to line capacitance.
–The crossover capacitance.
C
2 = C
21 + 2C
22 + C
23
Layer 3
Layer 2
Layer 1
C
23
C
22
C
21 C
21
C
22
components.
–The line to ground capacitance.
–The line to line capacitance.
–The crossover capacitance.
C
2 = C
21 + 2C
22 + C
23
Layer 3
Layer 2
Layer 1
C
23
C
22
C
21 C
21
C
22
RESISTANCE ESTIMATION
•The resistance of a uniform slab of conducting material is
given by R = (/t) (l/w) ohms
= resistivity,t = thickness
l = conductor length,w = conductor width
It can be rewritten as R = Rs (l/w) ohms
where Rs = Sheet resistance / sq.
•Contact and Via resistance
–Contacts and Via also have resistance associated with
them and is dependent upon the contacted materials and
proportional to the area of contact. As contacts are
reduced the associated resistance increases.
•The resistance of a uniform slab of conducting material is
given by R = (/t) (l/w) ohms
= resistivity,t = thickness
l = conductor length,w = conductor width
It can be rewritten as R = Rs (l/w) ohms
where Rs = Sheet resistance / sq.
•Contact and Via resistance
–Contacts and Via also have resistance associated with
them and is dependent upon the contacted materials and
proportional to the area of contact. As contacts are
reduced the associated resistance increases.
•Distributed RC Effects
–The propagation of a signal along a wire depends upon
many factors including the distributed resistances and
capacitances, the impedance of the driving source and
the load impedance.
–The transmission line effect is very high on the poly
lines since the resistance is relatively high. A heavily
loaded metal wire also can have high RC components.
–The propagation of a signal along a wire depends upon
many factors including the distributed resistances and
capacitances, the impedance of the driving source and
the load impedance.
–The transmission line effect is very high on the poly
lines since the resistance is relatively high. A heavily
loaded metal wire also can have high RC components.
•The RC effects
–Cause rise and fall times in signals
–Causes degradation of clock
–Causes skew in global routing
–Causes degradation of signal levels
–Increases load capacitance
•For reducing the RC effects
–Reduce the length of Net
–Reduce usage of Global Buses
–Cause rise and fall times in signals
–Causes degradation of clock
–Causes skew in global routing
–Causes degradation of signal levels
–Increases load capacitance
•For reducing the RC effects
–Reduce the length of Net
–Reduce usage of Global Buses
•Inductance
–Normally the on-chip inductances are very small, but
the bond wire inductance can cause undesirable effects
in large high speed I/O buffers. The on-chip
inductance mainly arise from conducting wires running
through the chip.
–Can cause inductive spike when a large current is
drawn through a wire in a short period of time. In high
speed design it is important for power supply
connections to keep the inductance level where a
change in voltage does not disturb the performance of
the chip.
–Power and ground bounces in devices are mainly
caused due to inductive spike
–Normally the on-chip inductances are very small, but
the bond wire inductance can cause undesirable effects
in large high speed I/O buffers. The on-chip
inductance mainly arise from conducting wires running
through the chip.
–Can cause inductive spike when a large current is
drawn through a wire in a short period of time. In high
speed design it is important for power supply
connections to keep the inductance level where a
change in voltage does not disturb the performance of
the chip.
–Power and ground bounces in devices are mainly
caused due to inductive spike
CMOS INVERTER
•DC characteristics
–The simple and basic logic device is formed by the
series connection of a n MOS and a p MOS transistor.
V
DD
s
g
P-deviced
d
N-device
Vout
Vin
g
s
b
b
•DC characteristics
–The simple and basic logic device is formed by the
series connection of a n MOS and a p MOS transistor.
V
DD
s
g
P-deviced
d
N-device
Vout
Vin
g
s
b
b
•Transfer characteristics
–Output voltage V
out
as a function of the inverter, V
in
.
Vtn
0.5 V
DD
V
DD
+ V
TP
V
DD
A
B
C
D
E
0.5 V
DD
Vinp
Idsn || Idsp
Vinn
Vdsn (V
DD-Vdsp)
–Output voltage V
out
as a function of the inverter, V
in
.
Vtn
0.5 V
DD
V
DD
+ V
TP
V
DD
A
B
C
D
E
0.5 V
DD
Vinp
Idsn || Idsp
Vinn
Vdsn (V
DD-Vdsp)
CMOS INVERTER
When the input is high,the n device conducts and pulls
down the output ,while the p MOS transistor acts as the
load. For low input the p MOS transistor drives or pulls
up the output node while the n MOS acts as the load.
Pull Down OutputPull Up OutputCombined Output
0 Z 0
Z 1 1
Z Z Z
0 1 Crow-Barred
When the input is high,the n device conducts and pulls
down the output ,while the p MOS transistor acts as the
load. For low input the p MOS transistor drives or pulls
up the output node while the n MOS acts as the load.
Pull Down OutputPull Up OutputCombined Output
0 Z 0
Z 1 1
Z Z Z
0 1 Crow-Barred
•The operation of CMOS inverter can be divided into five
regions.The behavior of n and p devices differ in each
region of operation
•Region A.
This region is defined by 0< V
in < V
tn in which the n
device is cut off and the p device in linear region. Since
I
dsn = -I
dsp, the drain to source current of p devices is also
zero. But for V
dsp
= V
out
- V
DD
, with V
dsp
= 0, the output
voltage is V
out
= V
DD
•Region B.
This region is characterized by V
tn
< V
in
< V
DD
/2 in which
the p-device is in its nonsaturated region (V
ds
=! 0) while
the n-device is in saturation.
OPERATION OF INVERTER
regions.The behavior of n and p devices differ in each
region of operation
•Region A.
This region is defined by 0< V
in < V
tn in which the n
device is cut off and the p device in linear region. Since
I
dsn = -I
dsp, the drain to source current of p devices is also
zero. But for V
dsp
= V
out
- V
DD
, with V
dsp
= 0, the output
voltage is V
out
= V
DD
•Region B.
This region is characterized by V
tn
< V
in
< V
DD
/2 in which
the p-device is in its nonsaturated region (V
ds
=! 0) while
the n-device is in saturation.
OPERATION OF INVERTER
•The saturation current I
dsn
for the n-device is obtained by
setting V
gs = V
in. This results in
I
dsn
=
n
(V
in
- V
tn
)
2
/2
• The current for the p-device can be obtained by
V
gs = (V
in - V
DD) andV
ds = (V
out - V
DD)
•Equivalent circuit for the inverter in region B is
Region B
Vout
I
dsn
I
dsp
dsn
for the n-device is obtained by
setting V
gs = V
in. This results in
I
dsn
=
n
(V
in
- V
tn
)
2
/2
• The current for the p-device can be obtained by
V
gs = (V
in - V
DD) andV
ds = (V
out - V
DD)
•Equivalent circuit for the inverter in region B is
Region B
Vout
I
dsn
I
dsp
•Region C
–In this region both the devices are in saturation.
I
dsp
= -
p
/2 (V
in
- V
DD
- V
tp
)
2
I
dsn
=
n
/2 (V
in
- V
tn
)
2
With I
dsp
= -I
dsn
Reducing we get V
in = V
DD / 2
The significant factor to be noted is that in region C we
have two current sources in series,which is an unstable
condition. Thus a small input voltage has a large effect on
the output. This makes the output transition very steep.
This region also defines the gain of the CMOS inverter
when used as a small signal amplifier.
–In this region both the devices are in saturation.
I
dsp
= -
p
/2 (V
in
- V
DD
- V
tp
)
2
I
dsn
=
n
/2 (V
in
- V
tn
)
2
With I
dsp
= -I
dsn
Reducing we get V
in = V
DD / 2
The significant factor to be noted is that in region C we
have two current sources in series,which is an unstable
condition. Thus a small input voltage has a large effect on
the output. This makes the output transition very steep.
This region also defines the gain of the CMOS inverter
when used as a small signal amplifier.
•Equivalent circuit of the CMOS inverter in the region C is
Region C
Vout
I
dsn
I
dsp
•Region D
– This region is described by V
DD/2 < V
in < V
DD + V
tp
I
dsp
= - 1/2
p
(V
in
- V
DD
- V
tp
)
2
and I
dsn
=
n
[ (V
in
- V
tn
) Vout - (V
out
2
/ 2)]
Region D
Vout
I
dsn
I
dsp
Region C
Vout
I
dsn
I
dsp
•Region D
– This region is described by V
DD/2 < V
in < V
DD + V
tp
I
dsp
= - 1/2
p
(V
in
- V
DD
- V
tp
)
2
and I
dsn
=
n
[ (V
in
- V
tn
) Vout - (V
out
2
/ 2)]
Region D
Vout
I
dsn
I
dsp
•Region E
–This region is defined by the input condition V
in > V
DD -
V
tp, in which the P device is in cut off and the n device is
in the linear mode. Here V
gsp = V
in - V
DD, which is more
positive than V
tp
. The output in this region V
out
= 0. This
characteristic is very important since the noise immunity is
maximized
n
/
p
Ratio
–For a given process if we want to change the gain
characteristics, we need to change the channel dimensions.
For a CMOS inverter
n /
p = 1 is desirable since it allows
a capacitive load to charge and discharge in equal times by
providing equal current source and current sink
capabilities.
–This region is defined by the input condition V
in > V
DD -
V
tp, in which the P device is in cut off and the n device is
in the linear mode. Here V
gsp = V
in - V
DD, which is more
positive than V
tp
. The output in this region V
out
= 0. This
characteristic is very important since the noise immunity is
maximized
n
/
p
Ratio
–For a given process if we want to change the gain
characteristics, we need to change the channel dimensions.
For a CMOS inverter
n /
p = 1 is desirable since it allows
a capacitive load to charge and discharge in equal times by
providing equal current source and current sink
capabilities.
•Noise margin
–Noise margin is a critical parameter related to the input
output voltage characteristics of the device. This
parameter allows us to determine the allowable noise
voltage on the input of a gate so that the output will not
be effected.
N
ML
= |V
ILmax
- V
OLmax
|
N
MH
= |V
OHmin
- V
IHmin
|
–It is important that if either N
ML
or N
MH
of a device is
reduced (~ 0.1 V
DD
), then the device may be susceptible
to switching noise that may be present on the inputs.
Quite often noise margins are compromised to improve
the speed.
–Noise margin is a critical parameter related to the input
output voltage characteristics of the device. This
parameter allows us to determine the allowable noise
voltage on the input of a gate so that the output will not
be effected.
N
ML
= |V
ILmax
- V
OLmax
|
N
MH
= |V
OHmin
- V
IHmin
|
–It is important that if either N
ML
or N
MH
of a device is
reduced (~ 0.1 V
DD
), then the device may be susceptible
to switching noise that may be present on the inputs.
Quite often noise margins are compromised to improve
the speed.
SWITCHING CAHRACTERISTICS
•The switching speed of a CMOS device is limited by the
time taken to charge and discharge the load capacitance. An
input transition results in an output transition that either
charges C
L
towards V
DD
or discharges C
L
towards V
SS
.
C
L
V
out
V
in
t
f t
r
10%
50%
90%
•The switching speed of a CMOS device is limited by the
time taken to charge and discharge the load capacitance. An
input transition results in an output transition that either
charges C
L
towards V
DD
or discharges C
L
towards V
SS
.
C
L
V
out
V
in
t
f t
r
10%
50%
90%
•Rise Time, t
r
–Time for a waveform to rise from 10% to 90% of its
steady-state value.
•Fall time, t
f
–Time for a waveform to fall from 90% to 10% of its
steady state value.
•Delay time, t
d
–Time difference between input transition (50%) and the
50% output level. This is the time taken for a logic
transition to pass from input to output.
r
–Time for a waveform to rise from 10% to 90% of its
steady-state value.
•Fall time, t
f
–Time for a waveform to fall from 90% to 10% of its
steady state value.
•Delay time, t
d
–Time difference between input transition (50%) and the
50% output level. This is the time taken for a logic
transition to pass from input to output.
•Fall Time
– The capacitive load in the CMOS inverter consists of
the input capacitance of the next gates, output of the
gate in discussion and the routing capacitance.
x3
I
ds
V
out
(t)
V
ds
= V
gs
- V
t
x2
x1
V
DD
Initial operating point
Non-saturated
State
0
– The capacitive load in the CMOS inverter consists of
the input capacitance of the next gates, output of the
gate in discussion and the routing capacitance.
x3
I
ds
V
out
(t)
V
ds
= V
gs
- V
t
x2
x1
V
DD
Initial operating point
Non-saturated
State
0
•Figure shows the trajectory of the n-transistor operating point
as the input voltage, V
in
(t), changes from Zero volts to V
DD
.
Initially, the n device is cut off and the load capacitor, C
L
is
charged to V
DD
. Application of a step voltage (I.e. V
gs
= V
DD
)
at the input of the inverter changes the operating point to X2.
It is evident that the fall time consists of two intervals.
–t
f1
= period during which the capacitor voltage, V
out
, drops
from 0.9 V
DD to (V
DD - V
tn)
–t
f2
= period during which the capacitor voltage, V
out
, drops
from (V
DD
- V
tn
) to 0.1 V
DD
.
t
f1
= 2C
L
(V
tn
- 0.1 V
DD
) /
n
(V
DD
-V
tn
)
2
C
L
t
f2
= --------------------- ln (19-20n), with n = V
tn
/ V
DD
n V
DD(1-n)
as the input voltage, V
in
(t), changes from Zero volts to V
DD
.
Initially, the n device is cut off and the load capacitor, C
L
is
charged to V
DD
. Application of a step voltage (I.e. V
gs
= V
DD
)
at the input of the inverter changes the operating point to X2.
It is evident that the fall time consists of two intervals.
–t
f1
= period during which the capacitor voltage, V
out
, drops
from 0.9 V
DD to (V
DD - V
tn)
–t
f2
= period during which the capacitor voltage, V
out
, drops
from (V
DD
- V
tn
) to 0.1 V
DD
.
t
f1
= 2C
L
(V
tn
- 0.1 V
DD
) /
n
(V
DD
-V
tn
)
2
C
L
t
f2
= --------------------- ln (19-20n), with n = V
tn
/ V
DD
n V
DD(1-n)
•t
f
= t
f1
+ t
f2
•t
f = k (CL /
nV
DD)
•Observations
–Delay is directly proportional load capacitance.
–Delay is inversely proportional to supply voltage.
–Delay is inversely proportional to gain of the driving
transistor.
•Advantage of less fall time
–Power dissipation is low
–propagation delay is decreased
f
= t
f1
+ t
f2
•t
f = k (CL /
nV
DD)
•Observations
–Delay is directly proportional load capacitance.
–Delay is inversely proportional to supply voltage.
–Delay is inversely proportional to gain of the driving
transistor.
•Advantage of less fall time
–Power dissipation is low
–propagation delay is decreased
RISE TIME
•t
r
= 3 4 C
L
/
p
V
DD
•For equally sized n and p transistors, where
n
= 2
p
, rise
time is approximately twice the fall time.
–Thus if we want to have approximately same rise time and
fall time for an inverter we need to make
n /
p = 1
–This implies that the channel width of the p device must
be increased to approximately two or three times that of
the n device, so that W
p = 2-3 W
n.sd.
•Delay time
–In CMOS circuits the delay of a single gate is dominated
by the output rise and fall time.
t
dr = t
r / 2 andt
df = t
f / 2
•t
r
= 3 4 C
L
/
p
V
DD
•For equally sized n and p transistors, where
n
= 2
p
, rise
time is approximately twice the fall time.
–Thus if we want to have approximately same rise time and
fall time for an inverter we need to make
n /
p = 1
–This implies that the channel width of the p device must
be increased to approximately two or three times that of
the n device, so that W
p = 2-3 W
n.sd.
•Delay time
–In CMOS circuits the delay of a single gate is dominated
by the output rise and fall time.
t
dr = t
r / 2 andt
df = t
f / 2
•Gate Delays
out
In - 3
In - 2
In - 1
N3
N2
N1
P3 P2 P1
V
DD
•The effective gain of the n transistors is given by
1
neff
= ---------------------------, where
n1
=
n2
=
n3
1/
n1 + 1/
n2 + 1/
n3
out
In - 3
In - 2
In - 1
N3
N2
N1
P3 P2 P1
V
DD
•The effective gain of the n transistors is given by
1
neff
= ---------------------------, where
n1
=
n2
=
n3
1/
n1 + 1/
n2 + 1/
n3
neff
=
n
/3
•For the pull up case only one p transistor has to turn on to raise
the output. Thus,
peff
=
p
.
p = 0.3
n
•The rise time of the total device
t
r = k . C
L / 0.3
nV
DD
•The fall time of the device is tf = k . C
L
/ (
n
/3) V
DD
•Thus an approximately equal rise time and fall time has been
maintained for the proper functioning of the device.
neff
=
n
/3
•For the pull up case only one p transistor has to turn on to raise
the output. Thus,
peff
=
p
.
p = 0.3
n
•The rise time of the total device
t
r = k . C
L / 0.3
nV
DD
•The fall time of the device is tf = k . C
L
/ (
n
/3) V
DD
•Thus an approximately equal rise time and fall time has been
maintained for the proper functioning of the device.
•Switch Level RC Models
–In this model the transistors are represented as a
resistance charging or discharging through a
capacitance. In the simple RC Model the total
resistance of the pull up and pull down path is
calculated and all the capacitance of the nodes involved
in switching are lumped on the output of the gate. Thus
the fall time delay for any input is calculated as
t
df
= R
pulldown
. C
pull down path
.
–The RC delay calculation tends to pessimize the delay
because it assumes that all the internal capacitance has
to be discharged or charged to switch the gate.
–In this model the transistors are represented as a
resistance charging or discharging through a
capacitance. In the simple RC Model the total
resistance of the pull up and pull down path is
calculated and all the capacitance of the nodes involved
in switching are lumped on the output of the gate. Thus
the fall time delay for any input is calculated as
t
df
= R
pulldown
. C
pull down path
.
–The RC delay calculation tends to pessimize the delay
because it assumes that all the internal capacitance has
to be discharged or charged to switch the gate.
•Power dissipation
–The components that establish the amount of power
dissipated in a CMOS circuit are.
•Static Dissipation
•Dynamic Dissipation
•Short Circuit Power Dissipation
•Static Dissipation
–Even though only one transistor in the CMOS pair is
conducting at any moment of time, there is some small
static dissipation due to the reverse bias leakage
between the drain and source regions to the substrate.
In addition subthreshold conduction can contribute to
the said power dissipation.
–The components that establish the amount of power
dissipated in a CMOS circuit are.
•Static Dissipation
•Dynamic Dissipation
•Short Circuit Power Dissipation
•Static Dissipation
–Even though only one transistor in the CMOS pair is
conducting at any moment of time, there is some small
static dissipation due to the reverse bias leakage
between the drain and source regions to the substrate.
In addition subthreshold conduction can contribute to
the said power dissipation.
–The leakage current is described by the diode equation.
i
o = i
s exp (qV/kT - 1)
Where is = reverse saturation current
V = diode voltage
q = electronic charge ( 1.602 x 10
-19
C)
k = Boltzmann’s constant (1.38 x 10
-23
J/K)
T = temperature in Kelvin
•Static Power Dissipation is a product of the device leakage
current and supply voltage. The total static power
dissipation is
n
Ps = leakage current x supply voltage,
1
where n = number of devices
i
o = i
s exp (qV/kT - 1)
Where is = reverse saturation current
V = diode voltage
q = electronic charge ( 1.602 x 10
-19
C)
k = Boltzmann’s constant (1.38 x 10
-23
J/K)
T = temperature in Kelvin
•Static Power Dissipation is a product of the device leakage
current and supply voltage. The total static power
dissipation is
n
Ps = leakage current x supply voltage,
1
where n = number of devices
•Dynamic Dissipation
–There are two components responsible for the dynamic
power dissipation. They are
•Switching transient current
•Charging and discharging of load capacitances.
•Switching Transient Current
–When suddenly a clock or a signal switches from 1 to 0
or from 0 to 1, the electrons which are flowing in the
channel will take some time to recombine with the
ionized items. The current thus produced will
contribute to the total output which is normally very
high. This adds to the switching current.
–There are two components responsible for the dynamic
power dissipation. They are
•Switching transient current
•Charging and discharging of load capacitances.
•Switching Transient Current
–When suddenly a clock or a signal switches from 1 to 0
or from 0 to 1, the electrons which are flowing in the
channel will take some time to recombine with the
ionized items. The current thus produced will
contribute to the total output which is normally very
high. This adds to the switching current.
•Charging & Discharging of Load Capacitance
–Switching power is dissipated when energy is drawn
from the power supply to charge up the output node
capacitance. The output node typically makes a full
transition from 0 to V
DD and one half of the energy is
dissipated as heat in conducting the P MOS Transistors.
While discharging the energy stored in the output
capacitance is dissipated as heat in conducting n MOS
transistors. The total capacity load normally at the
output consists of
•Output node capacitance of the gate itself
•Total interconnect capacitance
•Input capacitance of driven gates.
–Switching power is dissipated when energy is drawn
from the power supply to charge up the output node
capacitance. The output node typically makes a full
transition from 0 to V
DD and one half of the energy is
dissipated as heat in conducting the P MOS Transistors.
While discharging the energy stored in the output
capacitance is dissipated as heat in conducting n MOS
transistors. The total capacity load normally at the
output consists of
•Output node capacitance of the gate itself
•Total interconnect capacitance
•Input capacitance of driven gates.
•The average dynamic consumption is given by
P
avg = C
load . V
DD
2
. f
CLK
•Short Circuit Dissipation
–If a CMOS device is driven by a signal which is having
finite rise and fall times, both the n device and p device
in the circuit may conduct simultaneously for a short
amount of time during switching. This will form a
direct current path between the power supply and
ground.
•The total power dissipation is given by
P
total = P
s + P
d + P
sc
P
avg = C
load . V
DD
2
. f
CLK
•Short Circuit Dissipation
–If a CMOS device is driven by a signal which is having
finite rise and fall times, both the n device and p device
in the circuit may conduct simultaneously for a short
amount of time during switching. This will form a
direct current path between the power supply and
ground.
•The total power dissipation is given by
P
total = P
s + P
d + P
sc
•Switching Power Reduction
–For reducing the power consumption in a CMOS device
the following measures are implemented.
•Reduction of power supply voltage.
•Reduction of voltage swing in all nodes.
•Reduction in the switching probability.
•Reduction of load capacitance.
–Reduction of switching activity requires a detailed
analysis of signal transition probabilities, and
implementation of various circuit level and system level
measures such as
•Logic optimization
•Use of gated clocks
•Prevention of glitches
–For reducing the power consumption in a CMOS device
the following measures are implemented.
•Reduction of power supply voltage.
•Reduction of voltage swing in all nodes.
•Reduction in the switching probability.
•Reduction of load capacitance.
–Reduction of switching activity requires a detailed
analysis of signal transition probabilities, and
implementation of various circuit level and system level
measures such as
•Logic optimization
•Use of gated clocks
•Prevention of glitches
MOS DEVICE BREAK DOWN MECHANISMS
–Jn BREAKDOWN (IN BETWEEN V
DRAIN
& V
SUB
)
–COX BREAK DOWN (IN BETWEEN V
GATE & V
SUB)
–P
UNCH THROUGH (IN BETWEEN V
DRAIN & V
SOURCE)
–HOT ELECTRON GENERATED BREAKDOWN (IN
BETWEEN V
GATE & V
DRAIN)
–SNAP BACK
–LATCH UP
–ELECTROMIGRATION
–CONTACT & VIA BURNING
–LEAKAGES [ISOLATION, INTER METAL]
–BREAKDOWN DUE TO ESD
–Jn BREAKDOWN (IN BETWEEN V
DRAIN
& V
SUB
)
–COX BREAK DOWN (IN BETWEEN V
GATE & V
SUB)
–P
UNCH THROUGH (IN BETWEEN V
DRAIN & V
SOURCE)
–HOT ELECTRON GENERATED BREAKDOWN (IN
BETWEEN V
GATE & V
DRAIN)
–SNAP BACK
–LATCH UP
–ELECTROMIGRATION
–CONTACT & VIA BURNING
–LEAKAGES [ISOLATION, INTER METAL]
–BREAKDOWN DUE TO ESD
JUNCTION BREAK DOWN
•During the operation of MOSFET, the following
breakdowns can lead to excessive current or permanent
damage to the device.
–Between V
D and Vsub :- This can happen if the voltage
between V
D
and Vsub exceed the reverse breakdown of
the diode (N+/P in this case). The diode leakage at the
N
+
N
+
V
G
Vd
Vs
Psub
Vsub
Vsat
x
•During the operation of MOSFET, the following
breakdowns can lead to excessive current or permanent
damage to the device.
–Between V
D and Vsub :- This can happen if the voltage
between V
D
and Vsub exceed the reverse breakdown of
the diode (N+/P in this case). The diode leakage at the
N
+
N
+
V
G
Vd
Vs
Psub
Vsub
Vsat
x
reverse bias of operating voltage is therefore is one of
the important parameters, which should be in the order
of FA/m2
–Between V
G
and V
D
:- This is also known as gate oxide
breakdown, even the hot electrons generated between
V
SAT
and V
D
can be attracted by V
G
and get trapped in
poly, resulting in threshold shift. All these effects are
important for reliability considerations.
–Between V
D
and V
S
:- This is the most dominant
breakdown for short channel MOSFET. This can occur
due to the following reasons.
the important parameters, which should be in the order
of FA/m2
–Between V
G
and V
D
:- This is also known as gate oxide
breakdown, even the hot electrons generated between
V
SAT
and V
D
can be attracted by V
G
and get trapped in
poly, resulting in threshold shift. All these effects are
important for reliability considerations.
–Between V
D
and V
S
:- This is the most dominant
breakdown for short channel MOSFET. This can occur
due to the following reasons.
–Assume VG = VS = 0 and the drain voltage is
increased. The depletion width of N
+
/P diode in the
drain side will increase. At a particular voltage, the
depletion associated with the drain will touch the
depletion associated with source. A huge current thus
will start to flow as there is no barrier between source
and drain. This is called punch through condition. The
drain current in this stage is independent of the gate
voltage.
–Assume the transistor is on and the MOS is operating in
the saturation region. The electron flow from the pinch
off point having a voltage V
sat to V
D is entirely due to
the field created due to the depletion width having a
potential difference (V
D-V
sat). The electrons are
increased. The depletion width of N
+
/P diode in the
drain side will increase. At a particular voltage, the
depletion associated with the drain will touch the
depletion associated with source. A huge current thus
will start to flow as there is no barrier between source
and drain. This is called punch through condition. The
drain current in this stage is independent of the gate
voltage.
–Assume the transistor is on and the MOS is operating in
the saturation region. The electron flow from the pinch
off point having a voltage V
sat to V
D is entirely due to
the field created due to the depletion width having a
potential difference (V
D-V
sat). The electrons are
–accumulated (hot electrons) in this region. If V
D
is
increased, the acceleration of the hot electrons will be
increased and secondary hole electron pairs will be
generated. Some of these electrons will add to the
drain current (Ids). Some electrons will be attracted by
the gate (V
G) and can result threshold shift. The holes
are collected by substrate (V
sub) and source (V
sb). Once
V
G-V
sat is very high, ‘Avalanche’ will take place and
the source junction will get forward biased due to the
high hole concentration. This is called snap-back.
D
is
increased, the acceleration of the hot electrons will be
increased and secondary hole electron pairs will be
generated. Some of these electrons will add to the
drain current (Ids). Some electrons will be attracted by
the gate (V
G) and can result threshold shift. The holes
are collected by substrate (V
sub) and source (V
sb). Once
V
G-V
sat is very high, ‘Avalanche’ will take place and
the source junction will get forward biased due to the
high hole concentration. This is called snap-back.
–Electro Migration :- The metal interconnect can
withstand a certain amount of current. Designers must
make sure that the current does not exceed the specified
value (current carrying capacity). The current carrying
capacity of the interconnect is decided by thickness and
width of the metal. At a particular thickness, which is
determined by process technology considerations,
current carrying capacity is specified by current/m of
width. This value is also dependant on the nature of
current (DC or pulse) flowing through the metal
interconnect. Designers need to give serious attention
to this for designing reliable circuit.
withstand a certain amount of current. Designers must
make sure that the current does not exceed the specified
value (current carrying capacity). The current carrying
capacity of the interconnect is decided by thickness and
width of the metal. At a particular thickness, which is
determined by process technology considerations,
current carrying capacity is specified by current/m of
width. This value is also dependant on the nature of
current (DC or pulse) flowing through the metal
interconnect. Designers need to give serious attention
to this for designing reliable circuit.
–Other leakages :- There are several other leakages
which can be significant if not properly taken care - off.
•Field leakage - unwanted conduction between two
independent devices,
•Inter metal leakages
•Gate - metal interconnect leakages
are some of them and need to be considered during
over all design.
•As a preventive measure for field leakage the main
methods are
–Junction isolation
–LOCOS
–Trench isolation
which can be significant if not properly taken care - off.
•Field leakage - unwanted conduction between two
independent devices,
•Inter metal leakages
•Gate - metal interconnect leakages
are some of them and need to be considered during
over all design.
•As a preventive measure for field leakage the main
methods are
–Junction isolation
–LOCOS
–Trench isolation
LATCH UP
•Physical origin of latch-up
p+ n+ n+ p+ p+ n+
outin
V
SS
V
DD
p-substrate
R
well
n-well
PNP
NPN
R
substrate
I
S
I =
PNP
NPN I
B
I
W
NPN
I
B
I
B
•Physical origin of latch-up
p+ n+ n+ p+ p+ n+
outin
V
SS
V
DD
p-substrate
R
well
n-well
PNP
NPN
R
substrate
I
S
I =
PNP
NPN I
B
I
W
NPN
I
B
I
B
•A bulk CMOS structure has inherent PNP and NPN
parasitic bipolar transistor by the substrate, the opposite
doped well and an active source/drain diffusion in either
the well and so substrate. The collector of either parasitic
transistor is connected to the base of the other, forming a
PNPN parasitic SCR (Semiconductor Controlled Rectifier)
I
DS
Holding
current
Triggering Current
Holding Voltage
Triggering Voltage
V
DD
parasitic bipolar transistor by the substrate, the opposite
doped well and an active source/drain diffusion in either
the well and so substrate. The collector of either parasitic
transistor is connected to the base of the other, forming a
PNPN parasitic SCR (Semiconductor Controlled Rectifier)
I
DS
Holding
current
Triggering Current
Holding Voltage
Triggering Voltage
V
DD
•Under certain conditions the current in the well and
substrate can cause sufficient ohmic drop, hence forward
biasing the emitter-base junctions and activating both BJT
devices. When the current gain product of the two bipolar
is sufficient to cause regeneration, the PNPN SCR can be
switched to a low impedance, high current state. This
condition is defined as latch-up; and the condition is self
sustaining after original stimulus is removed, provided the
power supplies are capable of sourcing the excess current.
Latch up when it occurs in CMOS, can result in momentary
or permanent loss of circuit function.
•CONDITION FOR LATCH UP IS
NPN
PNP > 1
substrate can cause sufficient ohmic drop, hence forward
biasing the emitter-base junctions and activating both BJT
devices. When the current gain product of the two bipolar
is sufficient to cause regeneration, the PNPN SCR can be
switched to a low impedance, high current state. This
condition is defined as latch-up; and the condition is self
sustaining after original stimulus is removed, provided the
power supplies are capable of sourcing the excess current.
Latch up when it occurs in CMOS, can result in momentary
or permanent loss of circuit function.
•CONDITION FOR LATCH UP IS
NPN
PNP > 1
•Part of NPN collector current (I
B
NPN
) flow into the PNP
base and other part shunted to the n+ well contact through
well resistor (Rw). This current denoted as Iw.
•The base current in PNP is
NPNI
B – Iw
•Collector current in PNP becomes
PNP (I
B
NPN – Iw)
•Similarly part of the collector current (denoted as Is) is
shunted to the substrate contact through the substrate
resistance (Rs).
•The feedback current flowing into NPN base is
(I
B
NPN – Iw)
PNP - I
S
•Latch up condition is
(I
B
NPN – Iw)
PNP - I
S > I
B
B
NPN
) flow into the PNP
base and other part shunted to the n+ well contact through
well resistor (Rw). This current denoted as Iw.
•The base current in PNP is
NPNI
B – Iw
•Collector current in PNP becomes
PNP (I
B
NPN – Iw)
•Similarly part of the collector current (denoted as Is) is
shunted to the substrate contact through the substrate
resistance (Rs).
•The feedback current flowing into NPN base is
(I
B
NPN – Iw)
PNP - I
S
•Latch up condition is
(I
B
NPN – Iw)
PNP - I
S > I
B
•I
W
and I
S
are approximately equal to V
beP
/ R
W
and V
beN
/ R
S
respectively. V
beP & V
beN are the base-emitter voltage of
PNP and NPN transistors, respectively. They are
approximately 0.7 volt.
•For vertical transistor the can be. Controlled by adjusting
well depth, well concentration and V
be
in well. The well
depth sets base width and concentration. In the case of
lateral transistors the can be controlled by layout spacing
between the diffusion outside well to the well edge. This
distance represents the base width.
W
and I
S
are approximately equal to V
beP
/ R
W
and V
beN
/ R
S
respectively. V
beP & V
beN are the base-emitter voltage of
PNP and NPN transistors, respectively. They are
approximately 0.7 volt.
•For vertical transistor the can be. Controlled by adjusting
well depth, well concentration and V
be
in well. The well
depth sets base width and concentration. In the case of
lateral transistors the can be controlled by layout spacing
between the diffusion outside well to the well edge. This
distance represents the base width.
LATCH UP CHARACTERISTICS
•Latch up is normally characterized by triggering and
holding condition.
•Triggering The current and voltage needed to initiate
latch up
•Holding The voltage and current needed to sustain a
latched state once it is triggered.
•For the latch up condition to sustain the holding voltage
should be more than the supply voltage.
•Different NPN, PNP conduction is performed due to
parasitic effects, which leads to latch up.
•Latch up is normally characterized by triggering and
holding condition.
•Triggering The current and voltage needed to initiate
latch up
•Holding The voltage and current needed to sustain a
latched state once it is triggered.
•For the latch up condition to sustain the holding voltage
should be more than the supply voltage.
•Different NPN, PNP conduction is performed due to
parasitic effects, which leads to latch up.
LATCH UP PREVENTION TECHNIQUES
•Bipolar Spoiling
–Keep the very low such that
NPN
PNP < 1
•Bipolar De-coupling
–Reduce the resistance Rs & Rw
•Methods are :-
–Retrograde well
–Epitaxial substrate
–Guard rings
–Trench isolation
•Bipolar Spoiling
–Keep the very low such that
NPN
PNP < 1
•Bipolar De-coupling
–Reduce the resistance Rs & Rw
•Methods are :-
–Retrograde well
–Epitaxial substrate
–Guard rings
–Trench isolation
LATCH UP PREVENTION TECHNIQUES
–Make as many substrate contacts as possible.
–N
+
- P
+
distance should be higher.
•Guard Bars
–To prevent latch up
–To provide isolation between modules
•Soft & Hard Guard Bars
–Soft Guard Bar - Just a diode, making use of depletion
region, without connecting to any potential.
•Use of Butted Contacts
–Acts as a guard bar as well as a substrate contact.
–Make as many substrate contacts as possible.
–N
+
- P
+
distance should be higher.
•Guard Bars
–To prevent latch up
–To provide isolation between modules
•Soft & Hard Guard Bars
–Soft Guard Bar - Just a diode, making use of depletion
region, without connecting to any potential.
•Use of Butted Contacts
–Acts as a guard bar as well as a substrate contact.
Electro Static Discharge
•Human body and other materials can accumulate static
charge measuring in kilovolts. If a charged material comes
into contact with the input pin of the device, the static
charge will start discharging through V
G
and V
sub
resulting
in momentarily large current which can damage gate oxide
or metal interconnect. Proper bye-pass structures are
therefore required to take care of this. These structures
invariably cause delay and need to be considered during
design.
•Direct device damage is caused by
–Gate oxide breakdown
–Opening of metal lines
•Human body and other materials can accumulate static
charge measuring in kilovolts. If a charged material comes
into contact with the input pin of the device, the static
charge will start discharging through V
G
and V
sub
resulting
in momentarily large current which can damage gate oxide
or metal interconnect. Proper bye-pass structures are
therefore required to take care of this. These structures
invariably cause delay and need to be considered during
design.
•Direct device damage is caused by
–Gate oxide breakdown
–Opening of metal lines
SIMULATING ESD EVENTS
•The most commonly used models are
–Human Body Model (HBM)
•Representing the charged human body touching the
IC.
–Machine Model (MM)
•Representing a charged conducting object making
contact with the IC.
–Charged device model (CDM)
•Representing the discharge of a packaged IC.
•The most commonly used models are
–Human Body Model (HBM)
•Representing the charged human body touching the
IC.
–Machine Model (MM)
•Representing a charged conducting object making
contact with the IC.
–Charged device model (CDM)
•Representing the discharge of a packaged IC.
ESD Protection Schemes
•The primary protection element is responsible for shunting
most of the high current encountered during the ESD stress.
•The secondary protection elements purpose is to limit the
voltage which appear across the first gate oxide. It is aided
by the resistor which limits the current for low source
impedance ESD stress (MM or CDM)
Bond Pads Resistor Device to be protected
Primary
Protection
Secondary
Protection
•The primary protection element is responsible for shunting
most of the high current encountered during the ESD stress.
•The secondary protection elements purpose is to limit the
voltage which appear across the first gate oxide. It is aided
by the resistor which limits the current for low source
impedance ESD stress (MM or CDM)
Bond Pads Resistor Device to be protected
Primary
Protection
Secondary
Protection
•Examples of primary protection elements include thick
field device, SCRs, large p-n diodes etc.
•Examples of secondary protection elements include
grounded-gate transistor, thick field devices, P-N diodes
etc.
PAD
Circuit to be
protected
V
DD
V
SS
PAD
Circuit to be
protected
TFD FPD
field device, SCRs, large p-n diodes etc.
•Examples of secondary protection elements include
grounded-gate transistor, thick field devices, P-N diodes
etc.
PAD
Circuit to be
protected
V
DD
V
SS
PAD
Circuit to be
protected
TFD FPD
MOS MODELING
•INTRINSIC PART MODELING :-
–QUASI STATIC OPERATION :-
+
-
V
G
+
-
V
S
-
+
V
B
+
-
V
D
IT
Is
Q
G
I
G
=0
I
D
Q
B
Qi
I
B=0
•INTRINSIC PART MODELING :-
–QUASI STATIC OPERATION :-
+
-
V
G
+
-
V
S
-
+
V
B
+
-
V
D
IT
Is
Q
G
I
G
=0
I
D
Q
B
Qi
I
B=0
•Currents & charges under d.c excitation
•Transport or conduction current is the current that arises from
flow of the elections in the channel from source to drain.
I
G=0, I
D=I
T, I
B=0, I
S=-I
T
I
T
= h
T
(V
D
, V
G
, V
B
, V
S
)
•Where h
T
is an appropriate function dependent on the model
used to describe the device’s dc behavior.
•Again
Q
I = f
I (V
D, V
G, V
B, V
S)
Q
G = f
G (V
D, V
G, V
B, V
S)
Q
B
= f
B
(V
D
, V
G
, V
B
, V
S
)
•Q
G
& Q
B
can be interpreted as charges stored in the device.
•Transport or conduction current is the current that arises from
flow of the elections in the channel from source to drain.
I
G=0, I
D=I
T, I
B=0, I
S=-I
T
I
T
= h
T
(V
D
, V
G
, V
B
, V
S
)
•Where h
T
is an appropriate function dependent on the model
used to describe the device’s dc behavior.
•Again
Q
I = f
I (V
D, V
G, V
B, V
S)
Q
G = f
G (V
D, V
G, V
B, V
S)
Q
B
= f
B
(V
D
, V
G
, V
B
, V
S
)
•Q
G
& Q
B
can be interpreted as charges stored in the device.
•Q
I
is simply the total charge of the electrons that happen to
be in the inversion layer at any given instant.
•The variation of the terminal voltages is sufficiently slow,
so that the device operates quasistatically .
•V
D
(t), V
G
(t), V
B
(t) & V
S
(t) be the varying terminal
voltages, then at any position the charges per unit area at
any time t’ are assumed identical to those that would be
found if dc voltages were used instead of values,
V
D = V
D(t’), V
G = V
G(t’), V
B = V
B(t’) & V
S = V
S(t)
q
I
(t) = f
I
(V
D
(t), V
G
(t), V
B
(t), V
S
(t) )
q
G
(t) = f
G
(V
D
(t), V
G
(t), V
B
(t), V
S
(t) )
q
B
(t) = f
B
(V
D
(t), V
G
(t), V
B
(t), V
S
(t) )
I
is simply the total charge of the electrons that happen to
be in the inversion layer at any given instant.
•The variation of the terminal voltages is sufficiently slow,
so that the device operates quasistatically .
•V
D
(t), V
G
(t), V
B
(t) & V
S
(t) be the varying terminal
voltages, then at any position the charges per unit area at
any time t’ are assumed identical to those that would be
found if dc voltages were used instead of values,
V
D = V
D(t’), V
G = V
G(t’), V
B = V
B(t’) & V
S = V
S(t)
q
I
(t) = f
I
(V
D
(t), V
G
(t), V
B
(t), V
S
(t) )
q
G
(t) = f
G
(V
D
(t), V
G
(t), V
B
(t), V
S
(t) )
q
B
(t) = f
B
(V
D
(t), V
G
(t), V
B
(t), V
S
(t) )
•Charging currents.
i
G
(t) = dq
G
/dt i
P
(t) = dq
B
/ dt
and,i
D
(t) _ i
S
(t) = dq
I
/ dt
Again,i
D(t) = i
T(t) + i
DC(t)
i
S(t) = -i
T(t) + i
SC(t)
i
DC
(t) + i
SC
(t) = dqI / dt
•i
T(t) as wholly responsible for the transport effect.
•i
DC
(t) & i
SC
(t) as wholly responsible for changing q
I
so it is called charging
current.
i
DC
(t) = dq
D
/ dt , i
SC
(t) = dq
S
/ dt
dq
I/ dt = dq
D / dt + dq
S / dt
i
T
(t) = h
T
(V
D
(t), V
G
(t), V
B
(t), V
S
(t) )
Four charging current components.
•i
DC(t) = dq
D / dt, i
G(t) = dq
G / dt,
•i
B(t) = dq
B / dt, i
SC(t) = dq
S / dt
i
G
(t) = dq
G
/dt i
P
(t) = dq
B
/ dt
and,i
D
(t) _ i
S
(t) = dq
I
/ dt
Again,i
D(t) = i
T(t) + i
DC(t)
i
S(t) = -i
T(t) + i
SC(t)
i
DC
(t) + i
SC
(t) = dqI / dt
•i
T(t) as wholly responsible for the transport effect.
•i
DC
(t) & i
SC
(t) as wholly responsible for changing q
I
so it is called charging
current.
i
DC
(t) = dq
D
/ dt , i
SC
(t) = dq
S
/ dt
dq
I/ dt = dq
D / dt + dq
S / dt
i
T
(t) = h
T
(V
D
(t), V
G
(t), V
B
(t), V
S
(t) )
Four charging current components.
•i
DC(t) = dq
D / dt, i
G(t) = dq
G / dt,
•i
B(t) = dq
B / dt, i
SC(t) = dq
S / dt
•Kirchoff’s law holds for total as well as charging currents also.
i
D
(t) + i
G
(t) + i
B
(t) + i
S
(t) = 0
i
DC(t) + i
G(t) + i
B(t) + i
SC(t) = 0
q
D dV
D q
D dV
G q
D dV
B q
D dV
S
i
DC(t) =----- ---- +---- ----- +---- ----- +----- -----
V
D
dtV
G
dtV
B
dtdV
S
dt
q
G dV
D q
G dV
G q
G dV
B q
G dV
S
i
G(t) =----- ---- +---- ----- +---- ----- +----- -----
V
D
dtV
G
dtV
B
dtdV
S
dt
q
B
dV
D
q
B
dV
G
q
B
dV
B
q
B
dV
S
i
B(t) =----- ---- +---- ----- +---- ----- +----- -----
V
D
dtV
G
dtV
B
dtdV
S
dt
q
S dV
D q
S dV
G q
S dV
B q
S dV
S
i
SC(t) =----- ---- +---- ----- +---- ----- +----- -----
V
D dtV
G dtV
B dtdV
Sdt
i
D
(t) + i
G
(t) + i
B
(t) + i
S
(t) = 0
i
DC(t) + i
G(t) + i
B(t) + i
SC(t) = 0
q
D dV
D q
D dV
G q
D dV
B q
D dV
S
i
DC(t) =----- ---- +---- ----- +---- ----- +----- -----
V
D
dtV
G
dtV
B
dtdV
S
dt
q
G dV
D q
G dV
G q
G dV
B q
G dV
S
i
G(t) =----- ---- +---- ----- +---- ----- +----- -----
V
D
dtV
G
dtV
B
dtdV
S
dt
q
B
dV
D
q
B
dV
G
q
B
dV
B
q
B
dV
S
i
B(t) =----- ---- +---- ----- +---- ----- +----- -----
V
D
dtV
G
dtV
B
dtdV
S
dt
q
S dV
D q
S dV
G q
S dV
B q
S dV
S
i
SC(t) =----- ---- +---- ----- +---- ----- +----- -----
V
D dtV
G dtV
B dtdV
Sdt
•A transistor with terminal voltages consisting of a dc bias plus a
time – varying small signal.
C
KK
= + q
K
/ V
K
| 0
C
KL = - q
K / V
L | 0l!= k
•Here C
KK
represents the effect of voltage change of node ‘k’ on
the charge of node ‘k’, while other node voltages are at their bias
point represented here by’0.
+
-
+
-
+
-
+
-
G
D I
D
+id
I
B
+idB
I
S+is
ig
Vg(t)
V
G
S
Vs(t)
Vs V
B
Vb(t)
V
D
Vd(t)
time – varying small signal.
C
KK
= + q
K
/ V
K
| 0
C
KL = - q
K / V
L | 0l!= k
•Here C
KK
represents the effect of voltage change of node ‘k’ on
the charge of node ‘k’, while other node voltages are at their bias
point represented here by’0.
+
-
+
-
+
-
+
-
G
D I
D
+id
I
B
+idB
I
S+is
ig
Vg(t)
V
G
S
Vs(t)
Vs V
B
Vb(t)
V
D
Vd(t)
•C
KL
represent the effect of voltage change of node ‘L’ on the
charge of node ‘k’, while other node voltages are at their bias
point represented here by ‘0’.
•Now to explain the above effect we consider five capacitance
parameters Cgs, Cbs, Cgd, Cbd & Cgb.
S
V
GD
+
-V
SO
+
-
+
-V
BO
V
DO
+
-
+
-
Q
GD
+ QG
D
Q
BD
+ Q
B
G
B
V
D
Effect of a small increase
in the drain voltage.
KL
represent the effect of voltage change of node ‘L’ on the
charge of node ‘k’, while other node voltages are at their bias
point represented here by ‘0’.
•Now to explain the above effect we consider five capacitance
parameters Cgs, Cbs, Cgd, Cbd & Cgb.
S
V
GD
+
-V
SO
+
-
+
-V
BO
V
DO
+
-
+
-
Q
GD
+ QG
D
Q
BD
+ Q
B
G
B
V
D
Effect of a small increase
in the drain voltage.
-Q
G
-Q
B
Cgd= ----- Cbd= --------
V
D V
D
S
V
GD
+
-V
SO
+
-
+
-
V
BO
V
DO
+
-
+
-
Q
GD
+ Q
G
Q
G
D
G
B
V
B
Effect of a small increase
in the body voltage.
G
-Q
B
Cgd= ----- Cbd= --------
V
D V
D
S
V
GD
+
-V
SO
+
-
+
-
V
BO
V
DO
+
-
+
-
Q
GD
+ Q
G
Q
G
D
G
B
V
B
Effect of a small increase
in the body voltage.
- Q
G
Cgd= - -----
V
D
S
V
GD
+
-V
SO
+
-
V
BO
V
DO
+
-
+
-
Q
GO
D
G
B
Transistor biased with
four dc voltages at a
certain operating point
G
Cgd= - -----
V
D
S
V
GD
+
-V
SO
+
-
V
BO
V
DO
+
-
+
-
Q
GO
D
G
B
Transistor biased with
four dc voltages at a
certain operating point
- Q
G
- Q
B
Cgs= ----- C
bS= --------
V
S
V
S
S
V
GD
+
-
V
SO
+
-
V
BO
V
DO
+
-
+
-
D
G
B
+
-
Vs
Q
GD
+ Q
G
Q
BD
+ Q
B
Effect of a small increase
in the source voltage
G
- Q
B
Cgs= ----- C
bS= --------
V
S
V
S
S
V
GD
+
-
V
SO
+
-
V
BO
V
DO
+
-
+
-
D
G
B
+
-
Vs
Q
GD
+ Q
G
Q
BD
+ Q
B
Effect of a small increase
in the source voltage
+
-
S
g
Cgs
-Cgs Vs
+Cgs Vs
Vs Meaning of Cgs, the small
signal intrinsic gate source
capacitance`
Cgs
Cgd
dS
Cbs
Cbd
Cgb
b
g
ImVgs
ImbVgs
gd
-
S
g
Cgs
-Cgs Vs
+Cgs Vs
Vs Meaning of Cgs, the small
signal intrinsic gate source
capacitance`
Cgs
Cgd
dS
Cbs
Cbd
Cgb
b
g
ImVgs
ImbVgs
gd
•Small signal equivalent circuit of intrinsic part of MOSFET.
–Small signal gate conductance g
m
g
m = - I
D / V
as | V
BS, V
DS
–Small signal substrate trans-conductance g
ms
g
ms = - I
D / V
BS | V
GS, V
DS
–Small signal drain conductance g
d
g
d = - I
D / V
DS | V
GS, V
BS
•Different capacitances arises in the intrinsic part MOSFET.
C
gs
= - I
G
/ V
S
| V
G
, V
D
, V
B
,
C
bd = Q
B / V
D | V
G, V
D, V
B
–Small signal gate conductance g
m
g
m = - I
D / V
as | V
BS, V
DS
–Small signal substrate trans-conductance g
ms
g
ms = - I
D / V
BS | V
GS, V
DS
–Small signal drain conductance g
d
g
d = - I
D / V
DS | V
GS, V
BS
•Different capacitances arises in the intrinsic part MOSFET.
C
gs
= - I
G
/ V
S
| V
G
, V
D
, V
B
,
C
bd = Q
B / V
D | V
G, V
D, V
B
C
bs
= I
B
/ V
S
| V
G
, V
D
, V
B
C
gb= Q
G / V
B | V
G, V
S, V
D
0.2 Cox
0.6 Cox
0.8 Cox
2 46810VDS
Cgs
Cgd
C
DS
Cbd
Cgb
Non Saturation
Saturation
V
GS
=8YV
SB
= 0V
0.2 Cox
0.6 Cox
0.8 Cox
2 46810VDS
Cgs
Cgd
C
DS
Cbd
Cgb
Non Saturation
Saturation
V
GS
=8VV
SB
= 5V
bs
= I
B
/ V
S
| V
G
, V
D
, V
B
C
gb= Q
G / V
B | V
G, V
S, V
D
0.2 Cox
0.6 Cox
0.8 Cox
2 46810VDS
Cgs
Cgd
C
DS
Cbd
Cgb
Non Saturation
Saturation
V
GS
=8YV
SB
= 0V
0.2 Cox
0.6 Cox
0.8 Cox
2 46810VDS
Cgs
Cgd
C
DS
Cbd
Cgb
Non Saturation
Saturation
V
GS
=8VV
SB
= 5V
•Variation of different capacitances with V
DS
.
0.2 Cox
0.6 Cox
0.8 Cox
2
4 6 8 10VDS
Saturation
Non-Saturation
0.4 Cox
Week
inversion
Moderate
inversion
V
DS
= 4V
V
SB
= 0V
Variation of different
capacitance with Vas.
DS
.
0.2 Cox
0.6 Cox
0.8 Cox
2
4 6 8 10VDS
Saturation
Non-Saturation
0.4 Cox
Week
inversion
Moderate
inversion
V
DS
= 4V
V
SB
= 0V
Variation of different
capacitance with Vas.
EXTENSION OF SIMPLE QS ANALYSIS TO
COMPLETE QS MODELING
•Of the Capacitance parameters defined earlier, five (Cgs,
Cbs, Cgd, Cbd & Cgb) have precisely the meaning
discussed.
•Using the above definitions, we have from equ~ and the
earlier discussions, the following expressions for small
signal charging currents.
dV
d dV
gdV
b dV
s
i
dc(t) = + C
dd ----- - C
dg ----- - C
db ----- - C
ds -----
dt dt dt dt
dV
d dV
gdV
bdV
s
i
g
(t) = + C
gd
----- + C
gg
----- - C
gb
----- - C
gs
-----
dt dt dtdt
COMPLETE QS MODELING
•Of the Capacitance parameters defined earlier, five (Cgs,
Cbs, Cgd, Cbd & Cgb) have precisely the meaning
discussed.
•Using the above definitions, we have from equ~ and the
earlier discussions, the following expressions for small
signal charging currents.
dV
d dV
gdV
b dV
s
i
dc(t) = + C
dd ----- - C
dg ----- - C
db ----- - C
ds -----
dt dt dt dt
dV
d dV
gdV
bdV
s
i
g
(t) = + C
gd
----- + C
gg
----- - C
gb
----- - C
gs
-----
dt dt dtdt
dV
d dV
g dV
b dV
s
i
b(t) = + C
bd ----- - C
bg ----- + C
bb----- - C
bs ----
dt dt dt dt
dV
d dV
g dV
b dV
s
i
sc(t) = - C
sd ----- - C
sg ----- - C
sb ----- + C
ss -----
dt dt dt dt
In generalC
KL != C
LK
+
-
V
G
V
S
V
B
V
D
V(t)
B
S
G
D
A transistor with all four terminal small-signal voltage equal
d dV
g dV
b dV
s
i
b(t) = + C
bd ----- - C
bg ----- + C
bb----- - C
bs ----
dt dt dt dt
dV
d dV
g dV
b dV
s
i
sc(t) = - C
sd ----- - C
sg ----- - C
sb ----- + C
ss -----
dt dt dt dt
In generalC
KL != C
LK
+
-
V
G
V
S
V
B
V
D
V(t)
B
S
G
D
A transistor with all four terminal small-signal voltage equal
Vd(t) = Vg(t) = Vb(t) = Vs(t) = V(t)
i
dc(t)= (C
dd-C
dg-C
db-C
ds) dv / dt
•There is no small-signal voltage across any two of the
terminals, all small signal currents must be zero. It is true for
non zero dV/dt
C
dd-C
dg-C
db-C
ds = 0
Again i
dc(t) + i
g(t) + i
b(t) + i
sc(t) = 0
Assume, dVg / dt = dVb/dt = dVs / dt = 0
We have,(C
dd
-C
dg
-C
db
-C
ds
) dVd / dt= 0
C
dd-C
dg-C
db-C
ds = 0
dV
ds
dV
gs
dV
bs
dV
s
i
dc(t) = + C
dd ----- - C
dg ----- - C
db ----- +(C
dd-C
dg-C
db-C
ds) ----
dt dt dtdt
i
dc(t)= (C
dd-C
dg-C
db-C
ds) dv / dt
•There is no small-signal voltage across any two of the
terminals, all small signal currents must be zero. It is true for
non zero dV/dt
C
dd-C
dg-C
db-C
ds = 0
Again i
dc(t) + i
g(t) + i
b(t) + i
sc(t) = 0
Assume, dVg / dt = dVb/dt = dVs / dt = 0
We have,(C
dd
-C
dg
-C
db
-C
ds
) dVd / dt= 0
C
dd-C
dg-C
db-C
ds = 0
dV
ds
dV
gs
dV
bs
dV
s
i
dc(t) = + C
dd ----- - C
dg ----- - C
db ----- +(C
dd-C
dg-C
db-C
ds) ----
dt dt dtdt
dV
ds
dV
gs
dV
bs
i
dc(t) = + C
dd ----- - C
dg ----- - C
db-----
dt dt dt
dV
ds
dV
gs
dV
bs
i
g(t) = + C
gd ----- + C
gg ----- - C
gb-----
dt dt dt
dV
ds
dV
gs
dV
bs
i
b
(t) = + C
bd
----- + C
bg
----- - C
bb
-----
dt dt dt
Complete small signal description of the charging
mechanisms requires nine independent capacitance
parameters.
ds
dV
gs
dV
bs
i
dc(t) = + C
dd ----- - C
dg ----- - C
db-----
dt dt dt
dV
ds
dV
gs
dV
bs
i
g(t) = + C
gd ----- + C
gg ----- - C
gb-----
dt dt dt
dV
ds
dV
gs
dV
bs
i
b
(t) = + C
bd
----- + C
bg
----- - C
bb
-----
dt dt dt
Complete small signal description of the charging
mechanisms requires nine independent capacitance
parameters.
Cbb
Cgg
Cdd idc
ig
g
isc
d
ib
b
dVgs
Cdg -----
dt
dVds
Cgd -----
dt
dVds
Cgb -----
dt
dVds
Cbd -----
dt
dVgs
Cbg -----
dt
dVbs
Cdb -----
dt
Cgg
Cdd idc
ig
g
isc
d
ib
b
dVgs
Cdg -----
dt
dVds
Cgd -----
dt
dVds
Cgb -----
dt
dVds
Cbd -----
dt
dVgs
Cbg -----
dt
dVbs
Cdb -----
dt
Cbb
Cgg
Cdd id
ig
g
isc
d
ib
b
dVgs
Cdg -----
dt
dVds
Cgd -----
dt
dVds
Cbd -----
dt
dVbs
Cdb -----
dt
ImVgs
gd
ImbVbs
dVds
Cgb -----
dt
dVgs
Cbg -----
dt
Cgg
Cdd id
ig
g
isc
d
ib
b
dVgs
Cdg -----
dt
dVds
Cgd -----
dt
dVds
Cbd -----
dt
dVbs
Cdb -----
dt
ImVgs
gd
ImbVbs
dVds
Cgb -----
dt
dVgs
Cbg -----
dt
•A small – signal equivalent circuit resulting from complete
quasistatic analysis.
C
dd = C
dg + C
db + C
ds = C
gd + C
bd + C
sd
C
gg
= C
gd
+ C
gb
+ C
gs
= C
dg
+ C
bg
+ C
sg
C
bb = C
bg + C
bg + C
bs = C
db + C
gb + C
sb
C
ss
= C
sd
+ C
sb
+ C
sb
= C
ds
+ C
gs
+ C
bs
•Now, we write
V
D= V
DS + V
S
V
G
= V
GS
+ V
S
V
B
= V
BS
+ V
S
quasistatic analysis.
C
dd = C
dg + C
db + C
ds = C
gd + C
bd + C
sd
C
gg
= C
gd
+ C
gb
+ C
gs
= C
dg
+ C
bg
+ C
sg
C
bb = C
bg + C
bg + C
bs = C
db + C
gb + C
sb
C
ss
= C
sd
+ C
sb
+ C
sb
= C
ds
+ C
gs
+ C
bs
•Now, we write
V
D= V
DS + V
S
V
G
= V
GS
+ V
S
V
B
= V
BS
+ V
S
•A different topology of small – signal equivalent circuit
will now be derived.
•Vds= Vdg + Vgs= - Vgd + Vgs
•Vbs= Vbg + Vgs= - Vgb + Vgs
+
-
Vs(t)
B
S
G
D
+
-
V
GS
(t)
- +
- +
V
BS(t)
V
DS(t)
A transistor with terminal voltages referenced to the source
will now be derived.
•Vds= Vdg + Vgs= - Vgd + Vgs
•Vbs= Vbg + Vgs= - Vgb + Vgs
+
-
Vs(t)
B
S
G
D
+
-
V
GS
(t)
- +
- +
V
BS(t)
V
DS(t)
A transistor with terminal voltages referenced to the source
i
g(t) = - C
gd (- dV
gd / dt + dV
gs / dt) + C
gg dV
gs / dt - C
gb(dV
gb /dt+dV
gs / dt)
dV
gd dV
gb dV
gs
= + C
gd
----- - C
gb
----- + (C
gg
-C
gd
-C
gb
) ----
dt dt dt
dV
gd dV
gb dV
gs
i
g(t) = C
gd ----- + C
gb ----- + C
gs -----
dt dt dt
dV
gd dV
gb dV
gs dV
gs dV
bs
i
dc(t) = C
gd ----- + C
sd ----- + C
bd ----- -C
m ----- - C
mb -----
dt dt dt dt dt
g(t) = - C
gd (- dV
gd / dt + dV
gs / dt) + C
gg dV
gs / dt - C
gb(dV
gb /dt+dV
gs / dt)
dV
gd dV
gb dV
gs
= + C
gd
----- - C
gb
----- + (C
gg
-C
gd
-C
gb
) ----
dt dt dt
dV
gd dV
gb dV
gs
i
g(t) = C
gd ----- + C
gb ----- + C
gs -----
dt dt dt
dV
gd dV
gb dV
gs dV
gs dV
bs
i
dc(t) = C
gd ----- + C
sd ----- + C
bd ----- -C
m ----- - C
mb -----
dt dt dt dt dt
dV
bd
dV
bg
dV
gb
dV
bs
i
b(t) = C
bd ---- + C
gb ----- - C
mx ----- + C
bs -----
dt dt dt dt
•Where
C
m
= C
dg
– C
gd
C
mb
= C
db
– C
bd
C
mx
= C
bg
– C
gb
bd
dV
bg
dV
gb
dV
bs
i
b(t) = C
bd ---- + C
gb ----- - C
mx ----- + C
bs -----
dt dt dt dt
•Where
C
m
= C
dg
– C
gd
C
mb
= C
db
– C
bd
C
mx
= C
bg
– C
gb
dVgs
Cmb -----
dt
dVbs
Cmb -----
dt
dVgb
Cmx -----
dt
gmVgs
gd
Csd
gmbVbs
is
id
Cgb
Cbd
Cbs
ib
b
Ig(t)
g
Cmb -----
dt
dVbs
Cmb -----
dt
dVgb
Cmx -----
dt
gmVgs
gd
Csd
gmbVbs
is
id
Cgb
Cbd
Cbs
ib
b
Ig(t)
g
•A complete quasistatic small signal model.
–At sufficiently low frequencies dV
gs
/dt and dV
bs
/dt will
be small, and the currents proportional to these
quantitie can be neglected in comparison to the currents
g
m
V
gs
, and g
m
bV
bs
.
–The current through C
sd can be neglected in comparison
to the current through g
d
–For approximate strong inversion model C
mx = 0
•With above assumptions the above equivalent circuit
approximated to the earlier derived equivalent circuit.
–At sufficiently low frequencies dV
gs
/dt and dV
bs
/dt will
be small, and the currents proportional to these
quantitie can be neglected in comparison to the currents
g
m
V
gs
, and g
m
bV
bs
.
–The current through C
sd can be neglected in comparison
to the current through g
d
–For approximate strong inversion model C
mx = 0
•With above assumptions the above equivalent circuit
approximated to the earlier derived equivalent circuit.
0.2Cox
0.4Cox
0.6Cox
0.8Cox
2 4 6 8
V
GS
(V)
Cgs
Cgd
Cbd
Csd
Cgb
Cmx
Cmb
Cbs
Cm
Saturation
Mox
Derate
inversion
Week
inversion
Non-saturation
Variation of nine capacitances with Vas for V
DS
= 4V and V
SB
= 0V
0.4Cox
0.6Cox
0.8Cox
2 4 6 8
V
GS
(V)
Cgs
Cgd
Cbd
Csd
Cgb
Cmx
Cmb
Cbs
Cm
Saturation
Mox
Derate
inversion
Week
inversion
Non-saturation
Variation of nine capacitances with Vas for V
DS
= 4V and V
SB
= 0V
Different capacitance terms arises in the extrinsic part of MOSFET.
Rsb Rdsb
Rdb
S D
Csd
Rch
Cgso
Cdgo
G
Rs Rd
CjdbCjsb
p
n+ n+
Rsb Rdsb
Rdb
S D
Csd
Rch
Cgso
Cdgo
G
Rs Rd
CjdbCjsb
p
n+ n+
Equivalent circuit of MOSFET including the extrinsic part.
G
Small signal
equivalent circuit
for intrinsic part
Rdsb
CjdbCjsb
Rsb Rdb
Cbb’
B
S
Rs Rd
Cgbe
Cgdo
Cgse
Csde
D
Rg
G
Small signal
equivalent circuit
for intrinsic part
Rdsb
CjdbCjsb
Rsb Rdb
Cbb’
B
S
Rs Rd
Cgbe
Cgdo
Cgse
Csde
D
Rg
SMALL SIGNAL MODELING FOR THE EXTRINSIC
PART OF MOSFET
•The charge storage effects associated with the extrinsic
part can be modeled by using six small – signal
capacitances.
•If the transistor happens to be inside a well on a CMOS
Chip, then the capacitance due to the p-n junction between
the well and the common substrate on which well has been
formed. This capacitance is denoted by C
b’b.
•Gate over lap capacitances :-
–Cgso and Cgdo, Cgbo
–Cgso = Cgdo = C’ox W Lov
•Junction capacitances :-
–Cbse, Cbde, Cbb
PART OF MOSFET
•The charge storage effects associated with the extrinsic
part can be modeled by using six small – signal
capacitances.
•If the transistor happens to be inside a well on a CMOS
Chip, then the capacitance due to the p-n junction between
the well and the common substrate on which well has been
formed. This capacitance is denoted by C
b’b.
•Gate over lap capacitances :-
–Cgso and Cgdo, Cgbo
–Cgso = Cgdo = C’ox W Lov
•Junction capacitances :-
–Cbse, Cbde, Cbb
•Drain source proximity capacitance :- Csd
–The terminal resistances Rg, Rs, Rd
–Substrate resistances Rdsb, Rsb, Rdb
–Overlap capacitances Cgso, Cgdo
–Junction capacitances Cjsb, Cjdb
–Gate wiring capacitance Cgbe
–S/D proximity capacitance Csde
•CAPACITOR MODEL SELECTION
–CAPOP = 0 SPICE original meyer model (General)
–CAPOP = 1 modified meyer model (General)
–CAPOP = 2 Parameterized modified meyer model
–CAPOP = 3 Parameterized modified meyer model with
simpson integration
–The terminal resistances Rg, Rs, Rd
–Substrate resistances Rdsb, Rsb, Rdb
–Overlap capacitances Cgso, Cgdo
–Junction capacitances Cjsb, Cjdb
–Gate wiring capacitance Cgbe
–S/D proximity capacitance Csde
•CAPACITOR MODEL SELECTION
–CAPOP = 0 SPICE original meyer model (General)
–CAPOP = 1 modified meyer model (General)
–CAPOP = 2 Parameterized modified meyer model
–CAPOP = 3 Parameterized modified meyer model with
simpson integration
–CAPOP = 4 Charge conservation model (analytic) levels
2,3,6,7,13,28&39 only
–CAPOP = 5 No capacitor model.
–CAPOP = 6 AMI Capacitor model. (Level 5)
–CAPOP = 9 Charge conservation model (Level 3)
–CAPOP = 13Generic BSIM Model (Level 13, 28, 39)
–CAPOP = 11Ward–Dutton model (specialized, Level 2)
–CAPOP = 12Ward–Dutton model (specialized, Level 3)
–CAPOP = 39BSIM 2 capacitance model (level 39)
2,3,6,7,13,28&39 only
–CAPOP = 5 No capacitor model.
–CAPOP = 6 AMI Capacitor model. (Level 5)
–CAPOP = 9 Charge conservation model (Level 3)
–CAPOP = 13Generic BSIM Model (Level 13, 28, 39)
–CAPOP = 11Ward–Dutton model (specialized, Level 2)
–CAPOP = 12Ward–Dutton model (specialized, Level 3)
–CAPOP = 39BSIM 2 capacitance model (level 39)
NOISE MODELING IN SEMICONDUCTOR DEVICE
FOR INTEGRATED CIRCUIT APPLICATION
•Noise phenomena are caused by the small current and
voltage fluctuations generated within the devices
themselves.
•Noise in IC is one of the most important factors that
determines the performance of low level integrated
integrated signal processing systems.
•It represents a lower limit to the size of the electrical signal
that can be handled by an IC without significant
deterioration in signal quality.
G
DS
B
iD(t)
I
D
iD(t)
FOR INTEGRATED CIRCUIT APPLICATION
•Noise phenomena are caused by the small current and
voltage fluctuations generated within the devices
themselves.
•Noise in IC is one of the most important factors that
determines the performance of low level integrated
integrated signal processing systems.
•It represents a lower limit to the size of the electrical signal
that can be handled by an IC without significant
deterioration in signal quality.
G
DS
B
iD(t)
I
D
iD(t)
NOISE SPECTRAL DENSITY
•The noise voltage or current x(t) is a quantity with an
average value that is zero
•Thus the most significant mathematical characterization is
obtained using the mean square value of x(t)
•As the variable x(t) might contain frequency components
distributed on a large spectrum, it is necessary to correlate
2
to its power spectral density Sx(f).
•The relation between
2
and Sx(f) comes from fourier
transforms
T
2
= lim 1 x
2
(t)dt
T8 T
o
•The noise voltage or current x(t) is a quantity with an
average value that is zero
•Thus the most significant mathematical characterization is
obtained using the mean square value of x(t)
•As the variable x(t) might contain frequency components
distributed on a large spectrum, it is necessary to correlate
2
to its power spectral density Sx(f).
•The relation between
2
and Sx(f) comes from fourier
transforms
T
2
= lim 1 x
2
(t)dt
T8 T
o
•As the variable x(t) might contain frequency components
distributed on a large spectrum, it is necessary to correlated
2
to its power spectral density Sx(t).
•The relation between
2
and Sx(f) comes from fourier
transform
T
2
= lim 1 x
2
(t)dt
T8 T
o
DIFFERENT NOISE SOURCES & THEIR PHYSICAL MECHANISM
•Shot Noise
–The flow of each carrier across the junction is a random event and is
dependent on the carrier having sufficient energy and velocity
directed toward the junction. Thus external current ‘I’, which
appears to be a steady current, is, infact, compose of a large number
of random independent current pulses.
distributed on a large spectrum, it is necessary to correlated
2
to its power spectral density Sx(t).
•The relation between
2
and Sx(f) comes from fourier
transform
T
2
= lim 1 x
2
(t)dt
T8 T
o
DIFFERENT NOISE SOURCES & THEIR PHYSICAL MECHANISM
•Shot Noise
–The flow of each carrier across the junction is a random event and is
dependent on the carrier having sufficient energy and velocity
directed toward the junction. Thus external current ‘I’, which
appears to be a steady current, is, infact, compose of a large number
of random independent current pulses.
•The resulting noise current has a mean square value.
•
2
= Si(f)f = 2qI
Df
•Here the terminal current ‘I’ is composed of a series of
random independent pulses with average value I
D
.
f is the bandwidth.
•Thermal noise :-
–Thermal noise is generated by the random thermal
motion of the electrons and is unaffected by the
presence or absence of direct current.
–This source of noiswe is due to the thermal motion of
electrons, it is related to absolute temperature ‘T’.
–In a resistor R, thermal noise current has the following
mean square value.
•
2
= Si(f)f = 2qI
Df
•Here the terminal current ‘I’ is composed of a series of
random independent pulses with average value I
D
.
f is the bandwidth.
•Thermal noise :-
–Thermal noise is generated by the random thermal
motion of the electrons and is unaffected by the
presence or absence of direct current.
–This source of noiswe is due to the thermal motion of
electrons, it is related to absolute temperature ‘T’.
–In a resistor R, thermal noise current has the following
mean square value.
2
= Si(f)f = 4K
B
T f
R
•KB is boltaman constant.
•The thermal noise is frequency independent.
i2
R
Representation of thermal noise.
2
= Si(f)f = 4K
B
T f
R
•KB is boltaman constant.
•The thermal noise is frequency independent.
i2
R
Representation of thermal noise.
•Flicker or 1/f Noise :-
–Two models to describe the 1/f Noise.
–Mobility Fluctuation Mode l:-
–The 1/f noise which is further referred to as m-1/f
noise is assumed to be attributed to the fluctuation in
mobilities of free carriers when they collide with the
crystal lattices.
–The PSD of total 1/f noise at saturation is given by
2
= X
L
qM
f
(Vas-V
T
) I
DS
L
2
f
–M
f effective 1/f noise mobility
–XL Hooge 1/f noise parameter.
–Two models to describe the 1/f Noise.
–Mobility Fluctuation Mode l:-
–The 1/f noise which is further referred to as m-1/f
noise is assumed to be attributed to the fluctuation in
mobilities of free carriers when they collide with the
crystal lattices.
–The PSD of total 1/f noise at saturation is given by
2
= X
L
qM
f
(Vas-V
T
) I
DS
L
2
f
–M
f effective 1/f noise mobility
–XL Hooge 1/f noise parameter.
•However, the experimental results on 1/f noise shows
different characteristics which cannot be predicted by
mobility fluctuation model, but the majority of experimental
results can be successfully accounted for using number
fluctuation model.
•Number Fluctuation Model :-
–In the number fluctuation mode, the 1/f noise which is
further referred to as n-1/f noise is believed to be caused
by the random trapping and detrapping of the mobile
carriers in the traps located at Si-SiO
2 interface and within
the gate oxide.
–The spectral density of flicker or 1/f noise.
•
2
= K
f
I
af
/ f
b
f
f band width I direct current
different characteristics which cannot be predicted by
mobility fluctuation model, but the majority of experimental
results can be successfully accounted for using number
fluctuation model.
•Number Fluctuation Model :-
–In the number fluctuation mode, the 1/f noise which is
further referred to as n-1/f noise is believed to be caused
by the random trapping and detrapping of the mobile
carriers in the traps located at Si-SiO
2 interface and within
the gate oxide.
–The spectral density of flicker or 1/f noise.
•
2
= K
f
I
af
/ f
b
f
f band width I direct current
•Kf Constant for a particular device it depends on
contamination and crystal implerfections.
•Af constant
•B constant approximately unity
•BURST OR POPCORN NOISE :-
–Burst noise is another type of low frequency noise
found in some IC and discrete BJT. The source of this
noise is not fully under stod. But it has been shown to
be related to the presence of heavy-metalion
contamination.
2
= K
b
Ic
--------- f
1+(f/fc)
2
contamination and crystal implerfections.
•Af constant
•B constant approximately unity
•BURST OR POPCORN NOISE :-
–Burst noise is another type of low frequency noise
found in some IC and discrete BJT. The source of this
noise is not fully under stod. But it has been shown to
be related to the presence of heavy-metalion
contamination.
2
= K
b
Ic
--------- f
1+(f/fc)
2
•Resistive poly gate noise
•Substrate resistance thermal noise
•Shot noise due to S & b reverse biased diodes.
•DIODE – NOISE MODEL :-
iD
gD CD
rs
irs
Complete diode small signal
equivalent value circuit with
noise source
•Substrate resistance thermal noise
•Shot noise due to S & b reverse biased diodes.
•DIODE – NOISE MODEL :-
iD
gD CD
rs
irs
Complete diode small signal
equivalent value circuit with
noise source
4K
BT I
D
at
2
rs
= ------- f
2
D
= 2qI
D
f + k
f
------ f
r
s
f
•BJT NOISE MODEL :-
ir
B
C
M
irc
CB
E
ir
E
gmV
BEgoic
Ccs
G^ C^
r
E
rc
r
B
i
B
g^
BT I
D
at
2
rs
= ------- f
2
D
= 2qI
D
f + k
f
------ f
r
s
f
•BJT NOISE MODEL :-
ir
B
C
M
irc
CB
E
ir
E
gmV
BEgoic
Ccs
G^ C^
r
E
rc
r
B
i
B
g^
2
rB
= 4KT/ r
B
f,
2
rc
= 4KT / r
C
f
2
rE
= 4KT / r
E
f,
2
C
= 2qIcf
I
B
af
I
B
2
B = 2qI
Bf + kf ------- f + kb ----------- f
f 1+(f/fc)
2
2
rs
= 4KT / r
B
f
2
rB
= 4KT/ r
B
f,
2
rc
= 4KT / r
C
f
2
rE
= 4KT / r
E
f,
2
C
= 2qIcf
I
B
af
I
B
2
B = 2qI
Bf + kf ------- f + kb ----------- f
f 1+(f/fc)
2
2
rs
= 4KT / r
B
f
In SPICE, however, the burst noise effect is not modeled.
D
C
GD
g
m
V
GS
g
m
bV
BS gds
i
D
g
BS
C
BS
irs
S
C
GB
C
GS
r
D
i
rD
r
s
g
BD
C
BD
G
B
D
C
GD
g
m
V
GS
g
m
bV
BS gds
i
D
g
BS
C
BS
irs
S
C
GB
C
GS
r
D
i
rD
r
s
g
BD
C
BD
G
B
2
rD
= 4KT / r
D
f
2
rs
= 4KT / r
S
f
8KTgm I
D
at
2
D
= --------- f + kf ----- f
3 f
2
rD
= 4KT / r
D
f
2
rs
= 4KT / r
S
f
8KTgm I
D
at
2
D
= --------- f + kf ----- f
3 f
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