CMOS TG

ABOUT CMOS TRANSMISSION GATES

1. CMOS Transmission gate Aghila Das ILMCET

2. A transmission gate is simply a digital controlled CMOS switch. The CMOS transmission gate consists of one nMOS and one pMOS transistor connected in parallel. The gate voltages applied to these two transistors are also set to be complementary signals. As such, the CMOS TG operates as a bidirectional switch between the nodes A and B which is controlled by signal C. CMOS Transmission gate

3. Here ,the substrate terminal of the nMOS transistor is connected to ground and the substrate terminal of the pMOS transistor is connected to V DD. Contd …

4. Schematic diagram

5. Circuit symbol

6. CASE I : When the CONTROL input is high Here, the gate of the pMOS transistor is high and nMOS transistor is low. If the data input is low, V GS1 is positive and V GS2 is 0V ; so neither transistor is ON. If data input is high, V GS1 is 0V and V GS2 is negative; so again neither transistor is ON. Therefore, when CONTROL input is high, the device is in the high impedance state. Circuit operation

7. The figure below shows the operation of transmission gate when CONTROL input is high.

8. CASE II : When the CONTROL input is low Contd …. Here, the gate of the pMOS transistor is low and nMOS transistor is high. If the data input is low, V GS1 is 0V and V GS2 is positive; therefore Q1 is OFF and Q2 is ON. If data input is high, V GS1 is negative and V GS2 is 0V; so Q1 is ON and Q2 is OFF. Thus, there is always a conduction path from input to output when control input is low.

9. The figure below shows the operation of transmission gate when CONTROL input is low :

10. For the DC analysis of the CMOS TG, we will consider the following bias conditions, as shown in figure below: DC analysis of the CMOS TG

11. The input node(A) is connected to a constant logic-high voltage, Vin= Vdd . The control signal is also logic high, thus ensuring that both transistors are turned ON. The output node (B) may be connected to a capacitor, which represents capacitive loading of the subsequent logic stages driven by TG. The drain-to-source and the gate-to-source voltages of the nMOS transistor are V DS,n =V DD - V out V GS,n =V DD - V out Contd ….

12. Thus, the nMOS transistor will be turned OFF for V out >V DD - V T,n and will operate in the saturation mode for V out <V DD - V T,n . The V DS and V GS voltages of the pMOS transistor are V DS,p = V out -V DD V GS,p =-V DD Consequently, the pMOS transistor is in saturation for Vout < VT,p and it operates in the linear region for Vout > VT,p The total current flowing through TG is the sum of the nMOS drain current and the pMOS drain current. I D = I DS,n +I SD,p Contd …

13. The equivalent resistance for each transistor is given by R eq,n = V DD - V out I DS,p Req,p = V DD - V out I SD,p The total equivalent resistance of the CMOS Tgwill then be the parallel equivalent of these two resistances. Contd …

14. Truth table Here control input is separated into C and Ć. Input C is connected directly to nMOS gate whereas input Ć is connected to pMOS gate.

15. THE END