Cmosprocessflow

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1. ASSIGNMENT NO 01 CMOS PROCESS FLOW EE16MTECH11012

2. STAGES OF S.C. MANUFACTURING 1.Material preparation 2.Crystal growth and wafer preparation. 3.Device fabrication 4.Packaging

3. SUBSTRATE SELECTION 1.Ptype 2.Moderately high resistivity 3.100

4. ACTIVE REGION FORMATION 1.Wafer cleaning 2.Thermal oxidation(>400A,15 min at 900 deg cel in H2O atm ) 3.Nitride LPCVD deposition(>800A,800 deg cel ) 4.Photoresist spinning 5.Baking

5. Mask 1 1.Pattern the active areas 2.Nitride is dry etched…….

6. Active region formation 1.Wafer cleaning………………………………………………. 2.Thermal oxidation (>400A,15 min 900 deg c) 3.Nitride LPCVD(>800A,800 deg c)……………………..

7. Mask 2 & 3…p &n well formation 1.Photoresist spunning ………………………….………… 2.Masked used for exposure……………….…….…….. 3.Boron implantation to create pwell ….……… 4.Phosphorous implantation to create pwell

8. Implant repair 1.Temp at 1000 deg c-1100 deg c or equ .(4-6hour) 2.Produce final well depth…………………………………... 3.Repairs implant damage by recreating bonds…

9. Mask4(for Boron implantation) 1.Mask4 is used for exposure for boron implantation 2.Photoresist stripped after process…….

10. Mask5(for arsenic implantation) 1.Mask5 is used for exposure for boron implantation 2.Photoresist stripped after process……………………………..

11. Gate oxide growth 1.Active regions thin oxide is stripped…….. 2.New oxide is grown typically at 50-100 a (1-2 hours at 800 deg c in O2)

12. Polysilicon deposition 1.Layer of polysilicon is deposited by thermal decomposition of silane (0.3-0.5um THICK AT 600 DEG C) 2.Polysilicon doped ntype by an unmasked ion implant or by situ doping 3. DOSE OF 5 x 10 15 CM^-2 TO GET LOW POLYSHEET RESISTIVITY AND LOW GATE RESISTANCE…….

13. Mask6( polysilicon etching) 1. Mask 6 is used to protect the mos gates. The poly is plasma etched using an anisotropic etch. 2.Anisotropic etchinng is prefered because of high selectivity

14. Mask 7( LDD formation) 1. Mask protects the pmos devices. A p + implant forms the ldd regions in the nmos devices (typically 5 x 10 13 cm -2 at50 kev ) 2.Lightly doped regions are produced to avoid hot electron effect causes due to ele . Field increased due to reduced length technology. …

15. Mask 8(LDD formation) M ask 8 protects the nmos devices. A B + implant forms the ldd regions in the pmos devices (typically 5 x 10 13 cm -2 at 50 kev ).

16. SiO2 DEPOSITION 1.Thickness of this layer & width of sidewall spacer region would be chosen to optimize characteristics. 2.SiH4+O2 will give rise the SiO2 layer……………………….

17. Anisotropic etching( sidewallspacers ) 1.Anisotropic etching leaves sidewall spacers along the edges of the poly gates. 2.Anistropic vertical etching is used.

18. Mask 9( nmos S&D formation) 1.Mask 9 protects the pmos devices, an as + implant forms the nmos source and drain regions (typically 2-4 x 10 15 cm -2 at 75 kev ). Growth of screen oxide (10nm) to avoid channeling 2.Simply by a deposition and then an etchback,we have formed the sidewall spacer.

19. Mask10 ( pmos S&D formation) 1.Mask 10 protects the nmos devices, a B + implant forms the pmos source and drain regions (typically 1-3 x 10 15 cm -2 at 50 kev ). 2.Low field required because boron is lighter than arsenic and hence require less energy.

20. Active Device Formation A final high temperature anneal drives-in the junctions and repairs implant damage (typically 30 min at 900˚c or 1 min rta at 1000˚c. …

21. Contact and local interconnect 1.Local contact 2.Metal layer 1 contact 3.Metal layer 2 contact 1.An unmasked oxide etch allows contacts to si and poly regions. 2.A short dip in buffered HF solution will etch oxide layer.

22. Ti DEPOSITION 1.Ti is deposited by sputtering (typically 100 nm). 2 .The ti is reacted in an n 2 ambient, forming TiSi 2 and TiN (typically 1 Min @ 600 - 700 ˚c). 3.TiS2 is excellent conductor and forms low resistance contact with n+ and p+. ..

23. TI AND TIS2 FORMATION 1 .Ti+Si- - TiSi2(600-700 deg cel ) forms excellent conductor and low resistance contacts to both n+ and p+ . 2 .Ti +N2- -  TiN conductor but not as high as most metal thus used for local or short distant interconnect. ..

24. Mask 11 1.Mask 11 is used to etch the TiN , forming local interconnects. 2.Etched in NH4OH:H2O2:H2O(1:1:5). 3.After photoresist removal heat at 800 deg c for a min to reduce resistivity of TiN and TiS2 to 10 ohm per sq , 1 ohm per sq respectively.

25. SIO2 LAYER DEPOSITION 1.After stripping the photoresist , a conformal SiO2 layer is deposited by LPCVD to make surface of the wafer planer. 2.Because photolithography is very difficult with highly nonlinear substrate ,especially when metal patterning is involved. 3.Thickness 1 micrometer.

26. Multilevel metal formation Planarization of wafer surface 1.Not desirable to deposit metal interconnects on such a topography with potential problems with metal discontinuties . CMP (chemical mechanical polishing)is used to planarize the wafer surface. .

27. Mask 12 1.Mask 12 is used to define the contact holes. 2.Define the regions where we want contact to be made between metal 1 & underlying structures. 3.SiO2 layer would be etchedin a plasma. 4.After etching the contact holes , photoresist would be stripped off the wafer. ..

28. Deposition of a blanket W layer by CVD 1.Polishing removes W and TiN everywhere except in the contact holes and 2. provide a planer surface on which the 1 st level metal can be deposited. ..

29. Planarization of wafer CMP is used to planarize the wafer surface, completing the damascene process( i.e.contact holes are etched,filled , planarised ).

30. Mask 13 1.Al is deposited on the wafer by sputtering. Mask 13 is used to pattern the Al and plasma etching is used to etch it . 2.Aluminium with small % of Si and Cu in it to avoid problems like Si absorbtion or open circuit . .

31. FINAL STAGE 1. MASK 14  USED TO DEFINE CONTACT VIAS 2. MASK 15  IS USED TO DEFINE METAL 2. 3.A FINAL PASSIVATION LAYER OF SI 3 N 4 IS DEPOSITED BY PECVD AND PATTERNED WITH MASK 16 . 4.Process involves filling up metal 1&2 with TiN and W, deposition of a top dielecric (SiO2 or Si3N4) to protect finished chip.

32. THANKS