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Coa unit 2

1. Basic Computer Organization
and Design
UNIT-II
Computer Organization & Architecture

2. BASIC COMPUTER ORGANIZATION AND DESIGN
• Instruction Codes
• Computer Registers
• Computer Instructions
• Timing and Control
• Instruction Cycle
• Memory Reference Instructions
• Input-Output and Interrupt
• Complete Computer Description
• Design of Basic Computer
• Design of Accumulator Logic

3. INTRODUCTION
•Modern computers are very complex devices than basic computers.
•Every computer organization is defined by its own components.
(like registers, buses, micro-operations, machine instructions, etc)
•Computer contains
–Internal registers
–Timing and control units, arithmetic and logic units,
–Set of instructions that it uses.
–Etc.
•Most complex part of computer is Central Processing Unit(CPU).
•Also known as microprocessor, central processor.
•CPU is responsible for carry out instructions and processing of data.

4. THE BASIC COMPUTER
•The Basic Computer has three components, a processor,
memory and I/O devices.
•The memory has 4096 words in it
–4096 = 2
12
, so it takes 12 bits to select a word in memory
•Each word is 16 bits long.
ALU
CU
Registers
CPU RAM
0
4095
015
I/O Devices

5. INSTRUCTIONS
Instruction codes
•Program
–A sequence of (machine) instructions
•(Machine) Instruction
–A group of bits that tells the computer to perform a specific operation (a sequence of
micro-operation)
•The instructions of a program, along with any needed data are
stored in memory.
•The CPU reads the next instruction from memory
•It is placed in an Instruction Register (IR)
•Control circuitry in control unit then translates the instruction into the
sequence of micro-operations necessary to implement it

6. INSTRUCTION FORMAT
Instruction codes
•A computer instruction is often divided into two parts
–An opcode (Operation Code) that specifies the operation for that instruction
–An address that specifies the registers and/or locations in memory to use for that
operation
•In the Basic Computer, since the memory contains 4096 (= 2
12
)
words, we needs 12 bit (0-11) to specify which memory address this
instruction will use.
•In the Basic Computer, 15
th
bit of the instruction specifies the
addressing mode (0: direct addressing, 1: indirect addressing)
•Since the memory words, and hence the instructions, are 16 bits
long, that leaves 3 bits for the instruction’s opcode(12-14th)
Opcode Address
Instruction Format
1514 12 0
I
11
Addressing
mode

7. ADDRESSING MODES
Instruction codes
•The address field of an instruction can represent either
–Direct address: the address in memory of the data to use (the address of the operand),
or
–Indirect address: the address in memory of the address in memory of the data to use
•Effective Address (EA)
– The effective address refers to the address of an exact memory location in which an
operand’s value is actually present.
0ADD 457
22
Operand
457
1ADD 30035
1350300
Operand1350
+
AC
+
AC
Direct addressing Indirect addressing

8. PROCESSOR REGISTERS
Instruction codes
•A processor has many registers to hold instructions, addresses, data,
etc.
•The processor has a register, the Program Counter (PC) that holds the
memory address of the next instruction
–Since the memory in the Basic Computer only has 4096 locations, the PC only needs 12
bits.
•Address Register (AR): In a direct or indirect addressing, the AR is
used to hold the locations/address for memory.
–The AR is a 12 bit register.
•When an operand is found, using either direct or indirect addressing, it
is placed in the Data Register (DR). Then processor uses this value as
data for its operation.
•The Basic Computer has a single general purpose register – the
Accumulator (AC).

9. PROCESSOR REGISTERS
Instruction codes
•The significance of a general purpose register is that it can be used for
loading operands and storing results
–e.g. load AC with the contents of a specific memory location; store the contents of AC into
a specified memory location
•Temporary Register (TR) : Often a processor need scratch register to
store intermediate results or other data.
•The Basic Computer uses a very simple model of input/output (I/O)
operations
–Input devices are considered to send 8 bits of character data to the processor
–The processor can send 8 bits of character data to output devices
•The Input Register (INPR) holds an 8 bit data received from an input
device.
•The Output Register (OUTR) holds an 8 bit data to be send to an
output device.

10. BASIC COMPUTER REGISTERS
List of Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
Registers
Registers in the Basic Computer
11 0
PC
15 0
IR
15 0
TR
7 0
OUTR
15 0
DR
15 0
AC
11 0
AR
INPR
07
Memory
4096 x 16
CPU

11. COMMON BUS SYSTEM
Registers
•A path must be provided to transfer data between

•The registers in the Basic Computer are connected using a
common bus system.
•Common bus system provides less circuitry over completely
connected registers.
R R
M R

12. COMMON BUS SYSTEM
Registers
S2
S1
S0
Bus
Memory unit
4096 x 16
LD INR CLR
Address
ReadWrite
AR
LD INR CLR
PC
LD INR CLR
DR
LD INR CLR
ACALU
E
INPR
IR
LD
LD INR CLR
TR
OUTR
LD
Clock
16-bit common bus
7
1
2
3
4
5
6

13. COMMON BUS SYSTEM
Registers
AR
PC
DR
LIC
LIC
LIC
AC
LIC
ALU
E
IR
L
TR
LIC
OUTR L
INPR
Memory
4096 x 16
Address
Read
Write
16-bit Common Bus
7 1 2 3 4 5 6
S
0S
1S
2

14. COMMON BUS SYSTEM
Registers
•Three control lines, S
2, S
1, and S
0 control which register the bus selects as its input
•Either one of the registers will have its load signal activated, or the memory will have
its read signal activated
–Will determine where the data from the bus gets loaded
•The 12-bit registers, AR and PC, four most significant bits are set to 0’s.
•When the 8-bit register OUTR is loaded from the bus, the data comes from the lower
8 bits on the bus.
0 0 0x
0 0 1AR
0 1 0PC
0 1 1DR
1 0 0AC
1 0 1IR
1 1 0TR
1 1 1Memory
S
2 S
1 S
0 Register

15. COMMON BUS SYSTEM
DATA
DATA
11
0
7
0
AR/PC
OUTR
DATA
15 11
0
BUS 0 0 0 0
DATA BUS

16. BASIC COMPUTER INSTRUCTIONS
Instructions
• Basic Computer Instruction code Format types
15 1412 11 0
IOpcode Address
Memory-Reference Instructions (OP-code = 000 ~ 110)
Register-Reference Instructions (OP-code = 111, I = 0)
Input-Output Instructions (OP-code =111, I = 1)
15 12 11 0
Register operation0 1 1 1
15 12 11 0
I/O operation1 1 1 1

17. BASIC COMPUTER INSTRUCTIONS
Hex Code
Symbol I = 0 I = 1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer
INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
Instructions
OUTR can only receive information
from the bus.
Memory-Reference Instructions
Register-Reference Instructions
Input/output instructions
I = 0 Direct , I = 1 Indirect
Last four bits always = 0111
Last four bits always = 1111

18. Memory-reference instruction:

AND 0XXX 8XXX AND memory word to AC
01115
X X X0 0 0 0
X X X1 0 0 0
Direct addressing
Indirect addressing

19. Register-reference instructions:

CLA 7800 Clear AC
0
1115
0 1 1 1
1000 0000 00001 1 1 1

Direct addressing
Indirect addressing
Input-output instructions:
IINP F800 Input character to AC

INP F800 Input character to AC
1000 0000 0000

20. INSTRUCTION SET COMPLETENESS
Set of instructions by which user can construct machine language
programs to evaluate any computable function.
Instructions
The set of instructions are said to be complete if the computer includes a
sufficient number of instructions in each of the following categories:
•Functional Instructions
•Transfer Instructions
•Control Instructions
•Input/output Instructions

21. INSTRUCTION SET
• Instruction Types
Set of instructions by which user can construct machine language
programs to evaluate any computable function.
• Functional Instructions : These instruction provides the computational
capabilities for processing the type of data needed.
- Arithmetic, logic, and shift instructions
- ADD Add memory word to AC
- CMA Complement AC
- CIR Circular Right AC and E
•Transfer Instructions : These are the types of instructions
which provides data transfer information between memory and
processor registers.
- LDA Load memory word to AC
- STA Store content of AC in memory
Instructions

22. INSTRUCTION SET COMPLETENESS
• Instruction Types
Set of instructions by which user can construct machine language
programs to evaluate any computable function.
•Control Instructions : The types of instruction are used to control and change
the flow of execution in program.
- BUN Branch Unconditionally
- BSA Branch and Save return Address
- ISZ Increment and Skip if Zero
•Input/output Instructions: Types of instructions are needed for communication
between computer and user.
- INP Input character to AC
- OUT Output Character from AC
Instructions

23. TIMING AND CONTROL
•CPU is Partitioned into ALU and Control Unit.

•The function of control unit is to generate relevant timing and control signals to all
operations in the computer.
•It controls the flow of data between the processor and memory and peripherals.
•The control unit directs the entire computer system to carry out stored program
instructions.
•The control unit instructs the arithmetic logic unit that which logical or arithmetic
operation is to be performed.
•The control unit co-ordinates the activities of the other two units as well as all
peripherals and auxiliary storage devices linked to the computer.
Functions of Control unit :

24. CONTROL UNIT
Instruction codes
•Control unit (CU) of a processor translates from machine instructions to the control
signals (for the micro-operations) that implement them.
•Control units are implemented in one of two organizations/ways:
•Hardwired Control
–CU is made up of sequential and combinational circuits to generate the control signals
•Micro-programmed Control
–A control memory on the processor contains micro-programs that activate the necessary control
signals.
•We will consider a hardwired implementation of the control unit for the Basic
Computer.

25. • Hardwired CU Microprogrammed CU
•Hardwired control unit generates the control
signals using logic circuits.
•It is fast because signals are generated by
Combinational circuits.
•Micro programmed control unit generates the
control signals with the help of micro-instructions
stored in control memory.
•Execute an instruction in micro-program
control unit requires more time.
Difficult to modify as the control signals that
need to be generated are hard wired.
•Easy to modify because design modifications,
corrections are easily possible. Simply
rewriting or modifying the content of memory.


•Cannot handle complex instructions as
the circuit design for it becomes complex
•It can handle complex instructions

26. TIMING AND CONTROL
Hardwired control unit consist of :H
•A Instruction Register : 16-bits in size
•Control Logic gates :
•Two decoders : 3x8 , 4x16
•4-bit sequencer :

27. TIMING AND CONTROL
Control unit of Basic Computer
Timing and control
Instruction register (IR)
15 14 13 12 11 - 0
3 x 8
decoder
7 6 5 4 3 2 1 0
I
D
0
15 14 . . . . 2 1 0
4 x 16
decoder
4-bit
sequence
counter
(SC)
Increment (INR)
Clear (CLR)
Clock
Other inputs
Control
signals
D
T
T
7
15
0
Combinational
Control
logic

28. TIMING AND CONTROL
•Instruction Register (IR) : An instruction read from memory is placed in the
instruction register (IR).
-- The instruction register is divided into three parts:
the I bit (15
th
bit) = addressing modes,
Operation code (Opcode) 3 bits, and
Address part (12 bits).
• First 12-bits (0 -11) of IR are applied to the control logic gates.
• The Operation code bits (12 – 14) are decoded with a 3 x 8 decoder.
•The eight outputs ( D0 - D7) from a decoder goes to the control logic gates to
perform specific operation.
•Last bit 15
th
is transferred to a I flip-flop designated by symbol I.

29. TIMING AND CONTROL
•The 4-bit sequence counter SC can count in binary from 0
- 15.
•The counter output is decoded into 16 timing pulses T0 -
T15.
•The sequence counter can be incremented by INR input
or clear by CLR input synchronously.

30. TIMING SIGNALS
Clock
T0 T1 T2 T3 T4 T0
T0
T1
T2
T3
T4
D3
CLR
SC
- Generated by 4-bit sequence counter and 416 decoder
- The SC can be incremented or cleared.
- Example: T
0
, T
1
, T
2
, T
3
, T
4
, T
0
, T
1
, . . .
Assume: At time T
4
, SC is cleared to 0 if decoder output D3 is active.
D
3
T
4
: SC  0
Timing and control

31. INSTRUCTION CYCLE
•In Basic Computer, a machine instruction is executed in the following cycle:
1.Fetch an instruction from memory
2.Decode the instruction and calculate effective address (EA)
3.Read the EA from memory if the instruction has an indirect address
(Fetch operand)
4. Execute the instruction
•After an instruction is executed, the cycle starts again at step 1, for the next
instruction
•Note: Every different processor has its own (different) instruction cycle

32. FETCH and DECODE
• Fetch and Decode T0: AR PC (S
0
S
1
S
2
=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)
S
2
S
1
S
0
Bus
7
Memory
unit
Address
Read
AR
LD
PC
INR
IR
LD
Clock
1
2
5
Common bus
T1
T0
Instruction Cycle

33. FETCH and DECODE
T0 : AR  PC Register transfer operation
•The content of PC is placed onto Bus and LD (load) input of AR is enabled.
i.e. S
0S
1S
2=010, T0=1
T1: IR  M [AR], PC  PC + 1 Memory read operation, Increment operation
•Instruction read from memory is placed to register IR , and at the same time PC is
Incremented by 1.
i.e. - Read Input of memory is enabled.
- S
0S
1S
2= 111 , content of memory is loaded onto Bus. (M  Bus)
- Content of Bus is loaded to IR, by enabling LD input of IR. (Bus  IR)
- by enabling INR input, PC value is incremented by 1.(PC  PC + 1)
T2 : D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)
•Opcode in IR is decoded, Address part of IR is transferred to AR, 15
th
bit of IR is
transferred to Flip-flop I .

34. DETERMINE THE TYPE OF INSTRUCTION
= 0 (direct)
Instruction Cycle
Start
SC 
ARPC
T0
IRM[AR],PCPC + 1
T1
ARIR(0-11),IIR(15)
Decode Opcode in IR(12-14),
T2
D7
= 0 (Memory-reference) =>opcode ≠ 111(Register or I/O) = 1
II
Execute
register-reference
instruction
SC0
Execute
input-output
instruction
SC0
M[AR]AR Nothing
= 0 (register)(I/O) = 1 (indirect) = 1
T3 T3 T3 T3
Execute
memory-reference
instruction
SC0
T4

35. DETERMINE THE TYPE OF INSTRUCTION
D'7IT3:AR M[AR]
D'7I'T3:Nothing
D7I'T3:Execute a register-reference instruction.
D7IT3:Execute an input-output instruction.
The three instructions types are divided into four separate paths.

36. REGISTER REFERENCE INSTRUCTIONS
r = D
7 I’T
3 => Register Reference Instruction
B
i = IR( I ) , I = 0,1,2,...,11
- control signal D
7
= 1, and I = 0
- Register Ref. Instr. is specified in b
0
~ b
11
of IR
- Execution completed with timing signal T
3
Instruction Cycle
Register Reference Instructions are identified when
r: SC  0
CLArB
11: AC  0
CLErB
10
: E  0
CMArB
9
: AC  AC’
CMErB
8
: E  E’
CIRrB
7: AC  shr AC, AC(15)  E, E  AC(0)
CILrB
6
: AC  shl AC, AC(0)  E, E  AC(15)
INCrB
5
: AC  AC + 1
SPArB
4: if (AC(15) = 0) then (PC  PC+1)
SNArB
3
: if (AC(15) = 1) then (PC  PC+1)
SZArB
2
: if (AC = 0) then (PC  PC+1)
SZErB
1
: if (E = 0) then (PC  PC+1)
HLTrB
0: S  0 (S is a start-stop flip-flop)

37. REGISTER REFERENCE INSTRUCTIONS
CLA : rB
11 AC  0 Clear AC
0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
r = D
7 I’T
3
CLA 7800 Hexadecimal

38. MEMORY REFERENCE INSTRUCTIONS

The effective address of the instruction is in AR and was placed during
timing signal T
2
when I = 0, or during timing signal T
3
when I = 1

Memory cycle is assumed to be short enough to complete in a CPU cycle

The execution of M-R instruction starts with T
4
MR Instructions
Symbol
Operation
Decoder
Symbolic Description
AND D
0
AC  AC  M[AR]
ADD D
1
AC  AC + M[AR], E  C
out
LDA D
2
AC  M[AR]
STA D
3 M[AR]  AC
BUN D
4
PC  AR
BSA D
5
M[AR]  PC, PC  AR + 1
ISZ D
6
M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1

39. AND to AC
D
0
T
4
:DR  M[AR] Read operand
D
0T
5:AC  AC  DR, SC  0 AND with AC
Control function for the above instruction is D
0,
and two timing signals T
4
and T
5

At T
4
: Operand transfer from memory to DR
T
5
: Result of AND operation between the contents of DR

and AC is
transferred to AC
,
at the same clock SC is cleared to 0.


MEMORY REFERENCE INSTRUCTIONS
The execution of the memory-reference instructions starts with timing signal
T4.•

40. LDA: Load to AC (transfers the memory word specified by the effective address to AC .)
D
2
T
4
:DR  M[AR] Read operand
D
2T
5:AC  DR, SC  0 Operand transferred to AC
STA: Store AC (stores the content of AC into the memory word)
D
3
T
4
:M[AR]  AC, SC  0 Memory write
BUN: Branch Unconditionally (transfers the program to the instruction specified by the EA)
D
4T
4:PC  AR, SC  0
ADD to AC
D
1T
4:DR  M[AR] Read operand
D
1T
5:AC  AC + DR, E  C
out, SC  0Add to AC and store carry in E flip flop
MEMORY REFERENCE INSTRUCTIONS

41. Subroutine Call :

BSA instruction is termed as subroutine call

Useful for branching to a portion of the program.

It stores the address of next instruction in sequence.
Memory, PC after execution
21
0BSA 135
Next instruction
Subroutine
20
PC = 21
AR = 135
136
1BUN 135
Memory, PC, AR at time T4
0BSA 135
Next instruction
Subroutine
20
21
135
PC = 136
1BUN 135

42. MEMORY REFERENCE INSTRUCTIONS
Memory, PC after execution
21
0BSA 135
Next instruction
Subroutine
20
PC = 21
AR = 135
136
1BUN 135
Memory, PC, AR at time T4
0BSA 135
Next instruction
Subroutine
20
21
135
PC = 136
1BUN 135
Memory Memory
BUN: Branch Unconditionally
D
4T
4:PC  AR, SC  0
BSA: Branch and Save Return Address
D
5
T
4
:M[AR]  PC, AR  AR + 1
D
5T
5:PC  AR, SC  0
M[135] ← 21, PC ← 135 + 1 = 136

43. MEMORY REFERENCE INSTRUCTIONS
MR Instructions
ISZ: Increment and Skip-if-Zero

Increment the word specified by EA.

Programmer stores -ve number in memory word, if -ve number
incremented by 1, eventually reaches to 0.

Since increment of word is not possible inside memory, so read the word
into DR, increment DR, and store back into memory.
Microoperations:
D
6T
4:DR  M[AR] Memory read the word
D
6
T
5
:DR  DR + 1 increment DR
D
6
T
6
:M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0

44. FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS
MR Instructions
Memory-reference instruction
DR  M[AR] DR  M[AR] DR  M[AR]
M[AR]  AC
SC  0
AND ADD LDA STA
AC  AC DR
SC  0
AC  AC + DR
E  Cout
SC  0
AC  DR
SC  0
D T
04
D T
14
D T
24
D T
34
D T
05
D T
15
D T
25
PC  AR
SC  0
M[AR]  PC
AR  AR + 1
DR  M[AR]
BUN BSA ISZ
D T
44
D T
54
D T
64
DR  DR + 1
D T
55
D T
65
PC  AR
SC  0
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0
D T
66


45. INPUT-OUTPUT AND INTERRUPT
• Input-Output Configuration
•The terminal sends and receives serial information
•The serial info. from the keyboard is shifted into INPR
•The serial info. for the printer is stored in the OUTR
•INPR and OUTR register communicate with the terminal serially and with the
AC in parallel.
•The flags are needed to synchronize the timing difference between I/O device
and the computer.
A Terminal with a keyboard and a Printer
I/O and Interrupt
Input-output
terminal
Serial
communication
interface
Computer
registers and
flip-flops
Printer
Keyboard
Receiver
interface
Transmitter
interface
FGOOUTR
AC
INPR FGI
Serial Communications Path
Parallel Communications Path

46. Input Register(INPR): It has 8-bits in size and holds an alphanumeric data.
FGI = 0 , INPR not holding Data.
FGI = 1, INPR holds new alphanumeric data.

if FGI = 1, Computer transfer the data from INPR to AC in parallel and Clears
the Flag FGI = 0.
Now INPR is ready to take another value from input devices.
Output Register(OUTR): working method is similar to INPR but information flow in
reverse direction.

Computer checks if the flag FGO=1, Information from AC is transferred parallely
to OUTR and FGO is cleared to ‘0’.

If FGO = 0, computer does not load data into OUTR(shows device is busy
executing operation).

After completion of operation, Output device accepts data from OUTR and, set
FGO = 1.
INPUT-OUTPUT CONFIGURATION

47. INPUT-OUTPUT INSTRUCTIONS
p:SC  0 Clear SC
INPpB
11:AC(0-7)  INPR, FGI  0 Input char. to AC
OUTpB
10:OUTR  AC(0-7), FGO  0 Output char. from AC
SKIpB
9
:if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKOpB
8
:if(FGO = 1) then (PC  PC + 1) Skip on output flag
IONpB
7:IEN  1 Interrupt enable on
IOFpB
6
:IEN  0 Interrupt enable off
Input -output instructions: are needed for transferring data to and from AC,
checking flag bits, and controlling the interrupt signal.
Opcode = 1111
t D
7IT
3 = p(common to all I/O instructions) I
IR(i) = B
i, (IR(6 -11) bit specifies the instructions)
nstructidre

48. IOF pB
6
:IEN  0 F040 (HEX) Interrupt enable off
INPUT-OUTPUT INSTRUCTIONS
1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bitwise representation

49. PROGRAM-CONTROLLED INPUT/OUTPUT
• Program-controlled I/O
- Continuous CPU involvement
I/O takes valuable CPU time to check the flag status.
- Communication slowed down between CPU and I/O devices.
- Flow of Data transfer is Inefficient.
- CPU is wasting time while checking Flag instead doing other
useful work.
I/O and Interrupt

50. PROGRAM-CONTROLLED INPUT/OUTPUT
• Program-controlled I/O
- Continuous CPU involvement
I/O takes valuable CPU time to check the flag status.
- Communication slowed down between CPU and I/O devices.
- Flow of Data transfer is Inefficient.
- CPU is wasting time while checking Flag instead doing other
useful work.
I/O and Interrupt
Alternative to the above one is to Let the external device (I/O device) inform the Computer
when it is ready for the transfer.

51. INTERRUPT INITIATED INPUT/OUTPUT
- It open communication only when some data has to be passed --> interrupt.
- The I/O interface, instead of the CPU, monitors the I/O device.
- When the interface founds that the I/O device is ready for data transfer,
it generates an interrupt request to the CPU.
- Upon detecting an interrupt, the CPU stops momentarily the task it is doing,
branches to the service routine to process the data transfer, and then returns to the
task it was performing.
* IEN (Interrupt-enable flip-flop)
- can be set and cleared by instructions(ION, IOF)
- when cleared, the computer cannot be interrupted.

52. INTERRUPT INITIATED INPUT/OUTPUT
* IEN (Interrupt-enable flip-flop)
- can be set and cleared by instructions(ION, IOF)
- when cleared, the computer cannot be interrupted.
An flip flop R is included in Computer for check the interrupt generated by I/O devices
• If R = 0, CPU go for Instruction cycle
• At Execute phase, IEN is checked ,
-- if IEN = 0, No interrupt and continue with the next instruction cycle.
-- If IEN = 1, Checks the flag bit,
-- if Both (FGI and FGO) are 0, continue with next instruction
cycle.
-- If Either flag is set to 1, set R =1
goes for interrupt cycle.

53. FLOWCHART FOR INTERRUPT CYCLE
I/O and Interrupt
- The interrupt cycle is a HW implementation of a branch and save return address
operation.
- At the beginning of the next instruction cycle, the instruction that is read from memory is
in address 1.
- At memory address 1, the programmer must store a branch instruction that sends the
control to an interrupt service routine.
- The instruction that returns the control to the original program is "indirect BUN 0"

54. REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE


After interrupt cycle
0BUN 1120
0
1
PC = 256
255
1BUN 0
Before interrupt
Main
Program
1120
I/O
Program
0BUN 1120
0
PC = 1
256
255
1BUN 0
Memory
Main
Program
1120
I/O
Program
256
I/O and Interrupt
When control reaches T0 and if R = 1, it proceeds with interrupt cycle.

Content of PC(256) is stored in location ‘ 0”

PC = 1, R = 0

Next cycle instruction read from location ‘1’.

That initiate program at address 1120.

Program checks flag and transfer the input or output data.

After completion, ION instruction is executed to set IEN = 1(to enable further interrupt).

55. Interrupt Cycle
List of Register transfer statement for interrupt cycle:
R F/F  1 if IEN (FGI + FGO)T
0
’ T
1
’

T
2

 T
0
’ T
1
’

T
2
(IEN)(FGI + FGO): R  1

Flip-flop R =1 , Interrupt initiated

Means if IEN = 1, and either FGI or FGO = 1

The symbol + designates a logic OR operation. All these ANDed with
with IEN and T
0
’ T
1
’

T
2

The fetch and decode phase of interrupt cycle
must be modified Replace T
0
, T
1
, T
2
with R'T
0
, R'T
1
, R'T
2
- The interrupt cycle :
RT
0
:AR  0, TR  PC
RT
1
:M[AR]  TR, PC  0
RT
2:PC  PC + 1, IEN  0, R  0, SC  0

56. COMPLETE COMPUTER DESCRIPTION
Flowchart of Operations
Description
=1 (I/O) =0 (Register) =1(Indir) =0(Dir)
start
SC  0
R
AR  PC
R’T
0
IR  M[AR], PC  PC + 1
R’T
1
AR  IR(0~11), I  IR(15)
D
0
...D
7
 Decode IR(12 ~ 14)
R’T
2
AR  0, TR  PC
RT
0
M[AR]  TR, PC  0
RT
1
PC  PC + 1, IEN  0
R  0, SC  0
RT
2
D
7
I I
Execute
I/O
Instruction
Execute
RR
Instruction
AR <- M[AR] Idle
D
7IT
3 D
7I’T
3 D
7
’IT3

D
7
’I’T3
Execute MR
Instruction
=0(Instruction =1 (interrupt
Cycle) Cycle)
=1(Register or I/O) =0(Memory Ref)
D
7
’T4
IEN
FGI
FGO
=1
=1
=1
=0
=0
=0
R  1

57. COMPLETE COMPUTER DESCRIPTION
Microoperations
Description
Fetch
Decode
Indirect
Interrupt

Memory-Reference
AND
ADD
LDA

STA
BUN
BSA
ISZ
RT
0:
RT
1:
RT
2:
D
7IT
3:
RT
0
:
RT
1
:
RT
2
:
D
0T
4:
D
0
T
5
:
D
1
T
4
:
D
1
T
5
:
D
2
T
4
:
D
2
T
5
:
D
3
T
4
:
D
4
T
4
:
D
5
T
4
:
D
5
T
5
:
D
6
T
4
:
D
6
T
5
:
D
6
T
6
:
AR  PC
IR  M[AR], PC  PC + 1
D0, ..., D7  Decode IR(12 ~ 14),
AR  IR(0 ~ 11), I  IR(15)
AR  M[AR]
R  1
AR  0, TR  PC
M[AR]  TR, PC  0
PC  PC + 1, IEN  0, R  0, SC  0
DR  M[AR]
AC  AC  DR, SC  0
DR  M[AR]
AC  AC + DR, E  C
out, SC  0
DR  M[AR]
AC  DR, SC  0
M[AR]  AC, SC  0
PC  AR, SC  0
M[AR]  PC, AR  AR + 1
PC  AR, SC  0
DR  M[AR]
DR  DR + 1
M[AR]  DR, if(DR=0) then (PC  PC + 1),
SC  0
T
0
T
1
T
2
(IEN)(FGI + FGO):

58. Register-Reference
CLA
CLE
CMA
CME
CIR
CIL
INC
SPA
SNA
SZA
SZE
HLT
Input-Output
INP
OUT
SKI
SKO
ION
IOF
D
7
IT
3
= r
IR(i) = B
i

r:
rB
11
:
rB
10
:
rB
9
:
rB
8
:
rB
7
:
rB
6
:
rB
5
:
rB
4
:
rB
3
:
rB
2
:
rB
1
:
rB
0
:
D
7
IT
3
= p
IR(i) = B
i
p:
pB
11:
pB
10:
pB
9:
pB
8:
pB
7:
pB
6:
(Common to all register-reference instr)
(i = 0,1,2, ..., 11)
SC  0
AC  0
E  0
AC  AC
E  E
AC  shr AC, AC(15)  E, E  AC(0)
AC  shl AC, AC(0)  E, E  AC(15)
AC  AC + 1
If(AC(15) =0) then (PC  PC + 1)
If(AC(15) =1) then (PC  PC + 1)
If(AC = 0) then (PC  PC + 1)
If(E=0) then (PC  PC + 1)
S  0
(Common to all input-output instructions)
(i = 6,7,8,9,10,11)
SC  0
AC(0-7)  INPR, FGI  0
OUTR  AC(0-7), FGO  0
If(FGI=1) then (PC  PC + 1)
If(FGO=1) then (PC  PC + 1)
IEN  1
IEN  0
Description
COMPLETE COMPUTER DESCRIPTION
Microoperations

59. DESIGN OF BASIC COMPUTER(BC)
Hardware Components of BC
A memory unit: 4096 x 16.
Registers:
AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
Flip-Flops(Status):
I, S, E, R, IEN, FGI, and FGO
Decoders: a 3x8 Opcode decoder
a 4x16 timing decoder
Common bus: 16 bits
Control logic gates:
Adder and Logic circuit: Connected to AC
Control Logic Gates
- Input Controls of the nine registers
- Read and Write Controls of memory
- Set, Clear, or Complement Controls of the flip-flops
- S
2
, S
1
, S
0
Controls to select a register for the bus
- AC, and Adder and Logic circuit
Design of Basic Computer

60. CONTROL OF REGISTERS AND MEMORY
Scan all of the register transfer statements that change the content of AR:
LD(AR) = R'T
0 + R'T
2 + D'
7IT
3
CLR(AR) = RT
0
INR(AR) = D
5T
4
Address Register: AR
R’T
0
: AR  PC LD(AR)
R’T
2: AR  IR(0-11) LD(AR)
D’
7
IT
3
: AR  M[AR] LD(AR)
RT
0
: AR  0 CLR(AR)
D
5
T
4
: AR  AR + 1 INR(AR)
Design of Basic Computer

61. CONTROL OF REGISTERS AND MEMORY
Address Register: AR
Design of Basic Computer
Logic gate structure associated with the control inputs of AR AR
of AR
LD(AR) = R'T
0
+ R'T
2
+ D'
7
IT
3
CLR(AR) = RT
0
INR(AR) = D
5T
4

62. CONTROL OF FLAGS
pB
7: IEN  1 (I/O Instruction)
pB
6
: IEN  0 (I/O Instruction)
RT
2
: IEN  0 (Interrupt)
p = D
7IT
3 (Input/Output Instruction)
IEN: Interrupt Enable Flag
Design of Basic Computer

63. CONTROL OF COMMON BUS
x1 for placing AR onto bus
D
4T
4: PC  AR
D
5
T
5
: PC  AR
x1 = D
4T
4 + D
5T
5
Design of Basic Computer
x1
x2
x3
x4
x5
x6
x7
Encoder
S
2
S
1
S
0
Multiplexer
bus select
inputs
x1 x2 x3 x4 x5 x6 x7S2 S1 S0
selected
register
0 0 0 0 0 0 0 0 0 0 none
1 0 0 0 0 0 0 0 0 1 AR
0 1 0 0 0 0 0 0 1 0 PC
0 0 1 0 0 0 0 0 1 1 DR
0 0 0 1 0 0 0 1 0 0 AC
0 0 0 0 1 0 0 1 0 1 IR
0 0 0 0 0 1 0 1 1 0 TR
0 0 0 0 0 0 1 1 1 1 Memory

64. CONTROL FOR MEMORY R/W
The Combinational Logic gate generates x
7
must applied to READ input of Memory unit.
X
7
= R’T
1
+ D’
7
I T
3
+ (D
0
+ D
1
+ D
2
+ D
6
) T
4
Memory READ
X
7
= RT
1
+ (D
3
+ D
5
)T
4
+ D
6
T
6
Memory WRITE

65. DESIGN OF ACCUMULATOR LOGIC
Circuits associated with AC
All the statements that change the content of AC
Design of AC Logic
16
16
8
Adder and
logic
circuit
16
AC
From DR
From INPR
Control
gates
LDINRCLR
16
To bus
Clock
D
0
T
5
:AC  AC  DR AND with DR
D
1
T
5
:AC  AC + DR Add with DR
D
2
T
5
:AC  DR Transfer from DR
pB
11
:AC(0-7)  INPR Transfer from INPR
rB
9
:AC  AC Complement
rB
7
:AC  shr AC, AC(15)  E Shift right
rB
6
:AC  shl AC, AC(0)  E Shift left
rB
11
:AC  0 Clear
rB
5
:AC  AC + 1 Increment

66. CONTROL OF AC REGISTER
Gate structures for controlling the LD, INR, and CLR of AC
AC
LD
INR
CLR
Clock
To bus
16
From Adder
and Logic
16
AND
ADD
DR
INPR
COM
SHR
SHL
INC
CLR
D
0
D
1
D
2
B
11
B
9
B
7
B
6
B
5
B
11
r
p
T
5
T
5
Design of AC Logic

67. ALU (Adder & Logic Circuits)
Design of AC Logic
The ALU can be subdivided into 16 stages, with each stage corresponding to one bit of AC.

68. Numerical Examples
Q1. A computer uses a memory unit with 256k words of 32 bits each. A binary instruction code is
stored in one word of memory. The instruction has four parts: an indirect bit, an opcode, a
register code part to specify one of 64 registers, and an address part.
a)How many bits are there in the opcode, the register code part, and the address part ?
b)Draw the instruction word format and indicate the number of bits in each part ?
c)How many bits are there in the data and address inputs of the memory ?

69. Numerical Examples
Q3. Draw the block diagram for the hardware that implements the following statements:

x + yz : AR <-- AR + BR,
where AR, BR are two n-bit registers, x, y, z are control variables,
Include the logic gates for the control function. ( + symbol designates OR operation in control
function but it represents addition operation in arithmetic micro operation).

70. Numerical Examples
Q3: Write and explain all the register transfer statements to perform the micro-operation Branch
and Save the return address.

71. Micro-programmed Control (Control Memory) Unit program
example, Design of control unit.
• Microinstruction: Each word in control memory contains within it a microinstruction.
• Microoperation: A microinstruction specifies one or more microoperations.
• Microprogram: A sequence of microinstructions forms what is called a microprogram.
• A computer that employs a microprogrammed control unit will have two separate
memories:
1. The main memory: This memory is available to the user for storing programs. The
user's program in the main memory consists of machine instructions and data.
2. The control memory: This memory contains a fixed microprogram that cannot be
altered by the user. The microprogram consists of microinstructions that specify various
internal control signals for the execution of register microoperations.

72. • Block diagram of the microprogrammed control unit

73. Next Address Generator (Sequencer):
It is used to generate the address of the next instruction to compute. The microinstruction
contains bits to initiate the micro-operations and bits to determine the address sequence for
control memory.
The next address can be determined as
- Loading an initial address to start the control operations.
- Incrementing the control address register
- Loading an address from the control memory
- Transferring an external address.

74. •Control Address Register: It is used to hold the address of the instruction to be executed. It passes
the address to the control memory.
• Control Data Register: It is holding the present microinstruction. It is also called the Pipeline
register. It allows the execution of the microoperations specified by the control word simultaneously
with the generation of the next microinstruction.
•Control Memory: Control Memory is the storage in the microprogrammed control unit to store the
microprogram. It is a ROM in which all control information is permanently stored.
•The microinstruction contains a control word that specifies one or more microoperations for the data
processor. Once these operations are executed, the control must determine the next address
•Advantage: Once the hardware configuration is established no need for further hardware or wiring
changes. For different control sequence a different set of microinstructions is used in control memory

75. Address Sequencing
•Microinstructions are usually stored in groups where each group specifies a
routine, where each routine specifies how to carry out an instruction.
•Each routine must be able to branch to the next routine in the sequence.
•An initial address is loaded into the CAR when power is turned on; this is usually
the address of the first microinstruction in the instruction fetch routine.
•Next, the control unit must determine the effective address of the instruction

76. Mapping
•The next step is to generate the microoperations that executed the instruction.
•This involves taking the instruction’s opcode and transforming it into an address for the
instruction’s microprogram in control memory. This process is called mapping.
•While microinstruction sequences are usually determined by incrementing the CAR, this is not
always the case. If the processor’s control unit can support subroutines in a microprogram, it will
need an external register for storing return addresses.
•When instruction execution is finished, control must be return to the fetch routine. This is done using
an unconditional branch.
• Addressing sequencing capabilities of control memory include:
– Incrementing the CAR
– Unconditional and conditional branching (depending on status bit).
– Mapping instruction bits into control memory addresses
– Handling subroutine calls and returns.

78. •Conditional Branching
• Status bits
• – provide parameter information such as the carry-out from the adder, sign of a number, mode bits of an instruction, etc.
• – control the conditional branch decisions made by the branch logic together with the field in the microinstruction that
specifies a branch address.
•Branch Logic
• Branch Logic - may be implemented in one of several ways: –
•The simplest way is to test the specified condition and branch if the condition is true; else increment
the address register.
• – This is implemented using a multiplexer:
• If the status bit is one of eight status bits, it is indicated by a 3-bit select number.
• If the select status bit is 1, the output is 0; else it is 0.
•A 1 generates the control signal for the branch; a 0 generates the signal to increment the CAR.
• Unconditional branching occurs by fixing the status bit as always being 1.

79. Mapping of Instruction
•Branching to the first word of a microprogram is a special type of
branch. The opcode of the instruction indicates the branch.
•The mapping scheme shown in the figure allows for four
microinstructions as well as overflow space from 1000000 to
1111111. Mapping of Instruction Code to Microoperation address

80. Subroutines
•Subroutine calls are a special type of branch where we return to one
instruction below the calling instruction.
•Provision must be made to save the return address, since it cannot be
written into ROM

81. References:
Book: Computer System Architecture, Third Edition, M. Morris Mano