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1. IN THE NAME OF ALLAH

2. ROSEN QUEEN`S IQRA IRSHAD MAHEEN ARIF EMAN NOOR UQBA NISAR MARYAM SHEHZAD ZOHA AMIR 33 01 47 19 28 06

3. INSTRUCTIONS PIPELINE An instruction pipeline is a technique used in design of computers to increase their instruction throughput (number of instructions executed per unit time) In instruction pipeline a stream of instructions can be executed in an overlapping manner. Instruction pipelining is used to achive instructions level parallism within a single processor.

4. In instructions pipelining these steps of many instruction can be carried out simultaneously in an overlapped manner to reduced the overall execution time. If pipeline made up of more stages then we get more throughput of time CPU. INSTRUCTION PIPELINE Insruction fetch Decode instruction Operand fetch Execute and wite back the result Instruction fetch Decode instruction Operand fetch Execute Write back Instruction fetch Decode instruction Calculate effecting of operands Fetch operand Execute Write back

5. SIX STAGES OF INSTRUCTION PIPELINE If the instrution processing is split into six phases the instruction pipeline will how six different for the execution of these phases STAGES: S1 – Fetch instruction S2 – Decode instruction S3 – Calculate operand S4 – Fetch operand S5 – Execute instructions S6 – Write back

6. Fetch instruction: Instructions are fetched from the memory into a temporary buffer before it gets executed. 2. Decode instruction : Instruction is decoded by the CPU so that he necessary op codes (operation) and operands can be determined. 3. Calculate effective address: In this stage based on the addressing scheme used either operands are directly provided in the instructions or the effective adress has to be calculated.

7. 5. Execute instructions: In this stage execution of instruction takes place. 6. Write back: In this stage the result from the execution of instruction shared or written back in the memory or register . F I D I C O F O E I W B 4. Fetch operand: In this stage operands are fetched from the adress calculated in stage 3.

8. TYPES OF PIPELINE DELAY The pipeline delay is of two types which are discribed as follows : UNIFORM DELAY PIPELINE: All the stages in a uniform delay pipeline will complete their operations by taking the same time. The cycle time in this pipeline is discribed as follows: CYCLE TIME (TP) = STAGE DELAY If there are buffers between the stages, then the cycle time will be discribed as follows: CYCLE TIME (TP) = STAGE DELAY + BUFFER DELAY

9. 2.NON UNIFORM DELAY PIPELINE: All the stages in a non uniform delay pipeline will complete their operations by taking different times. The cycle time in this pipeline is discribed as follows: CYCLE TIME (TP) = MAXIMUM (STAGE DELAY) FOR EXAMPLE: Suppose we have foue stages which contain stage delay as 1 ns, 2 ns, 3ns, and 4 ns. In this case the cycle time will be: TP = MAXIMUM (1ns, 2ns, 3ns, 4ns) =4ns If there are buffers between the stages then the cycle time will be discribed as follows: CYCLE TIME (TP) = MAXIMUM (STAGE DELAY + BUFFER)

10. Frequency: The number of waves or vibrations that passes in one unit of time. Formula: f=1/T

11. ADVANTAGES OF PIPELININIG Instruction throughput increases. Increase in the number of pipeline stages increase the number of instructions executed simultaneously. Faster ALU can be designed when pipelining is used. Pipelining increases the overall performance of the CPU.

12. DISADVANTAGES OF PIPELINING Designing of the pipelined processor is complex. Instructions latency increases in pipelined processors. The throughput of a pipelined processor is difficult to predict. The longer the pipeline, worse the problem of hazard for branch instructions.

13. NAME MAHEEN ARIF ROLL NO; 01 SUBJECT COMPUTER ORGANIZATION AND DESIGN TOPIC DIFFERENCE BETWEEN PIPELINE AND NON PIPELINE

14. Pipeline VS Non Pipeline Pipeline Non pipeline Many instructions are executed at the same time. Only one instruction is executed at the same time. Execution time is comparatively less. Execution takes more time. Less and execution is done in a fewer cycle. More numbers of cycles comparatively Low user response time. High user response time. Decrease the performance of C.P.U. Increase the performance of C.P.U.

15. IF IF IF ID ID ID IE IE IE WB WB WB Stage 1 Stage 2 Stage 3 Stage 4 2 3 4 5 6 7 8 PIPELINE

16. NON PIPELINE IF IF IF ID ID ID IE IE IE WB WB WB Stage 1 Stage 2 Stage 3 Stage 4 1 2 3 4 5 6 7 8 9 10 11 12

17. Example of pipelining F F F T T T P P P 10 20 30 40 50 60 70 80 90 100 Stage 1 Stage 2 Stage 3 Circle cycle F=Cycle frame, T=Cycle tyre , P=Paint

18. Example of nonpipelining F F F T T T P P P 10 20 30 40 50 60 70 80 90 100 Stage 1 Stage 2 Stage 3 Circle Cycle

19. INSTRUCTION SET

20. Instruction set: A set of instructions that a CPU can perform is called instruction set. Different types of CPU can execute different types of instruction sets. Modern CPU can execute 80 to 120 instruction. Types of instruction: Data transfer instructions Arithmatic and logical instructions I/O instruction Control transfer instruction

21. Data transfer instructions: The instructions used to transfer data from one component to another componenet during the program execution are called data transfer instructions. Programmer can use these instruction to move data from CPU to main memory.

22. Arithmetic and logical instructions: The instruction used to perform arithmatic operations are called arithmatic instruction.different arithmatic operations are: ADDITION + SUBTRACTION- MULTIPLICATION* DEVISION/ The instructions used to perform logical operations are called logical instruction. Differnt logical instructions are: LESS THAN< GREATER THAN> EQUAL TO=

23. I/O instructions: Every CPU provides the operations of reading data from peripheral devices and writing data to peripheral devices. Peripheral devices means input and output devices such as keyboard, muse and monitor.

24. Control transfer instruction: The instruction used to change the sequence of instructions of the program are called control transfer instructions.

25. IMPORTANCE OF INSTRUCTION SET Efficiency: Determines how efficeintly instructions are executed. Compatibility: Defines which software can run on the processor. Hardware Utilization: Influences power consumption and resource allocation.

26. Programming Ease: Affects how easy it is to write and optimize code. Extensions: Allows for specialized instructions for specific tasks. Portability: Enables software to run across different hardware platforms. Future-Proofing: Ensures compatibility with emerging technologies.

27. Security: Includes features to protect against vulnerabilities. Performance Optimization: Directly impacts processor speed and efficiency. Ecosystem Support: Enhances overall value through development tools and community resources.