Computer organization and Architecture Addition&Subtraction.pptx

Computer organization and Architecture Module 1 arithmetic operations and compliments

1. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Computer Organization & Architecture MVJ19IS43 Module:4 Prepared by: PROF. SNEH , AP, Dept of ECE, MVJCE

2. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Course objective is to: • Distinguish between the various ISA styles. • Trace the execution sequence of an instruction through the processor • Compare different approaches used for implementing a functional unit. • Understand the fundamentals of memory and I/O systems and their interaction with the processor.

3. Course Code Course Outcome CO1 Demonstrate the fundamental organization of a computer system. CO2 Analyze various issues related to memory hierarchy. CO3 Examine various, inter connection structures of multi processors. CO4 Formulate and solve problems related to computer arithmetic, performance of systems CO5 Demonstrate parallel computing and concepts of pipeline. COURSE OUTCOME :

4. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Reference Books: 1. M. Morris Mano, Computer System Architecture, 3rd edition, Prentice- Hall of India Pvt. Ltd.,1999. 2. Carl Hamacher : “Computer Organization ”, Fifth Edition, Mc Graw Hill 3. William Stallings: “Computer Organization and Architecture”, Pearson Education

5. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Content Addition and subtraction, multiplication Algorithms, Division Algorithms, Floating – point Arithmetic operations. Decimal Arithmetic unit Decimal Arithmetic operations.

6. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC BRIDGE COURSE TOPICS Basics of Computers - Number System The technique to represent and work with numbers is called  number system .  Decimal number system  is the most common number system. Other popular number systems include  binary number system, octal number system, hexadecimal number system,  etc. Decimal Number System Decimal number system is a  base 10  number system having 10 digits from 0 to 9. This means that any numerical quantity can be represented using these 10 digits. Decimal number system is also a  positional value system . 

7. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC BRIDGE COURSE TOPICS Binary Number System The easiest way to vary instructions through electric signals is two-state system – on and off. On is represented as 1 and off as 0, though 0 is not actually no signal but signal at a lower voltage. The number system having just these two digits – 0 and 1 – is called  binary number system . Each binary digit is also called a  bit . Binary number system is also positional value system, where each digit has a value expressed in powers of 2, as displayed here. re each digit has a value expressed in powers of 2, as displayed here.                                  

8. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC BRIDGE COURSE TOPICS Octal Number System Octal number system  has eight digits – 0, 1, 2, 3, 4, 5, 6 and 7. Octal number system is also a positional value system with where each digit has its value expressed in powers of 8, as shown here − Hexadecimal Number System Octal number system  has 16 symbols – 0 to 9 and A to F where A is equal to 10, B is equal to 11 and so on till F. Hexadecimal number system is also a positional value system with where each digit has its value expressed in powers of 16, as shown here −

9. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Signed Integer 3 major representations: Sign and magnitude One’s complement Two’s complement Assumptions: 4-bit machine word 16 different values can be represented Roughly half are positive, half are negative

10. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Sign and Magnitude Representation High order bit is sign: 0 = positive (or zero), 1 = negative Three low order bits is the magnitude: 0 (000) thru 7 (111) Number range for n bits = +/-2 n-1 -1 Two representations for 0

11. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC One’s Complement Representation Subtraction implemented by addition & 1's complement Still two representations of 0! This causes some problems Some complexities in addition

12. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Two’s Complement Representation Only one representation for 0 One more negative number than positive number like 1's comp except shifted one position clockwise

13. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Binary, Signed-Integer Representations 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + 1 - 2 + 3 + 4 + 5 + 6 + 7 + 2 - 3 - 4 - 5 - 6 - 7 - 8 - + - 1 + 2 + 3 + 4 + 5 + 6 + 7 + + 7 - 6 - 5 - 4 - 3 - 2 - 1 - - 1 + 2 + 3 + 4 + 5 + 6 + 7 + + 7 - 6 - 5 - 4 - 3 - 2 - 1 - b 3 b 2 b 1 b Sign and magnitude 1' s complement 2' s complement B V alues represented Figure 2.1. Binary, signed-integer representations.

14. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Addition and Subtraction of Signed-Magnitude Data We designate the magnitude of the two numbers by A and B. When the signed numbers are added or subtracted, we find that there are eight different conditions to consider, depending on the sign of the numbers and the operation performed. These conditions are listed in the Table. The algorithms for addition and subtraction are derived from the table.

15. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC

16. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Rules for addition and subtraction using signed magnitude When the signs of A and B are same, add the two magnitudes and attach the sign of result is that of A. When the signs of A and B are not same, compare the magnitudes and subtract the smaller number from the larger. And give the sign of larger magnitude to the result. If the two magnitudes are equal, subtract B from A and make the sign of the result will be positive.

17. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Hardware for signed magnitude addition and subtraction

18. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Example For addition: add A+B +3 0011 +2 0010 …………………… +5 0101 For subtraction: add A+B’ +1 +3 0011 -2 1110 …………………….. +1 00 01

19. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Hardware Implementation It consists of registers A and B and sign flip-flops A s and B s , subtraction is done by adding A to the 2’s complement of B. The output carry is transferred to flip flop E, where it can be checked to determine the relative magnitudes of the two numbers. The add-overflow flip-flop AVF holds the overflow bit when A and B are added. The addition of A plus B is done through the parallel adder. The S(sum) output of the adder is applied to the input of the A register. The complementor provides an output of B or the complement of B depending on the state of the mode control M. The M signal is also applied to the input carry of the adder. When M=0, the output of B is transferred to the adder, the input carry is 0, and the output of the adder is equal to the sum A + B. When M=1, the 1’s complement of B is applied to the adder, the input carry is 1, and output S= A + B’ +1.

20. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC

21. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Flowchart for add and subtract operations The two signs A s and B s are compared by an XOR gate. If the output of the gate is 0, the signs are identical; if it is 1, the signs are different. For an add operation, identical signs dictate that the magnitudes be added. For a subtract operation, different signs dictate that the magnitudes be added. The magnitudes are added with a micro operation EA ← A+B, where EA is a register that combines E and A. The carry in E after the addition constitutes an overflow if it is equal to 1. the value of E is transferred into the add-overflow flip flop AVF. The two magnitudes are subtracted if the signs are different for an add operation or identical for a subtract operation. The magnitudes are subtracted by adding A to the 2’s complement of B. No overflow can occur if the numbers are subtracted to AVF is cleared to 0. A 1 in E, indicates that A ≥ B and the number in A is the correct result. If this number is zero, the sign A, must be made positive to avoid a negative zero. A 0 in E indicates that A < B.

22. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Example (+8) + (-3)=+5 (-8) +(-3)=-11 (+8) - (-3)=+11 (-8) - (-3)=-5

23. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Addition and subtraction with Signed- 2’s Complement Data 23 Hardware for signed-2’s Complement addition and subtraction

24. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Hardware for signed-2’s Complement addition and subtraction AC and BR are the registers to hold the numbers. The leftmost bit in AC and BR represent the sign bits of the numbers. The two sign bits are added or subtracted together with the other bits in the complementer and parallel adder. The overflow flip flop V is set to 1 if there is an overflow.

25. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Algorithm

26. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Algorithm The sum is obtained by adding the contents of AC and BR. The overflow bit V is set to 1 if the exclusive OR of the last two carries is 1, and it is cleared to 0 otherwise. The subtraction operation is accomplished by adding the content of AC to the 2’s complement of BR. Taking the 2’s complement of BR has the effect of changing a positive number to negative, and vice versa.

27. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Rules for addition using 2’s complement When two negative numbers are added a carry will be generated from the sign bit which will be discarded. 2’s complement of the magnitude bits of the operation will be the final sum.

28. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Rules for subtraction using 2’s complement At first, 2’s complement of the negative number is found. Then it is added to the other number. If the final carry over of the sum is 1, it is dropped, and the result is positive. If there is no carry over, the two’s complement of the sum will be the result and it is negative.

29. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Example +3 0 011 + +2 0 010 …………………… +5 0101 -3 1 101 + -2 1 110 ……………………….. -5 1 0 11 +3 0011 - + 2 1110 ( 2’s complement ) …………………………. +1 001 - 3 1101 - -2 0010 ……………………….. -1 1 1 11

30. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Addition and Subtraction – 2’s Complement 4 + 3 7 0100 0011 0111 -4 + (-3) -7 1100 1101 11001 4 - 3 1 0100 1101 10001 -4 + 3 -1 1100 0011 1111 If carry-in to the high order bit = carry-out then ignore carry if carry-in differs from carry-out then overflow Simpler addition scheme makes twos complement the most common choice for integer number systems within digital systems

31. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC Overflow Conditions 5 2 7 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 1 -3 -5 -8 1 1 1 1 1 1 0 1 1 0 1 1 1 1 0 0 0 No overflow No overflow Overflow when carry-in to the high-order bit does not equal carry out

32. Approved by AICTE |Affiliated to VTU | Recognized by UGC with 2(f) & 12(B) status |Accredited by NBA and NAAC EXAMPLE-2’S COMPL ADD ( 28) AND (15) ADD (28) AND (-15)