CXL Memory Expansion, Pooling, Sharing, FAM Enablement, and Switching

During the CXL Forum at OCP Global Summit, Tam Do and Sanketh Srinivas of Microchip provide an overview of the company's portfolio of CXL products.

1. Tam Do, Product Marketing, Microchip Sanketh Srinivas, Product Marketing, Microchip CXL Memory Expansion, Pooling, Sharing, FAM Enablement, and Switching

2. Compute Memory Bottleneck Heterogenous architectures and Memory Efficiency Plateau CXL ™ A Protocol For Memory Memory Tiering with CXL TM CXL TM Switching Agenda

3. CPU vendors are introducing powerful CPUs with higher core counts at a rapid pace Amount of DDR memory that could be directly attached to CPU is limited due to Number of parallel DDR interfaces/channels per CPU Requires large number of IO pins for each memory channel (~300 pins) Adding more interfaces will impact CPU Die and package size Compute Memory Bottleneck

4. CPU CPU GPU GPU Accel Accel Heterogeneous Compute resources Memory and Storage resources Data Global data Resources and generation CPUs, GPUs, Custom Accelerators Analysis extraction Medical outcomes Self-driving vehicles Filtered and sorting Data analytics Cat photos Time critical data Stock market decisions Task Prioritization Augmented reality Advertising Catastrophe avoidance Heterogenous architectures and Memory Efficiency Plateau

5. CXL Disaggregates Memory to Allow Expansion ​ Lowering pin-count allows expansion More memory added to support more processor cores Allow memory pooling and multiple processors to share memory and data more efficiently

6. CXL enables Memory Diversity with the same look and feel abstracting different memory types to be supported behind a memory controller Memory Tiering with CXL TM

7. Memory Tiering Model with CXL™ Storage On-package memory/High Bandwidth Memory (HBM) DDR direct-attached CXL direct-attached CXL Switch-attached CXL Fabric-attached or GFAM OPM DRAM (Hot) DRAM (Warm) SCM (Cool) DRAM/SCM (Cold) Direct attach “Near” Memory Switch/fabric attach “Far” Memory Microchip Memory Infrastructure Products will enable memory tiering to optimize performance and cost for application-dependent workloads

8. Memory Tiering with CXL Switch-Attached Memory Expansion CPU SSD SSD SSD HDD HDD HDD CPU CPU CPU IO Controller IO C T R L MEM C T R L L3 Cache DDR5 DIMMs L1 Cache L2 Cache DDR5 DIMMs CXL Switch DDR5 DIMMs MEM C T R L DDR4 DIMMs Low Latency NAND or PMEM CXL Flash Controller

9. Memory Tiering w ith CXL Fabric-Attached Memory Expansion

10. CXL ™ Memory Performance Comparison CPU DDR CXL CXL OS 70 ns 30 ns 100 ns 100 ns 100 ns 40 ns 70 ns 150 ns Use-Case Load to Use Direct DDR ~100 ns Direct CXL ~170 ns Pooled CXL ~200 ns Switched CXL ~320 ns Memory Controller DRAM DRAM DRAM 30 ns DRAM DRAM DRAM CXL CXL Multi-head Memory Controller 30 ns DRAM DRAM DRAM Switch 40 ns Memory Controller 30 ns DRAM DRAM DRAM

11. Resilience, Security and Performance BO - Content

12. Connects multiple hosts and memory devices Provides low latency, high-bandwidth interfaces between various CXL devices, such as CPUs, GPUs and memory modules It enables these devices to share data through multiple host platforms Supports downstream PCIe® links Flexible CXL TM Switching Root Port CXL Switch CXL Type 2 CXL Type 3 CXL Switch CXL EP PCIe EP

13. CXL 3.0 enables non-tree topologies and peer-to-peer communication (P2P) within a virtual hierarchy of devices PCIe® is tree topology CXL TM 3.0: Device to Device Connectivity

14. CXL TM 2.0 & 3.0 Switch Comparison Diagram

15. Thank you!

16. Using PCI Express® and (PCIe®) physical and electrical interface standard Enables efficient high bandwidth interface between CPU, memory and accelerators Maintains memory coherency between CPU memory space and memory on CXL attached devices that enables resource sharing, memory disaggregation with memory pooling and sharing Open industry standard starting with CXL 1.0 to 3 CXL ™ A Protocol For Memory

17. How to get involved in the Project/Sub-Project Community Timeline for Contribution Availability Timeline for Product/Facility Availability Link to Contribution DB/OCP Marketplace Where to find additional information (URL links) [Example] Where to buy: https:// www.opencompute.org /products [Example] Project Wiki with latest specification : http:// www.opencompute.org /wiki/Server/Mezz [Example] Mailing list: http:// lists.opencompute.org /mailman/ listinfo / opencompute -mezz-card BO - Content [Call to Action] [MANDATORY]

18. Open Discussion

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