D latch

D latch basics and operation
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1. D Latch

2. Today's Topic Sequential Logic Circuits D Latch

3. There is one drawback of SR Latch That is “Race Around Condition” That is the next state value can’t be predicted when both the inputs S & R are one . (when NOR gate SR is taken) when both the inputs S & R are Zero . (when NAND gate SR is taken) Truth table for SR (or) RS latch using NOR gates S R Q p Qp ’ State Q p Qp ’ Memory / No change state 1 1 RESET 1 1 SET 1 1 - - Invalid/ Forbidden state WHY D LATCH

4. So, we can overcome this difficulty by D Latch. It is also called as Data Latch. The  circuit diagram  of D Latch is shown in the following figure.

5. D Latch D latch is called as Data latch or Delay latch. One of the simple latches to store data. It is also called transparent latch. A simple D latch can be constructed using SR latch and a NOT gate D Latch Without Enable D Latch With Enable / Gated D latch

6. A B Y 1 1 1 1 1 NOR truth table Logic Diagram of D latch Without ENABLE D Q Q ’ State 1 Reset 1 1 Set i/p o/p

7. Logic Diagram of D latch With ENABLE (Gated D Latch) The difference between D latch and Gated D latch is Enable pin(E). E D Q Q ’ State Q Q ’ No Change 1 Q Q ’ No Change 1 1 Reset 1 1 1 Set E D Q State X Q No Change 1 Reset 1 1 1 Set The Output is obtained only when Enable pin is ACTIVATED. Otherwise it remains in No Change state =

8. In Next Class Flip Flops

9. A