Data Path single cycle data movement.pptx

data path

1. Single and Multiple cycle Data Path

2. Data path design Datapath are a key aspect in the design of a computer architecture specifically in a CPU There are two kinds of Datapath: Single Cycle Datapath and Multiple Cycle Datapath 1.Single Cycle Datapath: A Single Cycle Datapath completes each instruction in a single clock cycle and it is the simplest design. The entire instruction from the fetching stage, decoding phase and the executing stage is done within a single cycle Features of Single Cycle Datapath One Cycle per Instruction:  All the instructions are done in one single clock cycle, and therefore, the CPI, which stands for Cycles per Instruction, is equal to 1.  Control Unit:  The control unit produces all that are presented in the entire instruction at once.  Simplified Design:  This design appears less complex because there is no fragmentation of the instructions 

3. Data path design Advantages:   Simplicity:  Its development is easier than that of other large systems  Consistent Timing:  All of the instructions take equal amounts of time 2.Multiple Cycle Datapath: Multiple Cycle Datapath divides the entire instruction into multiple parts, each of which occurs in a serial fashion in a single clock cycle. Reusability of functional units occurs in various clock cycles This design optimizes utilization of the hardware and can result in more efficient execution of instructions.  Features of Multiple cycle: Multiple Cycles per Instruction  In general, steps are followed as step-wise instructions, and each step is implemented in a different cycle.  Control Unit:  It produces the signals of the current step of the instruction and keeps record of which step is being performed.  Efficiency:   Fewer cycles are taken per instruction leads to faster execution

4. Data path design Feature / Aspect Single-Cycle Datapath Multi-Cycle Datapath Execution Model Each instruction completes in 1 cycle Instruction is split into multiple cycles Hardware Utilization Requires duplicated hardware (e.g., separate memories) Hardware is reused across cycles Control Unit Simple, hardwired More complex, needs FSM sequencing Performance Lower performance, clock is slow Higher performance, clock is faster Implementation Complexity Easier to design Harder to design Efficiency Inefficient for simple instructions More efficient, especially for varied workloads