DELD_UNIT III all the topics and subtopics.pptx

Dwld unit 3

1. 2020-21 (SEM-I) On Second Year of Computer Engineering (2019 Course) 210245 : Digital Electronics & Logic Design

2. Digital Electronics & Logic Design : Teaching/Examination Scheme Teaching Scheme: Examination Scheme TH: 03 Hours/Week Mid_Semester(TH): 30 Marks End_Semester(TH): 70 Marks Credits : 03

3. Digital Electronics & Logic Design : Course Outcomes On completion of the course, learner will be able to– CO1: Simplify Boolean Expressions using K Map. CO1: Design and implement combinational circuits. CO1: Design and implement sequential circuits. CO1: Develop simple real-world application using ASM and PLD. CO1: Choose appropriate logic families IC packages as per the given design specifications. CO1: Explain organization and architecture of computer system.

4. Digital Electronics & Logic Design Unit III Sequential Logic Design (6 Hours) Flip-Flop: SR, JK,D,T; Preset &Clear, Master Slave JK Flip Flops, Truth Tables and Excitation tables, Conversion from one type to another type of Flip Flop. Registers: SISO, SIPO, PISO, PIPO, Shift Registers, Bidirectional Shift Register, Ring Counter , Universal Shift Register, Counters: Asynchronous Counter, Synchronous Counter, BCD Counter, Johnson Counter, Modulus of the counter ( IC 7490),Synchronous Sequential Circuit Design :Models- Moore and Mealy, State diagram and State Table ,Design Procedure, Sequence Generator and detector.

5. Sequential Circuits A sequential circuit is one whose outputs depend not only on its current inputs, but also on the past sequence of inputs. In other words, sequential circuits must be able to ” remember ” (i.e., store) the past history of the inputs in order to produce the present output. The information about the previous inputs history is called the state of the system. A circuit that uses n binary state variables to store its past history can take up to 2 n different states. Digital Electronics & Logic Design

6. Sequential Circuits Digital Electronics & Logic Design

7. Differences Combinational circuits 1. Output depends on present input only 2. It does not have memory element 3. Clock input is not require EX: Adders, Subtractors, Code Convertors Sequential circuits 1. Output depends on present inputs as well as previous inputs / Past outputs. 2. Memory element is necessary 3. Clock input is require Ex: Flip flops, Shift Registers, Counters Digital Electronics & Logic Design

8. Flip-flop A flip-flop is a circuit that has two stable states and can be used to store state information. The flip-flop can be made to change state by signals applied to one or more control inputs and will have one or two outputs. Digital Electronics & Logic Design

9. 1 Bit Memory Cell ( Flip flop) Cross Couple Inverters as Memory Element Properties The output Q and Q̅̅are always Complementary. The Circuit has two stable State.(i.e. Q=1 Set State and Q=0 Reset State). The Circuit continues to remain in the same state referred as Memory. The information is latched or locked in this circuit ,so it is also referred as Latch. G1 G2 A 1 A 2 Q Q Digital Electronics & Logic Design

10. Latches & Flip flops The two most popular varieties of storage cells used to build sequential circuits are: latches and flip-flops. Latch: level sensitive storage element Flip-Flop: edge triggered storage element SR, D latches. D, JK, SR & T flip flops. The difference between a latch and a flip-flop is that a latch is level-triggered (outputs can change as soon as the inputs changes) and Flip-Flop is edge triggered (only changes state when a control signal goes from high to low or low to high). Digital Electronics & Logic Design

11. 1. 1 Bit Memory Cell with input (SR FF) IF S=R=0 Circuit will be same state i.e. No Change. IF S=1 & R=0 then Q=1 IF S=0 & R=1 then Q=0 IF S=R=1 , then both the outputs Q and Q̅ will try to become 1 which is not allowed and therefore this input condition is prohibited (Race Condition). Digital Electronics & Logic Design

12. A Clocked S-R Flip Flop Truth Table:- shows operation of circuit in tabular format Input Input Output Sn Rn Qn+1 Qn 1 1 1 1 1 ? Digital Electronics & Logic Design

13. 2. JK FF Used to avoid race condition which does occur in SR FF It has 2 inputs named J & K. It has two outputs Q & Q’. One Clock signal. 2 Asynchronous inputs PR & CLR Symbol of JK - Digital Electronics & Logic Design

14. JK FF Operation J K Q Q’ Mode Q Q’ Hold 1 1 Sets 1 1 Resets 1 1 Q’ Q Toggle The 4 modes of operation are: hold, set, reset, toggle Truth Table of JK Digital Electronics & Logic Design

15. Mode of Operation: Hold J K Q Q’ Orig. Q Orig. Q’ 1 1 Hold : no change in Q. Digital Electronics & Logic Design

16. J K Q Q’ Orig. Q Orig. Q’ 1 1 1 Reset : Q = 0. Digital Electronics & Logic Design Mode of Operation: Reset

17. J K Q Q’ Orig. Q Orig. Q’ 1 1 1 Set : Q = 1. Digital Electronics & Logic Design Mode of Operation: Set

18. J K Q Q’ Orig. Q Orig. Q’ 1 1 1 1 Toggle : Q = Q’. Digital Electronics & Logic Design Mode of Operation: Toggle

19. D-Type Flip Flop D – means Delay. The Q output always takes on the state of the D input at the moment of a rising clock edge. The output takes the value of the D input or Data input, and Delays it by one clock count. Truth Table D Q 1 1 Digital Electronics & Logic Design

20. T -Type Flip Flop (Toggle) In J K Flip Flop , if J=K, the resulting Flip flop is referred to as a T- type Flip Flop. T Q Q 1 Q’ Pr Clk Cr Digital Electronics & Logic Design

21. Race Around Condition When J=K=1, then race around condition occurs It occurs, when the time period of the clock pulse (pulse width) is greater than the propagation delay of the flip flop. Due to that output changes or toggles in a single clock period. Propagation delay is the speed of operation of circuit. If it toggles even number of time, then the output is same but if it toggles odd number of times then output is complimented. How to avoid it? We cant make clock pulse smaller than propagation delay, so to avoid it two options: Master slave JK FF Edge triggered JK FF Digital Electronics & Logic Design

22. Digital Electronics & Logic Design Race Around Condition

23. Inputs: PR and CLR A low at the PR input sets Q = 1 A low at the CLR input sets Q = 0 Digital Electronics & Logic Design

24. Preset & Clear When the power is switched on the state of the circuit is uncertain.(i.e. 0 or 1) In many application it is desired to initially set or reset the Flip Flop to initial state. This is accomplished by using direct or asynchronous inputs referred to as preset(Pr) and clear(Cr) inputs. These inputs may be applied at any time between clock pulses. They are highest priority inputs. Digital Electronics & Logic Design

25. SR flip-flop with Preset & Clear Preset(Pr) Clear (Cr) CLK An S-R Flip- Flop with Preset and Clear Inputs Output Operation Performed Clk Pr Cr Q 1 1 1 Qn+1 Normal FF 1 Clear 1 1 Preset Race Prohibited Condition Digital Electronics & Logic Design

26. Master Slave FF The  Master-Slave Flip-Flop  is basically two gated SR flip-flops connected together in a series configuration with the slave having an inverted clock pulse. The outputs from Q and Q’ from the “Slave” flip-flop are fed back to the inputs of the “Master” with the outputs of the “Master” flip flop being connected to the two inputs of the “Slave” flip flop.  When clock is ‘high’, master SR latch will lock the input conditions and as clock is inverted to slave , slave SR latch will not toggles. When clock goes low, the outputs from master FF are latched and any additional changes to its inputs are ignored . Now gated slave FF are now responds. Digital Electronics & Logic Design

27. On low to high transitions of clock pulse the inputs of master FF are fed through to the gated inputs of slave FF and on High-to-Low” transition the same inputs are reflected on the output of the “slave” making this type of flip flop edge or pulse-triggered. Then, the circuit accepts input data when the clock signal is “HIGH”, and passes the data to the output on the falling-edge of the clock signal. Master-Slave JK Flip flop  is a “Synchronous” device as it only passes data with the timing of the clock signal. Digital Electronics & Logic Design Master Slave FF

28. Digital Electronics & Logic Design Master Slave FF

29. Input Output waveform of Mater Slave flip flop Digital Electronics & Logic Design

30. Excitation Tables Two tables are there:- Truth table:- shows operation of circuits i.e. shows changes in output whenever changes in inputs. Mapping between input to output. Excitation table:- Sometimes there is need to find input condition from the given output conditions, we need excitation table. In this case for the desired output, we need to find out input conditions Digital Electronics & Logic Design

31. J K Flip Flop JK truth table Next state table J K Qn+1 Qn 1 1 1 1 1 Qn’ Qn Qn+1 J K X 1 1 X 1 X 1 1 1 X JK excitation table J K Qn Qn+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Digital Electronics & Logic Design

32. SR truth table Next state table S R Qn+1 Qn 1 1 1 1 1 ? Qn Qn+1 S R X 1 1 1 1 1 1 X SR excitation table S R Qn Qn+1 1 1 1 1 1 1 1 1 1 1 1 1 ? 1 1 1 ? Digital Electronics & Logic Design S R Flip Flop

33. D truth table Next state table D Qn+1 1 1 D excitation table D Qn Qn+1 1 1 1 1 1 1 Qn Qn+1 D 1 1 1 1 1 1 Digital Electronics & Logic Design D Flip Flop

34. T truth table Next state table T Qn+1 Qn 1 Qn’ T excitation table T Qn Qn+1 1 1 1 1 1 1 Qn Qn+1 T 1 1 1 1 1 1 Digital Electronics & Logic Design T Flip Flop

35. Conversion of FF We can convert easily one type of flip flop into another flip flop by using some additional gates / combinational circuits. In this case, what we need is truth table of required FF and excitation table of given FF. Digital Electronics & Logic Design

36. JK- Flip Flop to T- Flip Flop Input Present State Next State Flip Flop Input Flip Flop Input T Qn Qn+1 JA KA X 1 1 X 1 1 1 X 1 1 X 1 Qn Qn+1 J K X 1 1 X 1 X 1 1 1 X Digital Electronics & Logic Design https://youtu.be/bl77FRTAXWA https://youtu.be/zEHoFrGYwdA https://youtu.be/iAEgeuIoEBQ https://youtu.be/PMJ09EwvnF0

37. Implement T Flip-flop by JK Flip-flop 0 X 1 X X 1 X 0 J K 0 0 0 1 1 0 1 1 T Q 1 0 1 1 0 Q Q+ 0 1 T Q 1 0 X 1 X 0 1 T Q 1 X 0 X 1 0 1 J = T K = T Digital Electronics & Logic Design

38. Excitation table of T Flip Flop Input Present State Next State Flip- Flop input D Qn Qn+1 T 1 1 1 1 1 1 1 1 Qn Qn+1 T 1 1 1 1 1 1 Digital Electronics & Logic Design Implement D- Flip-flop by T- Flip-flop

39. T Flip-Flop to D Flip-Flop 0 1 0 1 1 0 D Qn 1 T = D Q’ + D’ Q D D’ T Digital Electronics & Logic Design

40. T Flip Flop to JK Flip Flop Input Input Present State Next State Flip Flop input J K Qn Qn+1 T 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Qn Qn+1 T 1 1 1 1 1 1 Digital Electronics & Logic Design

41. 0 1 0 0 0 1 1 1 0 J K Q 0 0 0 1 1 1 1 0 T = J Q’ + K Q T 0 1 J K 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 T Q + 1 Q Q’ J K Q Q’ Q Q + J K Q + 0 0 0 1 1 0 1 1 Q 1 Q’ Digital Electronics & Logic Design

42. Input Input Present State Next State Flip Flop input J K Qn Qn+1 D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Digital Electronics & Logic Design D Flip Flop to JK Flip Flop

43. 0 1 0 1 0 0 1 1 J K Q 0 0 0 1 1 1 1 0 D = J Q’ + K’ Q D 0 1 J K Q 0 0 0 1 1 1 1 0 0 1 0 0 1 1 D Q + 1 1 J K Q Q’ Digital Electronics & Logic Design D Flip Flop to JK Flip Flop

44. Application of Flip Flop Digital Electronics & Logic Design

45. Bounce Elimination Switch Mechanical switches are employed digital systems as input devices by which digital information is entered into the system. In Sequential circuit , if 1 is to be entered through a switch , then the switch is thrown to the corresponding position. The output oscillates between 0 and 1 creates difficulty in the operation of system. This problem is eliminated by Bounce Elimination Switch. Digital Electronics & Logic Design

46. Switch Denouncer Digital Electronics & Logic Design

47. Registers A register s composed of group of Flip Flops to store group of bits. For storing N bit word , N number of Flip Flops are required. One Flip Flop is required for storing each bit. There are different way to enter data in registers. Digital Electronics & Logic Design

48. Digital counters are often needed to count events. The counter are also composed of Flip Flops. A circuit with n Flip Fops has 2 n possible states Digital Electronics & Logic Design Counters

49. Registers hold larger quantities of data than individual flip-flops. Registers are central to the design of modern processors. There are many different kinds of registers. A register is an extension of a flip-flop that can store multiple bits. Registers are commonly used as temporary storage in a processor. They are faster and more convenient than main memory. More registers can help speed up complex calculations. Digital Electronics & Logic Design Registers

50. Buffer Register Shift Register Serial In Serial Out (SISO) Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) Parallel In Parallel Out (PIPO) Bidirectional Shift Register Universal Shift Register Digital Electronics & Logic Design Types of Registers

51. Buffer Register D Q Q Input Output D Q Q Output D Q Q Output Input Input Digital Electronics & Logic Design

52. Shift Registers SISO: Serial In, Serial Out SIPO: Serial In, Parallel Out PISO: Parallel In, Serial Out PIPO: Parallel In, Parallel Out 10110 10110 10110 10110 10110 10110 10110 10110

53. Shift Register Construction Shift registers are comprised of D Flip-Flops that share a common clock input. Registers 1. 53 D Q Q D Q Q D Q Q Digital Electronics & Logic Design

54. SISO Flip-Flop Shift Register a Serial In Serial Out shift register has a single input and a single output Registers 1. 54 D Q Q D Q Q D Q Q Input Output Digital Electronics & Logic Design

55. A Serial In Parallel Out shift register has a single input and access to all outputs Registers 1. 55 D Q Q D Q Q D Q Q Input Output Output Output Digital Electronics & Logic Design SIPO Flip-Flop Shift Register

56. A Parallel In Serial Out shift register requires additional gates, and the parallel input must revert to logic low for serial output. Registers 1. 56 Input D Q Q Input Output Input D Q Q D Q Q Digital Electronics & Logic Design PISO Flip-Flop Shift Register

57. A Parallel In Parallel Out register has the simplest configuration. It represents a memory device. Registers 1. 57 D Q Q Input Output D Q Q Output D Q Q Output Input Input Digital Electronics & Logic Design PIPO Flip-Flop Shift Register

58. Bidirectional Shift Register Digital Electronics & Logic Design

59. Digital Electronics & Logic Design Bidirectional Shift Register

60. If the register has both shifts (right shift and left shift) and parallel load capabilities, it is referred to as universal shift register. Registers 1. 60 Digital Electronics & Logic Design Universal Shift Register

61. Digital Electronics & Logic Design

62. Digital Electronics & Logic Design

63. Temporary data storage. Bit manipulation. Serial to parallel convertor. Parallel to serial convertor. Computer and Data Communications. Serial and Parallel Communications. Multi-bit number storage. Sequence generator. Sequence Detector. Logical operations. Registers 1. 63 Digital Electronics & Logic Design Shift Register Applications

64. Ring Counter A ring counter takes the serial output of the last Flip-Flop of a shift register and provides it to the serial input of the first Flip-Flop. Digital Electronics & Logic Design

65. Clock Pulse Q0 Q1 Q2 Q3 1 1 1 2 1 3 1 4 1 0 (Repeat) Digital Electronics & Logic Design

66. Timing Sequence of 4 bit Ring Counter Digital Electronics & Logic Design

67. Johnson Counter / Twisting Ring / Switch Tail Counter A Johnson Counter re-circulates the last flip-flop Q (inverted) output back to the input of the first Flip-Flop. It doesn’t require an initialization value, and will provide a predictable output state sequence. Digital Electronics & Logic Design

68. Digital Electronics & Logic Design https://youtu.be/SXbXnfgY6jk

69. Counter A Counter is a register capable of counting the number of clock pulses arriving at its clock input. n bit counter has n flip flops and it has 2 n distinct states with maximum count of 2 n -1. Types of Counter Synchronous Counter Asynchronous Counter Digital Electronics & Logic Design

70. Output of the first flip flop drives the clock for the next flip flop. All the flip flops are not clocked simultaneously. Logic circuit is very simple. These counters are slow because of propagation delay. No connection between output of first flip flop and clock input of the next flip flop. All the flip flops are clocked simultaneously. Logic circuit is complex. These counters are fast. Synchronous Counter Asynchronous Counter Differences Digital Electronics & Logic Design

71. Ripple/Asynchronous Counter Digital Electronics & Logic Design https://youtu.be/fyagSrWSWbc

72. 4 bit Asynchronous up counter Digital Electronics & Logic Design https://youtu.be/eEeBh8jfDjg

73. Digital Electronics & Logic Design 4 bit Asynchronous down counter https://youtu.be/bP-NHd2Hrh8 https://youtu.be/qBhP0-8g4AA

74. Asynchronous Up/ Down Counter Input Input Input Output M Q Q’ Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Digital Electronics & Logic Design

75. Digital Electronics & Logic Design

76. Synchronous Counter Digital Electronics & Logic Design

77. 3 bit Synchronous Up/Down Counter Counter has 8 states i.e N=8 2 n >= N n = no. of Flip Flop= 3 Digital Electronics & Logic Design

78. Control input M Input for Flip-flop Q C Q B Q A Q C+1 Q B+1 Q A+1 J C K C J B K B J A K A 1 X X 1 X 1 1 X 1 X X 1 1 1 1 X X 1 X 1 1 1 1 X X 1 X 1 1 1 1 X X 1 X 1 1 1 1 X 1 X X 1 1 1 1 1 1 X X 1 X 1 1 1 X 1 X 1 X 1 1 1 1 1 1 1 X 1 X 1 X 1 1 1 1 1 X X X 1 1 1 1 1 X X 1 1 X 1 1 1 1 X 1 X X 1 1 1 1 1 X 1 X 1 X 1 1 1 X X X 1 1 1 X X 1 1 X 1 1 1 1 1 X 1 X X 1 Digital Electronics & Logic Design https://youtu.be/10DVImrPRvM

79. Digital Electronics & Logic Design

80. Digital Electronics & Logic Design

81. Logical diagram of 3 bit Synchronous Counter Digital Electronics & Logic Design

82. Decade Binary Counter/Modulo N counter /Divide by counter IC 7490 is a decade binary counter Internal Diagram of IC 7490 Digital Electronics & Logic Design https://youtu.be/40P8CJmuY3Q https://youtu.be/DzROIvNPpFw

83. Function table 7490 Reset Input Output R(0) R(1) S(0) S(1) Q D Q C Q B Q A H H L X L L L L H H X L L L L L X X H H H L L H X L X L COUNT L X L X COUNT L X X L COUNT X L L X COUNT Digital Electronics & Logic Design

84. Digital Electronics & Logic Design

85. Design MOD 6 counter using IC 7490. Theoretical Method Clock count states Q D Q C Q B Q A Reset input 1 1 2 1 3 1 1 4 1 5 1 1 6 1 1 1 7 1 1 1 1 8 1 1 9 1 1 1 Digital Electronics & Logic Design https://youtu.be/t3esAnNl_bI

86. Digital Electronics & Logic Design Design MOD 6 counter using IC 7490.

87. Logical Diagram for Mod 6 Counter Digital Electronics & Logic Design

88. Divide by 20 counters using IC 7490 Logical Method :- MOD 20 COUNTER : -We know that One IC can work as mod-10 BCD counter. Therefore we need two ICs. The counter will go through 0-19 & should be reset on state 20 i.e. Q D Q C Q B Q A Q D Q C Q B Q A 0 0 1 0 0 0 0 0 7490(1) 7490(2) Digital Electronics & Logic Design

89. Logical Diagram for Mod 20 counter Digital Electronics & Logic Design

90. BCD counter (Synchronous) It counts from 0 – 9. Digital Electronics & Logic Design

91. Truth table (1) Connect Y to reset input. When Y=0, circuit will reset else it will count Digital Electronics & Logic Design

92. Synchronous BCD counter (2) Design BCD counter using JK flip flop. Digital Electronics & Logic Design

93. Synchronous Sequential Circuit Design: FF and sequential circuits changes their state in accordance with clock signal. Present state:- the status of all state variables, at some time t, before the next clock edge, represents condition – present state. ( State before application of clock pulse) Next State:-the status of all variables, at some time, t+1, represents next state ( State after application of clock pulse) Digital Electronics & Logic Design

94. Moore Machine:- Output of the circuit depends only on present state of FF, then it is Moore machine. Digital Electronics & Logic Design Synchronous Sequential Circuit Design:

95. Mealy Machine:- Output of the circuit depends on present state as well as on the inputs, called mealy m/c. Digital Electronics & Logic Design

96. State diagram:- It is pictorial representation of a behavior of a sequential circuits. State is represented by circle and transitions indicated by directed lines connecting the circles. Self loop indicates next state is same as present state. Directed line is labeled by input and output separated by /. Digital Electronics & Logic Design

97. State table:- State diagram translated into tabular format, called state table. It represents relationship between input, output and flip flop states. Mealy Machine Moore Machine Present state Next State (i/p) Output X=0 X=1 X=0 X=1 AB AB AB Y Y a a c b b a c d c 1 d b d Present state Next State Output X=0 X=1 AB AB AB Y a a c b b a c d c 1 d b d Digital Electronics & Logic Design

98. Design procedure Obtain the state table from the circuit information such as – state diagram, timing diagram. Redundant state may be reduced by state reduction technique Assign binary value to each state in state table Determine number of flip flop required and assign letter Choose type of FF From state table, derive circuit excitation and output table Using simplification technique derive the equations Draw logic diagram. Digital Electronics & Logic Design

99. Sequence Generator A Sequence Circuit, Which generates a prescribed sequence of bits in synchronism with a clock, is referred to as sequence generator. Digital Electronics & Logic Design

100. Problem Statement Design sequence generator to go through the following states by using J K flip-flop Digital Electronics & Logic Design

101. Present states Next state A B C Q A Q B Q C Q A+1 Q B+1 Q C+1 J A K A J B K B J C K C 1 X X 1 X 1 1 1 X 1 X X 1 X X X X X X X X X 1 1 1 1 X X 1 X 1 1 1 1 X 1 X X 1 1 X X X X X X X X X 1 1 X 1 X 1 X 1 1 1 X X X X X X X X X Present state Next state Jn Kn X 1 1 X 1 X 1 1 1 X Digital Electronics & Logic Design

102. Digital Electronics & Logic Design

103. Sequence Generator Digital Electronics & Logic Design

104. Sequence Detector A Sequence Circuit, Which detects a prescribed sequence of bits in synchronism with a clock, is referred to as sequence detector. Digital Electronics & Logic Design

105. Problem Statement Design sequence detector using J K flip-flop to detect the following sequence: 1001  Solution: State diagram Digital Electronics & Logic Design https://youtu.be/CculzwwVvow https://youtu.be/1KrrQE34DuI

106. Present states Next state FF 1 FF 0 Q 1 Q X Q 1+1 Q 0+1 Z J 1 K 1 J K X X 1 1 X 1 X 1 1 1 X X 1 1 1 1 X X 1 1 1 X 1 X 1 1 1 X 1 1 X 1 1 X 1 X 1 1 1 1 1 1 X 1 X Present state Next state Jn Kn X 1 1 X 1 X 1 1 1 X State Transition Table Digital Electronics & Logic Design

107. K Map Digital Electronics & Logic Design

108. Sequence Detector Digital Electronics & Logic Design

109. Asynchronous sequential circuits Synchronous Sequential Asynchronous Sequential Memory elements are clocked FF Memory elements are either un clocked FF or time delay elements In this the change in input signals can affect memory element upon activation of clock signals In this change in input signals can affect memory elements at any instant of time. The maximum operating speed of clock depends on time delays involved Because of absence of clock, asynchronous circuits can operate faster than synchronous circuits Easier to design More difficult to design Digital Electronics & Logic Design

110. Asynchronous Sequential Circuits Asynchronous circuits don’t use clock pulses State transitions by changes in inputs Storage Elements: Clockless storage elements (Unclocked) or Delay elements In many cases, as combinational feedback 🡪 Normally much harder to design Digital Electronics & Logic Design

111. Asynch. Sequential Circuit delay delay delay Combinational Circuit x 1 x 2 x n z 1 z 2 z m y 1 y 2 y k Y 1 Y 2 Y k inputs outputs Current State Next State Digital Electronics & Logic Design

112. Current state :- also called secondary variables Next state:- excitation variables When an input variable changes in value, the secondary variables y1, y2 do not change instantaneously Certain amount of time is required for the input signal to propagate from input terminals through combinational circuit and delay elements. Combinational circuit generates Y excitation variables which gives next state of the circuit. The excitation variables are propagated through delay elements to become the new present state for the secondary variables are same, but during transition they are different. Digital Electronics & Logic Design

113. To ensure proper operation, it is necessary for circuit to be in stable state before the input changed to a new value. It is impossible to have two or more input variables change exactly at same instant Only one input variable is allowed to change at one time instant and time between two input changes in kept longer than the time it takes the circuit to reach a stable state. Digital Electronics & Logic Design

114. Asynch. Sequential Circuit y i = Y i in steady state (but may be different during transition) Called stable state else unstable. Simultaneous change in two (or more) inputs is prohibited. The time between two changes must be less than the time of stability. Digital Electronics & Logic Design

115. Advantages and Disadvantages Advantages: Low power High performance No need for clock Disadvantages: Complexity of design process Digital Electronics & Logic Design

116. Analysis Design procedure Determine the next secondary state and output equations from given sequential circuits Construct the state table Construct the transition table Construct output map Digital Electronics & Logic Design https://youtu.be/g-Av3aFAJTI https://youtu.be/Qyj95-bPxZM

117. Analysis Find boolean expressions of Y i ’s in terms of y i ’s and inputs. Y 2 Y 1 x y 2 y 1 Y 1 = x.y 1 + x’.y 2 Y 2 = x.y 1 ’ + x’.y 2 Digital Electronics & Logic Design

118. Design Procedure Find the equations:- Y 1 = x.y 1 + x’.y 2 Y 2 = x.y 1 ’ + x’.y 2 Z= Y1’.Y2 Digital Electronics & Logic Design

119. Present total state Next total state State Input X1 X0 Yes/NO Z X1 X0 I1 I0 yes 1 Yes 1 1 Yes 1 Yes 1 1 No 1 1 1 No 1 1 1 1 Yes 1 1 No 1 1 1 1 Yes 1 1 1 1 No 1 1 1 1 1 1 1 Yes 1 1 1 1 1 No 1 1 No 1 1 No 1 1 1 No 1 1 1 No Digital Electronics & Logic Design

120. Transition table X1X0\I1I0 00 01 11 10 00 (00) (00) (00) (00) 01 10 10 (01) 00 11 (11) 10 (11) 01 10 01 00 00 01 Output table X1X0\I1I0 00 01 11 10 00 01 -- -- -- 11 -- 1 -- 10 -- -- -- -- Digital Electronics & Logic Design