design and implementation of Area efficient arithmetic circuit

SravanKumar743222 17 views 12 slides Oct 01, 2024
Slide 1
Slide 1 of 12
Slide 1
1
Slide 2
2
Slide 3
3
Slide 4
4
Slide 5
5
Slide 6
6
Slide 7
7
Slide 8
8
Slide 9
9
Slide 10
10
Slide 11
11
Slide 12
12

About This Presentation

PPT regarding Project Base Paper


Slide Content

DESIGN AND IMPLEMENTATION OF LOW POWER AND AREA EFFICIENT OF ARITHMETIC CIRCUIT BY USING GATE DIFFUSION INPUT (GDI) TECHNIQUE Presented by M .Tech (VLSI&ES ) Under the esteemed guidance of Professor Department of ECE SVPEC

INDEX ABSTRACT INTRODUCTION PASS TRANSISTOR LOGIC GDI LOGIC ARITHMETIC CIRCUIT ADVANTAGES APPLICATIONS REFERENCES

ABSTRACT Lot of advancement in VLSI technology makes low power and low energy as important issues in consumer electronics. In digital circuits, multiplexer or data selector plays an important role where it processes multiple input lines and gives a single output . With regard to pass transistor logic, the paper proposes to construct an 8:1 multiplexer using the Innovative Gate Diffusion Input (GDI) technique (PTL). In this project, the arithmetic circuit is designed using basic GDI cell. The design of digital combinational circuit by GDI technique is done using Tanner EDA tool. The GDI technique overcomes the disadvantages in Pass Transistor Logic(PTL). These logic styles are simulated ,and To compare the propagation delay, power, and transistor count. The pass transistor logic has a propagation delay of 0.06378ns and a power dissipation of 0.06191 w, compared to the GDI technique’s propagation delay and power dissipation of 0.04759ns and 0.04007w, respectively. Innovative GDI technique gives less propagation delay and power consumption when compared with pass transistor logic.

INTRODUCTION In comparison to conventional CMOS design and existing PTL techniques, the GDI technique is appropriate for the construction of quick, low-power circuits employing fewer transistors. [12 ]. At the beginning of the 80s,CMOS logic was introduced and various design technique have been developed to reduced delay propagation and speed up operation. Delay performance and power reduction is the important parameter for determining circuit efficiency in VLSI digital circuits [28 ]. The primary factor for high performance computing applications , image processing , portable [3]digital equipment is need of low power . Numerous research efforts are prompted by the rapid development of portable digital applications, the necessity for rising speed, small implementation, delay performance, and low power dissipation . Pass transistor logic is a type of logic that is common in low power digital circuitry (PTL) [15].Pass transistors logic are designed by using NMOS alone. Different combinational selections are applied to the nMOS transistors’ gates depending on the selection line.

Pass Transistor Logic Pass transistor logic (PTL) is a design technique used in Very Large Scale Integration (VLSI) to implement digital logic circuits. Instead of using traditional logic gates like AND, OR, and NOT (which rely on transistors and resistors), pass transistor logic uses transistors to pass logic levels directly between nodes of the circuit . In PTL, MOSFETs (typically NMOS or PMOS transistors) are used as switches to pass or block signals. The source or drain terminals of the transistor are connected to the input or output, and the gate terminal is used to control whether the transistor is on or off . One of the challenges with pass transistor logic is the voltage degradation that can occur. NMOS transistors pass a strong logic '0' but a weak logic '1', while PMOS transistors pass a strong logic '1' but a weak logic '0'. This can introduce logic level issues, which must be managed . PTL circuits can be faster than conventional CMOS circuits because fewer transistors are involved, reducing parasitic capacitance. This leads to faster signal propagation in some cases. Fig :Circuit diagram of Pass Transistor Logic .

Gate Diffusion Input Gate Diffusion Input (GDI) is a design technique used in VLSI to reduce power consumption, area, and complexity of digital circuits, while maintaining or improving performance. GDI is an alternative to traditional CMOS logic and pass transistor logic, offering benefits like reduced transistor count and lower power dissipation . Unlike conventional CMOS logic, where a logic gate typically has two terminals (input and output), the GDI cell has three inputs: G : The gate of the transistor (as in standard logic gates). P : Connected to the source/drain of the PMOS transistor. N : Connected to the source/drain of the NMOS transistor. This allows the GDI method to implement various logic functions by controlling these three inputs. GDI typically uses fewer transistors than traditional CMOS logic circuits to implement the same logic functions. For example, inverters, multiplexers, and XOR gates can be implemented with only 2 transistors, compared to the 6 transistors required in standard CMOS logic. Fig :Circuit diagram of Gate Diffusion Input.

Arithmetic Circuit The basic component of an arithmetic circuit is the parallel adder. By controlling the data inputs to the adder, it is possible to obtain different types of arithmetic operations . The diagram of a 4-bit arithmetic circuit is shown in Figure. It has four full-adder circuits that Constitute the 4-bit adder and four multiplexers for choosing different operations . There are two 4-bit inputs A and B and a 4-bit output D. The four inputs from A go directly to the X inputs of the binary adder. Each of the four inputs from B are connected to the data inputs of the multiplexers Fig :Circuit diagram of Arithmetic Circuit.

Arithmetic Circuit The multiplexers data inputs also receive the complement of B. The other two data inputs are connected to logic-0 and logic-1. The four multiplexers are controlled by two selection inputs S1 and S0. The input carry Cin , goes to the carry input of the FA in the least significant position. The other carries are connected from one stage to the next. By controlling the value of Y with the two selection inputs S1 and S0 and making Cin equal to 0 or 1, it is possible to generate the eight arithmetic micro operations listed in Table.

ADVANTAGES Low Power Consumption Smaller Chip Area Increased Speed Design Flexibility Lower Power Dissipation in Arithmetic Circuits Simple Implementation of Complex Logic

APPLICATIONS Low-power and high-speed digital circuits, especially in portable devices Arithmetic circuits Memory design, where low power consumption is crucial Signal processing applications.

REFERENCE Abebe Diro , Haftu Reda , Naveen Chilamkurti , Abdun Mahmood, Noor Zaman, and Yunyoung Nam. Lightweight authenticated-encryption scheme for internet of things based on publish-subscribe communication. IEEE Access, 8:60539–60551, 2020. [ 2] Devaraj Ezhilarasan , Velluru S. Apoorva , and Nandhigam Ashok Vardhan . Syzygium cumini extract induced reactive oxygen species-mediated apoptosis in human oral squamous carcinoma cells. Journal of Oral Pathology Medicine: Official Publication of the International Association of Oral Pathologists and the American Academy of Oral Pathology, 48(2):115–21, 2019. [ 3] Giovanni Fiengo . Alessandro di Gaeta. Angelo Palladino , and Veniero Giglio “Basic Concepts on GDI Systems.” Common Rail System for GDI Engines, 2013. [ 4] Kumutha Jayaraman , Bethou Adhisivam , Saravanan Nallasivan , R. Gokul Krishnan, Chinnathambi Kamalarathnam , Mangala Bharathi , Brent McSharry , et al. 38(2):198–202. [ 5] M. Kamaraju , K. Lal Kishore, and A. V. N. Tilak . Power optimized alu for efficient datapath . International Journal of Computer Applications, 50(4):427–59, 2010. [ 6] Hammad Khawar , Tariq Rahim Soomro , and Muhammad Ayoub Kamal. Machine learning for internet of things-based smart transportation networks . In Machine Learning for Societal Improvement, Modernization, and Progress, pages 112–134. IGI Global, 2022.

THANK YOU
Tags