Design of Alu in computer architecture.pptx

Design of alu

1. Design of Arithmetic and Logic Unit

2. Inside a computer, there is an Arithmetic Logic Unit (ALU), which is capable of performing logical operations (e.g. AND, OR, Ex-OR, Invert etc.) in addition to the arithmetic operations (e.g. Addition, Subtraction etc.). The control unit supplies the data required by the ALU from memory, or from input devices, and directs the ALU to perform a specific operation based on the instruction fetched from the memory. An arithmetic logic unit(ALU) is a major component of the central processing unit of the a computer system. It does all processes related to arithmetic and logic operations that need to be done on instruction words. Different operation as carried out by ALU can be categorized as follows – logical operations − These include operations like AND, OR, NOT, XOR, etc. Bit-Shifting Operations − This pertains to shifting the positions of the bits by a certain number of places either towards the right or left, which is considered a multiplication or division operations. Arithmetic operations − This refers to bit addition and subtraction. Although multiplication and division are sometimes used, these operations are more expensive to make. Multiplication and subtraction can also be done by repetitive additions and subtractions respectively.

3. A simple block diagram of a 4 bit ALU for operations and, or, xor and Add is shown here :

4. The circuit functionality of a 1 bit ALU is shown here, depending upon the control signal S 1 and S the circuit operates as follows: for Control signal S 1 = 0 , S = 0, the output is A And B , for Control signal S 1 = 0 , S = 1, the output is A Or B , for Control signal S 1 = 1 , S = 0, the output is A Xor B , for Control signal S 1 = 1 , S = 1, the output is Complemet

5. The arithmetic, logic and shift circuits can be combined into one ALU with common selection variables. Notations used: The subscript i designates a typical stage. Inputs A i and B i are applied to both the arithmetic and logic units. A particular microoperation is selected with input S 1 and S . A multiplexer at the output chooses between an arithmetic output in E i and a logic output in D i . The data in multiplexer are selected with inputs S 3 and S 2 . The other two data inputs to the multiplexer receive inputs A i-1 for the shiftright operation and A i+1 for the shift left operation. The output carry C i+1 of a given arithmetic stage must be connected to the input carry C i of the next stage

6. Function table for Arithmetic Logic Shift