Digital Electronics & Fundamental of Microprocessor-I

1
DEPARTMENT OF INFORMATION TECHNOLOGY &
ELECTRONICS ENGINEERING
“DIGITALELECTRONICSAND
FUNDAMENTALOFMICROPROCESSOR-I”
(COPYRIGHTREGISTRATIONNO. L-71129/2017)
DATTAMEGHEINSTITUTE OF MEDICAL SCIENCE’S
DATTA MEGHE INSTITUTE OF ENGINEERING, TECHNOLOGY & RESEARCH,
SAWANGI(MEGHE), WARDHA. 442001(MS)
AUTHOR
MR. PRAVINW. JARONDE
Presentation of Notes on

2
Copyright Certificate

PREFACE
Aseducators,weallhavethesamecommongoal“toguideourstudents”sothatthey
gainthemaximumpossibleinapositiveenvironmentthatpromotestheirsuccess
andinculcatesinthemdesiretolearn.Oneofthebesttoolsavailabletousinthis
pursuitisPPTinstructionthatissystematicandselfLearning.ThegoalofthisPPT
istohelpteachersintheuseofeLearningthatitisboth
effectiveandefficientmethodforteachingourstudents.Ithasbeendevelopedfor
purelyacademicandnon-commercialpurpose.
MydesireinpreparingthisPPTistosupporttheteachers,whohavethevery
demandingtaskofTeaching-Plantodeliverinstructiononalecture/periodbasis.
ThePPTisthereforepreparedlecturewise.Furtherattheendofeachchapter
summaryandalsoquestionsforpracticehasbeenprovidedonthesamechapter.
WebegininChapter1withbasicelementslikenumbersystem,logicgatesanditstruth
table.InChapters2welearnindetailstheformoffunctionandK-map.Chapter3we
learndetailsofcombinationalcircuitsandarithmeticcircuits.Chapter4wefocuson
typesofFlipflopsanditsapplicationascountersandregisters.
Withdeepregardsandhumility,IthankmyManagementofMGIformotivatingandour
CEOforstrongfollow-upstopreparePPTsunderDTELalsoDr.AshwinKothari,
AssociateProfessor,VNIT,Nagpurforhisvaluablesuggestions.IdedicatethisPPTto
mydearstudentsandmysharedprofession.
3PravinJaronde

CONTENT: DIGITAL CIRCUIT & FUNDAMENTAL OF MICROPROCESSOR
CHAPTER 1:
1
CHAPTER 2:
2
CHAPTER 3:
3
CHAPTER 4:
4
4
Basic of Digital Circuits
Logical Expression, Minimization
& Implementation
Combinational Circuit
Flip-flops
Slide No:05
Slide No:73
Slide No:108
Slide No:149

GENERAL OBJECTIVE
1
2
5
The student will be able to:
Distinguish form of expression and also simplify
functions using K-map.
Understand Number system, Gates and its truth table.
3
Design combinational and arithmetic circuit.
4
List different types of Flip-flops and Understand its
application as a Counter.

6
“DIGITALELECTRONICSAND
FUNDAMENTALOFMICROPROCESSOR”
CHAPTER–1
“BASICOFDIGITALCIRCUITS”

CHAPTER -1 Basic of Digital Circuits
Number system.1
Conversion of Number systems.
2
Logic Gates and Truth Table.
4
7
Function Realization using Gates.
5
Boolean Algebra.
3
Topic 1:
Topic 2:
Topic 3:
Topic 4:
Topic 5:

CHAPTER-1 SPECIFIC OBJECTIVE / COURSE OUTCOME
Learn number systems and can convert amongst themselves.
1
Understand Boolean algebra.
2
8
The student will be able to:
Know Logic Gate, Their types with Truth table
3
Design function using Logic gates
4

LECTURE 1:-NUMBER SYSTEM Number Systems
Thenumberthatweuseinourdaytodaylifeisadecimal
numbersystem.i.e.anumbersystemhaving10different
digits0to9.
Anumbercomprisesof10differentdigitsareknownas
decimalnumber.
Whichfurthercanbedefinedbyitsbase(radix).
Base(radix):-Itisthenumberofuniquedigits,including
zero,usedtorepresentnumbersinapositionalnumeral
system.
Exa.(254)10:-Isdecimalnumberhavingbase10.
9
9
Introduction to Number Systems

LECTURE 1:-NUMBER SYSTEM Number Systems
(254)10:-Isdecimalnumberhavingbase10.
Eachdigitcanbemultipliedwith10tothepowerdepending
onthepositionofthedigitinthatnumberwithpoweras
a‘0’forunitplaceandincreasingtowardsleftsidealong
thatnumberthenaddittogetequivalentdecimal
number.
Itcanbeelaborateas-
Inabovenumber4isunitplace,5is10
th
placeand4is
100
th
place.
Therefore
(254)10=2x10
2
+5x10
1
+4x10
0
=2x100+5x10+4x1=200+50+4=254.
10
10
Introduction to Number Systems

LECTURE 1:-NUMBER SYSTEM Number Systems
Ingeneralifthenumberis(ABCD)Rwhere“ABCD”isa4
digitnumberwithbase‘R’andthesamewantstobe
representindecimalformattheneachdigitismultiplied
withbase‘R’tothepowerdependingonitspositionin
thatnumber,withpowerofunitplaceis‘0’andaddit.
Itwillbeasfollows-
AxR
3
+BxR
2
+CxR
1
+DxR
0
Ifitis(ABCD.EF)R
Then
AxR
3
+BxR
2
+CxR
1
+DxR
0
+ExR
-1
+FxR
-2
11
11
Introduction to Number Systems

LECTURE 1:-NUMBER SYSTEM Various Number Systems
In general there are various types of Number systems
out of we are focusing on following types-
Decimal Number system
Binary Number system
Octal Number system
Hexadecimal Number system
Note :-Number can be identified by its radix(base)
12
12
Introduction to Number Systems

LECTURE 1:-NUMBER SYSTEM Various Number Systems
Decimal Number system
Definition-ItisaNumbersystemhaving10different
digitsi.e.from0to9.AndtheRadix(Base)ofthe
numberis10.
Examples :-
1) (514)
10
2) (8936)
10
3) (912.34)
10
Advantages:-Userfriendly,Easytorecognize,etc.
Disadvantage:-Formachineitistedious,Ifweconsidera
switchthen10differentstatesarerequired,Difficultto
implement. 13
13

LECTURE 1:-NUMBER SYSTEM Various Number Systems
Binary Number system
Definition-ItisaNumbersystemhavingtwodifferent
digitsi.e.0&1.AndtheRadix(Base)ofthenumberis2.
Examples :-
1) (1011)
2
2) (111000)
2
3) (101.11)
2
Advantages:-Asonlytwopossibilities,Machine
understandable,fastworking.
Disadvantage:-Torepresentbignumberlargewidthofbit
streamisused.
14
14

LECTURE 1:-NUMBER SYSTEM Various Number Systems
Octal Number system
Definition-ItisaNumbersystemhaving8differentdigits
i.e.0to7.AndtheRadix(Base)ofthenumberis8.
Examples :-
1) (571)
8
2) (1205)
8
3) (543.23)
8
Advantages:-Torepresentsingledigitinoctalthreebitsof
binaryisrequired.
Disadvantage:-Itisnotcommonlyused.
15
15

LECTURE 1:-NUMBER SYSTEM Various Number Systems
Hexadecimal Number system
Definition-ItisaNumbersystemhaving16different
digitsi.e.0to9andAtoF.AndtheRadix(Base)ofthe
numberis16.
Examples :-
1) (203)
16
2) (56AB)
16
3) (DCE.4A)
16
Advantages:-Torepresentsingledigitin
Hex,4binarybitsarerequired.
Mostlyusedformemoryaddressing.
16
16
For
Dec
Write
Hex as
10 A
11 B
12 C
13 D
14 E
15 F
Table 1.1 Dec to Hex

LECTURE 1:-NUMBER SYSTEM Various Number Systems
Signed Number
Inallkindofmathematicaloperationbothpositiveand
negativenumberareused.
Forexample,evenwhendealingwithpositivearguments,
mathematicaloperationsmayproduceanegativeresult:
Example:125–236=–111.
•Thusneedstobeaconsistentmethodofrepresenting
negativenumbersinbinarycomputerarithmeticoperations.
•Therearevariousapproaches,buttheyallinvolveusing
oneofthedigitsofthebinarynumbertorepresentthesign
ofthenumber.
•Twomethodsarethesign/magnituderepresentationand
theone’scomplementmethodofrepresentation. 17
17
Reference :-https://www.utdallas.edu/~dodge/EE2310/lec3.pdf

LECTURE 1:-NUMBER SYSTEM Various Number Systems
Binary Sign Representation
Sign-magnitude: The left bit is the sign (0 for + numbers
and 1 for –numbers).
One’scomplement:Thenegativenumberofthesame
magnitudeasanygivenpositivenumberisitsone’s
complement.
Ifm=01001100,thenmcomplement(orm)=10110011
Themostsignificantbitisthesign,andis0for+binary
numbersand–fornegativenumbers.
18
18
Reference :-https://www.utdallas.edu/~dodge/EE2310/lec3.pdf
Fig.1.1 Binary Sign Representation

LECTURE 1:-NUMBER SYSTEM Signed Unsigned Number
19
19
Table 1.2 Sign Unsigned Number

LECTURE 1:-NUMBER SYSTEM Various Number Systems
2’s Complement Negative Binary Number
•Duetotheproblemswithsign/magnitudeand1’s
complement,anotherapproachhasbecomethestandard
forrepresentingthesignofafixed-pointbinarynumberin
computercircuits.
•Considerthefollowingdefinition:“Thetwo’scomplement
ofabinaryintegeristhe1’scomplementofthenumber
plus1.”
Examples:
20
20
Reference :-https://www.utdallas.edu/~dodge/EE2310/lec3.pdf

LECTURE 1:-NUMBER SYSTEM Various Number Systems
2’s Complement Negative Binary Number
Convertinganegativedecimalnumberto2’scomplement
binary-
But:Positivedecimalnumbersareconvertedsimplyto
positivebinarynumbersasbefore(no2’scomplement).
Example:+67(usingmethodofsuccessivediv.)→0100
0011
21
21
Reference :-https://www.utdallas.edu/~dodge/EE2310/lec3.pdf

LECTURE 1:-NUMBER SYSTEM Various Number Systems
2’s Complement Binary to Decimal
Binary2’scomplement-to-decimalexamples,negative
numbers:
Butforapositivebinarynumber:
22
22
Reference :-https://www.utdallas.edu/~dodge/EE2310/lec3.pdf

LECTURE 1:-NUMBER SYSTEM Table for Various Number Systems
23
23
Sr. No.DecimalBinaryOctal Hexadecimal
0 0 0 0 0
1 1 1 1 1
2 2 2 2
3 3 3 3
4 4 4 4
5 5 5 5
6 6 6 6
7 7 7 7
8 8 8
9 9 9
10 A
11 B
12 C
13 D
14 E
15 F
Table 1.3 Various Number Systems

LECTURE 1:-NUMBER SYSTEM Conversion Among Bases
It is possible to convert any number system to any
number.
The possibilities:
Hexadecimal
Decimal Octal
Binary
24
24
Fig.1.2 Number Conversion Possibilities

25
LECTURE 2:-NUMBER SYSTEM Conversion Among Bases
Decimal to Binary
Dividethedecimalno.by2andcheckquotientifitisnot
lessthan2againdivideitby2tillquotientlessthan2,
andremainderofeachdivisionwillbetheanswer.For
writinganswerwehavetosequencetheremainderfrom
bottomtotop.Asshownbelow-
Exa:(15)
10= (?)
2
Ans :-(15)
10= (1111)
2
DivisionQuotientRemainderSequence
15 ÷2 7 1 LSB
7 ÷2 3 1
3 ÷2 1 1
1 1 MSB
Table 1.4 Decimal to Binary

26
LECTURE 2:-NUMBER SYSTEM Conversion Among Bases
Decimal to Binary
Ifthenumberisfractionalthenithastomultiplywith2,
separateresultintwopartsreal&fractionalrealpartis
binaryandfractionalpartisagainmultiplybytwo.
Repeatthistillresultisnotequalto1.0,theequivalent
binaryresultistherealpartoftheresultofeach
multiplication.Asshownbelow-
Exa: (0.125)
10= (?)
2
0.125 x 2 = 0.25
0.25 x 2 = 0.5
0.5 x 2 = 1.0
Ans-(0.125)
10= (0.001)
2
ResultFractionalBin
0.25 0.25 0 MSB
0.5 0.5 0
1.0 0.0 1 LSB
Table 1.5 Decimal to Binary

27
LECTURE 2:-NUMBER SYSTEM Conversion Among Bases
Decimal to Octal
Dividethedecimalno.by8andcheckquotientifitisnot
lessthan8againdivideitby8tillquotientlessthan8,
andremainderofeachdivisionwillbetheanswer.For
writinganswerwehavetosequencetheremainderfrom
bottomtotop.Asshownbelow-
Exa:(30)
10= (?)
8
Ans :-(30)
10= (36)
8
DivisionQuotientRemainderSequence
30 ÷8 3 6 LSB
3 3 MSB
Table 1.6 Decimal to Octal

28
LECTURE 2:-NUMBER SYSTEM Conversion Among Bases
Decimal to Hexadecimal
Dividethedecimalno.by16andcheckquotientifitis
notlessthan16againdivideitby16tillquotientless
than16,andremainderofeachdivisionwillbethe
answer.Forwritinganswerwehavetosequencethe
remainderfrombottomtotop.Asshownbelow-
Exa:(56)
10= (?)
16
Ans :-(56)
10= (38)
16
DivisionQuotientRemainderSequence
56 ÷16 3 8 LSB
3 3 MSB
Table 1.7 Decimal to Hexadecimal

29
LECTURE 2:-NUMBER SYSTEM Conversion Among Bases
Binary to Decimal
Multiplyeachbinarybitwith2tothepowerthatbits
positionasLSBbitis0
th
positionitincreasesfromright
toleftbyone,thenaddallproductstogetequivalent
decimalnumber.Asshownbelow-
Exa:(101)
2= (?)
10
(1 0 1)
2 (101)
2= 1x2
2
+ 0x2
1
+ 1x2
0
= 4 + 0 + 1
MSB LSB = (5)
10
(2
nd
position) (0
th
position)
Ans :-(101)
2= (5)
10

30
LECTURE 2:-NUMBER SYSTEM Conversion Among Bases
Binary to Decimal
1)(10110)
2
(10110)
2=1x2
4
+0x2
3
+1x2
2
+1x2
1
+0x2
0
=16+0+4+2+0
=(22)
10
2)(111.01)
2
(111.01)
2=1x2
2
+1x2
1
+1x2
0
+0x2
-1
+0x2
-2
=4+2+1+0.5+0.25
=(7.75)
10

31
LECTURE 2:-NUMBER SYSTEM Conversion Among Bases
Octal to Decimal
Multiplyeachoctalbitwith8tothepowerthatbits
positionasLSBbitis0
th
positionitincreasesfromright
toleftbyone,thenaddallproductstogetequivalent
decimalnumber.Asshownbelow-
Exa:(512)
8= (?)
10
(5 1 2)
8 (512)
8= 5x8
2
+ 1x8
1
+ 2x8
0
= 320 + 8 + 2
MSB LSB = (330)
10
(2
nd
position) (0
th
position)
Ans :-(512)
8= (330)
10

32
LECTURE 2:-NUMBER SYSTEM Conversion Among Bases
Octal to Decimal
1)(1011)
8=(?)
10
(1011)
8= 1x8
3
+ 0x8
2
+ 1x8
1
+ 1x8
0
= 512 + 1 + 8 +1
= (522)
10
2) (53.11)
8= (?)
10
(53.11)
8= 5x8
1
+ 3x8
0
+ 1x8
-1
+ 1x8
-2
= 40 + 3 + 0.125 + 0.0156
= (43.14)
10

33
LECTURE 2:-NUMBER SYSTEM Conversion Among Bases
Hexadecimal to Decimal
MultiplyeachHexadecimalbitwith16tothepowerthat
bitspositionasLSBbitis0
th
positionitincreasesfrom
righttoleftbyone,thenaddallproductstoget
equivalentdecimalnumber.Asshownbelow-
Exa:(32)
16= (?)
10
(3 2)
16 (32)
16= 3x16
1
+ 2x16
0
= 48 + 2
MSB LSB = (50)
10
(1
st
position) (0
th
position)
Ans :-(32)
16= (50)
10

34
LECTURE 2:-NUMBER SYSTEM Conversion Among Bases
Hexadecimal to Decimal
1)(BD2)
16=(?)
10
(BD2)
16= 11x16
2
+ 13x16
1
+ 2x16
0
= 2816 + 208 + 2
= (3026)
10
2)(E4.3F)
16=(?)
10
(E4.3F)
16= 14x16
1
+ 4x16
0
+ 3x16
-1
+ 15x16
-2
= 224 + 64 + 0.1875 + 0.0586
= (288.24)
10

35
LECTURE 2:-NUMBER SYSTEM Conversion Among Bases
Octal to Binary
Torepresenteachoctalbitthereisrequirementofminimum
3binarybits.Hencetheconversioncanbedoneasbelow-
Exa: 1) (32)
8= (?)
2 2) (54.75)
8= (?)
2
(3 2)
8 (5 4 7 2)
8
(011 010)
2 (101 100 111 010)
2
Ans :-(32)
8= (011010)
2Ans :-(54.75)
8= (101100.111010)
2

36
LECTURE 2:-NUMBER SYSTEM Conversion Among Bases
Binary to Octal
Wehavetomakegroupof3binarybitformakingitinto
equivalentoctal.Ifthebinarystreamhavelessthan
multipleof3bitsthenitisrequiredtopadzeros.Hencethe
conversioncanbedoneasbelow-
Exa: 1) (101110)
2= (?)
8 2) (1011.11)
2= (?)
8
(101 110)
2 (001 011 . 110)
2
( 5 6)
8 (1 3 . 6)
8
Ans :-(101110)
2= (56)
8 Ans :-(1011.11)
2= (13.6)
8

BinarytoOctal:- OctaltoBinary:-
1) (10111)
2= (?)
8 1)(734)
8= (?)
2
= (010 111)
8 (734)
8= (111 011 100)
2
= (2 7)
8
2) (101011101)
2= (?)
8 2)(65)
8= (?)
2
= (101 011 101)
8 (65)
8= (110 101)
2
= (5 3 5)
8
37
LECTURE 2:-NUMBER SYSTEM Conversion Among Bases

38
LECTURE 3:-NUMBER SYSTEM Conversion Among Bases
Hexadecimal to Binary
TorepresenteachHexadecimalbitthereisrequirementof
minimum4binarybits.Hencetheconversioncanbedone
asbelow-
Exa: 1) (68)
16= (?)
2 2) (91.8)
16= (?)
2
(6 8)
16 (9 1 . 8)
16
(0110 1000)
2 (1001 0001 . 1000)
2
Ans :-(68)
16= (01101000)
2Ans :-(91.8)
16= (10010001.1000)
2

39
LECTURE 3:-NUMBER SYSTEM Conversion Among Bases
Binary to Hexadecimal
Wehavetomakegroupof4binarybitformakingitinto
equivalentHexadecimal.Ifthebinarystreamhavelessthan
multipleof4bitsthenitisrequiredtopadzeros.Hencethe
conversioncanbedoneasbelow-
Exa: 1) (10111001)
2= (?)
16 2) (101111.101)
2= (?)
16
(1011 1001)
2 (0010 1111 . 1010)
2
(B 9)
16 (2 F . A)
16
Ans :-(10111001)
2= (B9)
16Ans :-(101111.101)
2= (2F.A)
16

BinarytoHexadecimal:- HexadecimaltoBinary:-
1) (10111)
2= (?)
16 1)(734)
16= (?)
2
= (0001 0111)
16 (734)
16= (0111 0011 100)
16
= (1 7)
16
2) (10101111)
2= (?)
16 2)(C4)
16= (?)
2
= (1010 1111)
16 (C4)
16= (1100 0100)
2
= (A F)
16
40
LECTURE 3:-NUMBER SYSTEM Conversion Among Bases

41
LECTURE 3:-NUMBER SYSTEM Conversion Among Bases
Octal to Hexadecimal
Directlythisconversionisnotpossible.Wehavetogo
throughbinaryorthroughdecimal.Asshownbelow-
Exa:(27)
8= (?)
16
(2 7)
8 (0001 0111)
2
(010 111)
2 (1 7)
16
(010111)
2 = (?)
16
Ans :-(27)
8= (17)
16

42
LECTURE 3:-NUMBER SYSTEM Conversion Among Bases
Hexadecimal to Octal
Directlythisconversionisnotpossible.Wehavetogo
throughbinaryorthroughdecimal.Asshownbelow-
Exa:(39)
16= (?)
8
(3 9)
16 (000111 001)
2
(0011 1001)
2 (0 7 1)
8
(00111001)
2 = (?)
8
Ans :-(39)
16= (71)
8

Exercise –Convert ...
Don’t use a calculator!
DecBinaryOctalHex-veDec
33
1110101
703
1AF
-54
43
LECTURE 3:-NUMBER SYSTEM
Do the conversion and complete the Table
Table 1.8 Conversion Table

Various Codes
44
LECTURE 3:-NUMBER SYSTEM
Codes
Inthecoding,whennumbers,lettersorwordsare
representedbyaspecificgroupofsymbols,itissaidthatthe
number,letterorwordisbeingencoded.Thegroupof
symbolsiscalledasacode.Thedigitaldataisrepresented,
storedandtransmittedasgroupofbinarybits.Thisgroupis
alsocalledasbinarycode.Thebinarycodeisrepresented
bythenumberaswellasalphanumericletter.
Thecodesarebroadlycategorizedintofollowingfour
categories.
•Weighted Codes
•Non-Weighted Codes
•Binary Coded Decimal Code
•Alphanumeric Codes
Reference :-http://www.tutorialspoint.com/computer_logical_organization/binary_codes.htm

Various Codes
45
LECTURE 3:-NUMBER SYSTEM
Advantages of Binary Code
•Binary codes are suitable for the computer applications.
•Binary codes are suitable for the digital communications.
•Binary codes make the analysis and designing of digital
circuits if we use the binary codes.
•Since only 0 & 1 are being used, implementation becomes
easy.
Reference :-http://www.tutorialspoint.com/computer_logical_organization/binary_codes.htm

Various Codes
46
LECTURE 3:-NUMBER SYSTEM
Weighted Codes
Weightedbinarycodesarethosebinarycodeswhichobey
thepositionalweightprinciple.Eachpositionofthenumber
representsaspecificweight.Severalsystemsofthecodes
areusedtoexpressthedecimaldigits0through9.Inthese
codeseachdecimaldigitisrepresentedbyagroupoffour
bits.
Reference :-http://www.tutorialspoint.com/computer_logical_organization/binary_codes.htm
Fig.1.3 Weighted Code

Various Codes
47
LECTURE 3:-NUMBER SYSTEM
Non-Weighted Codes
Inthistypeofbinarycodes,thepositionalweightsarenot
assigned.Theexamplesofnon-weightedcodesareExcess-
3codeandGraycode.
Excess-3code
TheExcess-3codeisalsocalledasXS-3code.Itisnon-
weightedcodeusedtoexpressdecimalnumbers.The
Excess-3codewordsarederivedfromthe8421BCDcode
wordsadding(0011)2or(3)10toeachcodewordin8421.
Theexcess-3codesareobtainedasfollows−
Reference :-http://www.tutorialspoint.com/computer_logical_organization/binary_codes.htm
Fig.1.4 Non-Weighted Code

Various Codes
48
LECTURE 3:-NUMBER SYSTEM
Excess-3 code
Reference :-http://www.tutorialspoint.com/computer_logical_organization/binary_codes.htm
Fig.1.9 Excess-3 Code

Various Codes
49
LECTURE 3:-NUMBER SYSTEM
Gray Code
Itisthenon-weightedcodeanditisnotarithmeticcodes.
Thatmeanstherearenospecificweightsassignedtothebit
position.Ithasaveryspecialfeaturethat,onlyonebitwill
changeeachtimethedecimalnumberisincrementedas
showninfig.Asonlyonebitchangesatatime,thegraycode
iscalledasaunitdistancecode.Thegraycodeisacyclic
code.Graycodecannotbeusedforarithmeticoperation.
Application of Gray code
•Graycodeispopularlyusedintheshaftpositionencoders.
•Ashaftpositionencoderproducesacodewordwhich
representstheangularpositionoftheshaft.
Reference :-http://www.tutorialspoint.com/computer_logical_organization/binary_codes.htm

Various Codes
50
LECTURE 3:-NUMBER SYSTEM
Gray Code
Reference :-http://www.tutorialspoint.com/computer_logical_organization/binary_codes.htm
Table 1.10 Gray Code

Various Codes
51
LECTURE 3:-NUMBER SYSTEM
Binary Coded Decimal (BCD) code
Inthiscodeeachdecimaldigitisrepresentedbya4-bit
binarynumber.BCDisawaytoexpresseachofthedecimal
digitswithabinarycode.IntheBCD,withfourbitswecan
representsixteennumbers(0000to1111).ButinBCDcode
onlyfirsttenoftheseareused(0000to1001).Theremaining
sixcodecombinationsi.e.1010to1111areinvalidinBCD.
Reference :-http://www.tutorialspoint.com/computer_logical_organization/binary_codes.htm
Table 1.11 Decimal to BCD

Various Codes
52
LECTURE 3:-NUMBER SYSTEM
Binary Coded Decimal (BCD) code
Advantages of BCD Codes
Itisverysimilartodecimalsystem.
Weneedtorememberbinaryequivalentofdecimalnumbers
0to9only.
DisadvantagesofBCDCodes
TheadditionandsubtractionofBCDhavedifferentrules.
TheBCDarithmeticislittlemorecomplicated.
BCDneedsmorenumberofbitsthanbinarytorepresentthe
decimalnumber.SoBCDislessefficientthanbinary.
Reference :-http://www.tutorialspoint.com/computer_logical_organization/binary_codes.htm

Various Codes
53
LECTURE 3:-NUMBER SYSTEM
The ASCII Alphanumeric Code
ASCIIcoderepresentsalphanumericdatainmostcomputers
(“AmericanStandardCodeforInformationInterchange”).
•DataonthistransparencyiscodedinASCII.
•ASCIIcodesareusedforvirtuallyallprinterstoday.
•InthebasicASCIIcodethatwewillstudy,asinglebyteis
usedforeachcharacter.Theleastsignificant7bitsrepresent
thecharacter.Theeighthbit(themostsignificantbit,orMSB)
maybeusedforerrorchecking.
“SuperASCII”codescanuseall8bits(ormore)foreven
moreelaboratecodes,suchasotheralphabetsand
charactersets(Greek,Katakana,etc.).
Reference :-http://www.tutorialspoint.com/computer_logical_organization/binary_codes.htm

Various Codes
54
LECTURE 3:-NUMBER SYSTEM
The ASCII Alphanumeric Code
•Thereare128basicASCIIcharacters,0-12710,or0-7f16
(00000000to01111111binary).
•EachASCIIcodeisunique,forexample:
-M=01001101=7710=4D16.
-m=01101101=10910=6D16.
-Notethatthesmalllettersareexactly3210(20hex)
largerinnumericalvaluethanthecapitalletters.
•ASCIIcharactersarestoredasbytesinthecomputer.
•ASCIIcharactersarenormallyrepresentedaspairsofhex
numbers(since1byte=2nibbles=2hexnumbers).
Reference :-http://www.tutorialspoint.com/computer_logical_organization/binary_codes.htm

GeorgeBoolehaspostulatedvariouslawsfor
minimizationofanyexpression.Thetheoryknownas
BooleanAlgebra.Itisthealgebraoflogic.
Ithavingfollowinglaws:-
1)‘OR’law:-
A+0=A A+1=1
A+A=A A+A’=1
2)‘AND’Law:-
A.0=0 A.1=A
A.A=A A.A’=0
LECTURE 4:-BOOLEAN ALGEBRA Various Laws
55
Boolean Algebra

3) ‘Complement’ law :-
0’ = 1 1’ = 0
If A = 0 A’ = 1
If A = 1 A’ = 0
(A’)’ = A
4) ‘Commutative’ Law:-
A + B = B + A ;A . B = B . A
5) ‘Associative’ Law :-
(A + B) + C = A + (B + C)
(A + B) + (C + D) = A + B + C + D
A . (B . C) = (A . B) . C
LECTURE 5:-BOOLEAN ALGEBRA
56
Various Laws
Boolean Algebra

6) ‘Distributive’ law:-
A . (B + C) = (A . B) + (A . C)
A + (B . C) = (A + B) . (A + C)
7) ‘Absorption’ Law :- 9) ‘X-OR’ Law:-
A + (A . B) = A AA= 0
A . (A + B) = A AA’ = 1
A . (A’ + B) = A . B
8) De Morgan’s Law :- 10) ‘X-NOR’ Law:-
(A + B)’ = A’ . B’ A A= 1
(A . B)’ = A’ + B’ A A’ = 0
LECTURE 5:-BOOLEAN ALGEBRA
57
Various Laws
Boolean Algebra

De Morgan’s 1
st
Theorem :-
ItStatesthatthecomplementofproductofvariables
isequaltothesumoftheirindividualcomplements.
(A.B)’=A’+B’
LECTURE 5:-BOOLEAN ALGEBRA
58
A B A.B (A.B)’ A’ B’ A’+B’
0 0 0 1 1 1 1
0 1 0 1 1 0 1
1 0 0 1 0 1 1
1 1 1 0 0 0 0
Various Laws
De Morgan’s Theorem
De Morgan’s stated two theorems as follows -
Table 1.12 De Morgan’s 1
st
Theorem

De Morgan’s 2
nd
Theorem :-
ItStatesthatthecomplementofsumofvariablesis
equaltotheproductoftheirindividualcomplements.
(A+B)’=A’.B’
LECTURE 5:-BOOLEAN ALGEBRA
59
A B A+B (A+B)’ A’ B’ A’.B’
0 0 0 1 1 1 1
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 0
Various Laws
Table 1.13 De Morgan’s 2
nd
Theorem

Logic Gates
Gatescanbedefinedthelogicdevicewhichcanmakes
thelogicdecision.Ithasoneormanyinputsandone
output.
The various gates is as below -
•NOT gates (also called inverters),
•AND gates,
•OR gates,
•NAND gates,
•NOR gates,
•XOR gates, and
•XNOR gates.
LECTURE 6:-LOGIC GATES
60
Various Gates

NOT Gate (IC7404)
•NOT Gate can be defined as a gate which can invert (or
complement) the input at the output.
•NOT Gates or invertershave a single bit input and a single bit
of output.
Truth Table 1.14 NOT Gate
Input Output
X Z
0 1
1 0
LECTURE 6:-LOGIC GATES
61
Basic Gates
Fig.1.4 NOT Gate

AND Gate (IC7408)
•ANDGatehavetwoormorebitsofinputandasinglebit
ofoutput.
•Itproduceoutputasa‘1’ifalltheinputsare‘1’otherwise
outputis‘0’.
TruthTable1.15ANDGate
InputOutput
X
1 X
0 Z
0 0 0
0 1 0
1 0 0
1 1 1
LECTURE 6:-LOGIC GATES
62
Basic Gates
Fig.1.5 AND Gate

OR Gate(IC7432)
•ORGatehavetwoormorebitsofinputandasinglebit
ofoutput.
•Itproducesoutputasa‘0’ifalltheinputsare‘0’
otherwiseoutputis‘1’.
TruthTable1.16ORGate
Input Output
X
1 X
0 Z
0 0 0
0 1 1
1 0 1
1 1 1
LECTURE 6:-LOGIC GATES
63
Basic Gates
Fig.1.6 OR Gate

NAND Gate(IC7400)
•NAND Gate have two or more bits of input and a single
bit of output.
•When all the input are ‘1’ then the output is ‘0’ otherwise
output is ‘1’.
•It can be form AND Gate followed by NOT Gate.
Truth Table 1.17 NAND Gate
Input Output
X
1 X
0 Z
0 0 1
0 1 1
1 0 1
1 1 0
LECTURE 6:-LOGIC GATES
64
Universal Gates
Fig.1.7 NAND Gate

NOR Gate(IC7402)
•NOR Gate have two or more bits of input and a single bit
of output.
•When all the input are ‘0’ then the output is ‘1’ otherwise
output is ‘0’.
•It can be form OR Gate followed by NOT Gate.
Truth Table 1.18 NOR Gate
InputOutput
X
1 X
0 Z
0 0 1
0 1 0
1 0 0
1 1 0
LECTURE 6:-LOGIC GATES
65
Universal Gates
Fig.1.8 NOR Gate

Ex-OR Gate(IC7486)
•Ex-ORGatehavetwoormorebitsofinputandasinglebit
ofoutput.ThisisalsocalledasDerivedGate.
•Truthtableshownbelowtellsthatwheninputsare
differentoutputis‘1’andwheninputsaresameoutputis
‘0’.
TruthTable1.19X-ORGate
Input Output
X
1 X
0 Z
0 0 0
0 1 1
1 0 1
1 1 0
LECTURE 6:-LOGIC GATES
66
Derived Gates
Fig.1.9 X-OR Gate

Ex-NOR Gate
•Ex-NORGatehavetwoormorebitsofinputandasingle
bitofoutput.ThisisalsocalledasDerivedGate.
•Truthtableshownbelowtellsthatwheninputsare
differentoutputis‘0’andwheninputsaresameoutputis
‘1’.
TruthTable1.20X-NORGate
Input Output
X
1 X
0 Z
0 0 1
0 1 0
1 0 0
1 1 1
LECTURE 6:-LOGIC GATES
67
Derived Gates
Fig.1.10 X-NORGate

Universal Gates
•ItcanbedefinedasaGatebywhichonecandesignany
gateoranyBooleanexpression.
•NANDgateandNORgatearecalledasUniversalgate.
Exa:-
1)NANDasNOT 2)NORasNOT
HenceoutputisthecomplementofinputthereforeNAND
gateandNORgateareknownasUniversalgates.
LECTURE 7:-LOGIC GATES
68
Universal Gates
Fig.1.11 NAND as NOT Gate Fig.1.12 NOR as NOT Gate

Realize the following function using basic gates
•F=AB+AC’+AB’C
Asthefunctionhave3producttermssoitrequires3AND
gates,2complementvariablesso2NOTgatesandall
producttermsareORedwitheachotherhence1ORgate.
Designisasbelow-
LECTURE 7:-LOGIC GATES Gate Realization
69
Fig.1.13 Realized above function

Realize the following function using NAND gates
•F=AB+AC’+AB’C
SamefunctioncanberealizeusingNANDgate(Universal
gate.Designisasbelow-
LECTURE 7:-LOGIC GATES Gate Realization
70
Fig.1.14 Realized above function

LECTURE 8:-
71
•Modern digital Electronics-R. P. Jain, McGraw Hill.
•Digital Integrated Electronics-Herbert Taub, McGraw Hill.
•Digital Logic and Computer Design-Morris Mano(PHI).
•Digital Integrated Electronics-Herbert Taub, McGraw Hill.
•Digital Electronics Logic and System –James Bingnelland Robert
Donovan, CengageLearning
•Digital Circuits & Systems by K.R.Venugopal& K. Shaila
•http://npteldownloads.iitm.ac.in/downloads_mp4/117106086/lec01.mp4
•http://www.digital.iitkgp.ernet.in/dec/index.php
•http://vlab.co.in/ba_nptel_labs.php?id=1
•http://www.tutorialspoint.com/computer_logical_organization/binary_cod
es.htm
•https://www.utdallas.edu/~dodge/EE2310/lec3.pdf
Chapter 1 References

LECTURE 8:-
72
Summary
1.The Number systems are:
i) Decimal Number Systems ii) Binary Number Systems
iii) Octal Number Systems iv) Hexadecimal Number Systems
2. 2-types for form of function available in digital electronics:
i) Sum of Product (POS) ii) Product of Sum (POS)
3. Boolean Algebra having following laws:
i)OR law ii) AND law iii) Complement law iv) Commutative law.
v) Associative law vi) Distributive law vii) Absorption law.
viii) Demorgan’slaw -are of two types:
a)Demorgan’sFirst law - (A.B)’ = A’ + B’
b)Demorgan’sSecond law - (A + B)’ = A’.B’
4. Logic Gates are following type use to implement any function.
i) NOT gate ii) AND gate iii) OR gate iv) NAND gate
v) NOR gate vi) Ex-OR gate vii) Ex-NOR gate.
5. Universal gate using can implement any Boolean function or any
gate NAND and NOR gates are the examples of Universal gate.

LECTURE 8:-
73
•Explain the number system and itstypes in details.
•Perform the following conversions :-
a) (320.72)
10→ ( )
8 → ( )
2 b) (4B.2E)
16→ ( )
10 → ( )
8
c) (27A5.3B)
16 = (?)
D d) (10110111)
Gray= (?)
Binary
e) (A3FE)
H = (?)
B f) (306.D)
H= (?)
B
g) (275)
8 = (?)
2 h) (673.124)
8= (?)
2
i) (101101.10101)
2= (?)
10 j) (543.265)
8= (?)
10
•41/3 = (13)
10find the base of the number system.
•Define gates. Why NAND & NOR are called as Universal gates.
•What is Boolean algebra ?
•State & Prove De-Morgan’
s
laws.
•Design X-OR gate using 4 NAND gate.
•Realize the function using NAND gate and NOR gate.
a) F = ABCD + AC’ D+ AB’C D’
b) F = A’BC’ + ABC’ + A’CD’
c) F = (A+B)(A+C’+D)(A+B’+C+D)
d) F = (A+B+C’+D)(A+B’+C’+D)(A+C+D)
Chapter 1 Question Bank

74
“DIGITALELECTRONICSAND
FUNDAMENTALOFMICROPROCESSOR”
CHAPTER–2
“LOGICALEXPRESSION, MINIMIZATION&
IMPLEMENTATION”

CHAPTER 2:-LOGICAL EXPRESSION, MINIMIZATION &
IMPLEMENTATION
Sum of Product and Product of Sum1
Standard SOP and Standard POS2
Minterm and Maxterm
3
Introduction to Karnaugh-map (K-map)
4
75
Simplification of function using K-map5
Topic 1:
Topic 2:
Topic 3:
Topic 4:
Topic 5:

CHAPTER-2 SPECIFIC OBJECTIVE / COURSE OUTCOME
Distinguish various form of function.
1
Convert function into standard form
2
76
The student will be able to:
Differentiate product term, sum term, minterm and maxterm
3
Understand the concept of K-map
4
Minimize function using K-map5

77
LECTURE 9:-Form of Function Expression
BasicallytherearetwotypesofBooleanfunctions–
1)SumofProduct(SOP)
2)ProductofSum(POS)
Sum of Product (SOP)
This is a function having all product terms connected
with OR sign (+).
Exa:-F(A,B,C) = AB + BC + A’BC’
Product of Sum (POS)
This is a function having all sum terms connected with
AND sign (.).
Exa:-F(A,B,C) = (A+B’) . (B’+C) . (A+B+C)

78
Standard Form of Function
Standard SOP or Standard POS
FunctioncanbecalledasinStandardformifinthat
function(i.e.SOP)producttermshavealltheliterals
eitherindirectorcomplementform,or(i.e.POS)sum
termshavingalltheliteralseitherindirector
complementform.
SSOPandSPOSalsocalledCanonicalform.
1)StandardSumofProduct(SSOP)
Exa:-F(A,B,C)=ABC+A’BC+A’BC’
2)StandardProductofSum(SPOS)
Exa:-F(A,B,C) = (A+B’+C) . (A+B+C)
LECTURE 9:-Form of Function

79
Minterm
Minterm
Itisaproducttermhavingalltheliteralseitherindirect
orcomplementform.
Exa:-F(A,B,C)=ABC+A’BC+A’BC’
Abovefunctioncontainsalltheproducttermshavingall
thevariablesasitisgiveninthefunction.Andhenceall
theproducttermcanbecalledasaminterm.
Henceallthemintermcanbeproducttermbutallthe
producttermsmaynotbeminterm.
LECTURE 9:-Form of Function

80
MAXTERM
MAXTERM
ItisaSumtermhavingalltheliteralseitherindirector
complementform.
Exa:
Exa:-F(A,B,C)=(A+B’+C).(A+B+C)
Abovefunctioncontainsallthesumtermshavingallthe
variablesasitisgiveninthefunction.Andhenceallthe
sumtermcanbecalledasamaxterm.
Henceallthemaxtermcanbesumtermbutallthesum
termsmaynotbemaxterm.
LECTURE 9:-Form of Function

TominimizeBooleanFunctionitisfounddifficultby
usingBooleanAlgebra.HencethescientistKarnaugh
hasinventednewtechniqueofboxestoreducethe
functionknownasK-Map.
IfthefunctionisinSOPform‘1’shouldbeenterinto
theK-mapforthegivenminterm.
IfthefunctionisinPOSform‘0’shouldbeenterinto
theK-mapforthegivenMAXTERM.
TherearebasicallyfollowingtypesofK-maps
1. 2 variable K-map.
2. 3 variable K-map.
3. 4 variable K-map.
4. 5 variable K-map.
LECTURE 10:-K-MAP Various K-Map
81
Introduction to K-Map

LECTURE 10:-K-MAP
2 -Variable K-map (SOP)
82
•There are four minterms for two variables.
•Number of Squares = 2^(Number of Variables).
•It consists of 4 squares, one for each minterm.
•Priority of groups 4,2,1
AB
B
A
F = AB F = A + B
Various K-Map
Fig.2.1: 2-Variable K-maps

LECTURE 10:-K-MAP
3 -Variable K-map (SOP)
83
•Thereareeightmintermsforthreevariables.
•Mapconsistsof8squares,oneforeachminterm.
•Priorityofgroups–8,4,2,1
Various K-Map
Fig.2.2: 3-Variable K-maps

LECTURE 10:-K-MAP
84
SimplifytheBooleanfunction-
1)F(A,B,C)=∑m(3,4,6,7)
F=AC’+BC
2)F(A,B,C)=∑m(1,2,3,5,7)
F=C+A’B
3 -Variable K-map (SOP)
AC’
BC
A’B
C
Various K-Map
Fig.2.3: 3-Variable K-maps
Fig.2.4: 3-Variable K-maps

LECTURE 10:-K-MAP
85
•Thereare16mintermsforfourvariables.
•Mapconsistsof16squares,oneforeachminterm.
•Priorityofgroups–16,8,4,2,1
4 -Variable K-map(SOP)
Various K-Map
Fig.2.5: 4-Variable K-maps

LECTURE 10:-K-MAP
86
SimplifytheBooleanfunction-
F(A,B,C,D)=∑m(0,1,2,4,5,6,13,15)
F=A’C’+A’D’+ABD
4 -Variable K-map(SOP)
A’C’
A’D’
ABD
Various K-Map
Fig.2.6: 4-Variable K-maps

LECTURE 10:-K-MAP
87
5 -Variable K-map(SOP)
Various K-Map
•Thereare32mintermsforfivevariables.
•Mapconsistsof32squares,oneforeachminterm.
•Priorityofgroups–32,16,8,4,2,1
Fig.2.7: 5-Variable K-maps

LECTURE 10:-K-MAP
88
SimplifytheBooleanfunction-
F(A,B,C,D,E)=∑m(0,1,2,4,5,6,9,11,16,17,20,21,25,27)
5 -Variable K-map(SOP)
Various K-Map
A’B’E’ B’D’BC’E
F(A,B,C,D,E) = A’B’E’ + B’D’ + BC’E
Fig.2.8: 5-Variable K-maps

LECTURE 11:-K-MAP
2 -Variable K-map (POS)
89
•There are four MAXTERMS for two variables
•Number of Squares = 2^(Number of Variables)
•It consists of 4 squares, one for each MAXTERM
•Priority of groups 4,2,1
Various K-Map
Fig.2.9: 2-Variable K-maps

LECTURE 11:-K-MAP
3 -Variable K-map (POS)
90
•ThereareeightMAXTERMSforthreevariables
•Mapconsistsof8squares,oneforeachMAXTERM
•Priorityofgroups–8,4,2,1
Various K-Map
Fig.2.10: 3-Variable K-maps

LECTURE 11:-K-MAP
91
SimplifytheBooleanfunction-
1)F(A,B,C)=ПM(0,1,2,3,7)
F=A.(B’+C’)
2)F(A,B,C)=ПM(2,3,4,5,6,7)
F=A’+B’
3 -Variable K-map (POS)
B’+C’
A
A’
B’
Various K-Map
Fig.2.11: 3-Variable K-maps
Fig.2.12: 3-Variable K-maps

LECTURE 11:-K-MAP
92
•Thereare16MAXTERMSforfourvariables
•Mapconsistsof16squares,oneforeachMAXTERM
•Priorityofgroups–16,8,4,2,1
4 -Variable K-map(POS)
Various K-Map
Fig.2.13: 4-Variable K-maps

LECTURE 11:-K-MAP
93
SimplifytheBooleanfunction-
F(A,B,C,D)=ПM(0,1,2,4,5,6,9,11,13,15)
F=(A+D).(A’+D’).(A+C)
4 -Variable K-map(POS)
A+D
A’+D’
A+C
Various K-Map
Fig.2.14: 4-Variable K-maps

LECTURE 11:-K-MAP
94
•6variable,7variableandalsomorethanthatK-map
isalsoavailableanditisfoundmoretediousto
minimizeit.
•Sothetabularmethodwhichisalsoknownasthe
Quine-McCluskeymethodisparticularlyusefulwhen
minimisingfunctionshavingalargenumberof
variables.
More Than 5-Variable K-map(POS)
Various K-Map

LECTURE 12:-DON’T CARE Don’t Care Condition
95
•Insomedigitalsystem,certaininputconditionsnever
occursduringnormaloperationtherefore
correspondingoutputneverappears,knownasDon’t
CareCondition.
•Itisindicatedby‘x’inthetruthtableaswellask-map.
•‘x’inak-map,willbeconsideredas‘0’or‘1’forPOS
andSOPrespectively.
Introduction

LECTURE 12:-DON’T CARE Don’t Care Condition
96
SimplifyusingK-map:-
F(A,B,C,D)=∑m(0,1,2,5,8,14)+d(4,10,13)
F=A’C’+B’D’+ACD’
Note:-Formakingagroupofmaximumnumberof‘1’,don’tcare‘x’
canbeconsideredasa‘1’.Otherwise‘x’canbeignore.
B’D’
A’C’
ACD’
Example
Fig.2.15: 4-Variable K-maps

LECTURE 12:-DON’T CARE Don’t care condition
97
SimplifyusingK-map:-
F(A,B,C,D)=ПM(0,1,2,5,8)+d(7,12,14)
F=(A+B+D).(A+C+D’).(A’+C+D)
Note:-Formakingagroupofmaximumnumberof‘0’,don’tcare‘x’
canbeconsideredasa‘0’.Otherwise‘x’canbeignore.
A’+C+D
A+C+D’
A+B+D
Example
Fig.2.16: 4-Variable K-maps

LECTURE 13:-DON’T CARE Conversion SOP to POS
98
Example:-ConvertthefollowingSOPintoPOS.
F(A,B,C)=AB+A’BC+AC’
ThereforeF’(A,B,C)=A’C’+B’C
F(A,B,C)=(A’C’+B’C)’
=(A’C’)’.(B’C)’
=(A+C).(B+C’)----------(POS)
Fig.2.17 Form given expression Fig.2.18 Groups of zeros
A’C’
B’C
Example

LECTURE 13:-CODE CONVERTER
BCD to 7-seg decoder
99
•AdigitaldisplaythatconsistofsevenLEDsegments.
•Commonlyusedtodisplaydecimalnumericalin
digitalsystems.
Examplesarecalculatorsandwatches.
a
b
c
d
e
g
f
Design Example
Fig.2.19: 7-Segment Display

LECTURE 13:-CODE CONVERTER Design Example
10
0
Digital
Display
INPUT OUTPUT
ABC D abcde fg
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 0 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 0 0 1 1
Truth Table of BCD to 7-seg decoder
Table 2.1 BCD to 7-Seg

LECTURE 13:-CODE CONVERTER
10
1
Draw the K-map for the output column of the truth table.
K-map for output ‘a’
a = A + B’D’ + BD + CD
Similarly K-map for output ‘b’, ‘c’, ‘d’, ‘e’, ‘f’ and ‘g’ can be
drawn and you can write the output in the form of input.
K-map of BCD to 7-seg decoder
Design Example
Fig.2.20: 4-Variable K-maps

B’
D’
D
B
C
D
A
a
LECTURE 13:-CODE CONVERTER
10
2
After getting the equations for ‘b’, ‘c’, ‘d’, ‘e’, ‘f’ and ‘g’ NAND
gate implementation can be done. As shown below for ‘a’-
a = A + B’D’ + BD + CD
Design Example
Circuit Design of BCD to 7-seg decoder
Fig.2.21: Circuit Design

LECTURE 14:-CODE CONVERTER Bin to Gray Code Converter
103
Sl
No
Input Output
Sl
No
Input Output
B
3
B
2
B
1
B
0
G
3
G
2
G
1
G
0
B
3
B
2
B
1
B
0
G
3
G
2
G
1
G
0
000000000810001100
100010001910011101
2001000111010101111
3001100101110111110
4010001101211001010
5010101111311011011
6011001011411101001
7011101001511111000
Truth Table
Table 2.2 Binary to Gray

LECTURE 14:-CODE CONVERTER Bin to Gray Code Converter
104
•(10110)
B
    
    
    
•(1 1 1 0 1)
G
•MSBinBinisequaltoMSBinGray
•The2-ndbitoftheGraycodeis1ifthe1-standthe2-nd
bitofthecorrespondingbinarycodearedifferentand0if
theyarethesame(EX-ORingoperation).
•TheN-thbitoftheGraycodeis‘1’ifthe(N-1)-thandthe
N-thbitofthecorrespondingbinarycodearedifferent
and‘0’iftheyarethesame.
Explanation of Truth table
Fig.2.22: Binary to Gray conversion method

LECTURE 14:-CODE CONVERTER Bin to Gray Code Circuit
105
B3
B2
B1
B0
G3
G2
G1
G0
Circuit Implementation
As per the relation of binary to gray circuit is implemented
• MSB of gray is same as MSB of binary (i.e. G3=B3)
• G2 = B3 Ex-OR B2
• G1 = B2 Ex-OR B1
• G0 = B1 Ex-OR B0
Fig.2.23: Binary to Gray Conversion Circuit

LECTURE 15:-
10
6
•Modern digital Electronics-R. P. Jain, McGraw Hill.
•Digital Integrated Electronics-Herbert Taub, McGraw Hill.
•Digital Logic and Computer Design-Morris Mano(PHI).
•Digital Integrated Electronics-Herbert Taub, McGraw Hill.
•Digital Electronics Logic and System –James Bingnelland Robert
Donovan, CengageLearning
•Digital Circuits & Systems by K.R.Venugopal& K. Shaila
•http://npteldownloads.iitm.ac.in/downloads_mp4/117106086/lec01.mp4
•http://www.digital.iitkgp.ernet.in/dec/index.php
•http://vlab.co.in/ba_nptel_labs.php?id=1
Chapter 2 References

LECTURE 15:-
107
Summary
1. 2-types for form of function available in digital electronics:
i)Sum of Product (POS) ii) Product of Sum (POS)
2. SOP can be converted into SSOP by applying Boolean laws and
make available all the literals either in true or complemented.
3. Mintermis a product term having all the literals.
4. MAXTERM is a sum term having all the literals.
5. Universal gate using can implement any Boolean function or any
gate NAND and NOR gates are the examples of Universal gate.
6. K-map required to minimize any Boolean expression, types are:
i)2-variable k-map ii) 3-variable k-map iii) 4-variable k-map.
7. K-map is the method to reduce any Boolean expression easily.

LECTURE 15:-
108
•Express the following equation in std. sop & pos form.
F(A,B,C,D) = (A + BC).(B + CD).
•What is the difference between Canonical form & standard form?
•Express Boolean function F = A+BC in a sum of minterm(canonical
form).
•Define mintermand MAXTERM.
•What is sum of product and product of sum.
•Explain binary to gray conversion with ckt. Diagram & example.
•How you convert a gray no. to binary no.?
•Reduce the function using K-map.
a) F(A,B,C,D) = ABC + BC’ + A’CD
b) F(A,B,C,D) = AB + B’C + ABCD
c) F(A,B,C,D) = (A + BCD).(ABC + BC’D).(A’CD + C’D’)
d) F(A,B,C,D) = (A + ABCD’).(ABC’ + CD).
Chapter 2 Question Bank

109
“DIGITALELECTRONICSAND
FUNDAMENTALOFMICROPROCESSOR”
CHAPTER–3
“COMBINATIONALCIRCUITS”

CHAPTER 3:-Combinational Circuits
Introduction to Combinational circuit.1
Multiplexer and Demultiplexer2
Encoder and Decoder3
Half and Full Adder Subtracture
4
110
ALU IC74181
5
Topic 1:
Topic 2:
Topic 3:
Topic 4:
Topic 5:

CHAPTER-3 SPECIFIC OBJECTIVE / COURSE OUTCOME
Understand and design combinational circuit.1
Design function using multiplexer and demultiplexer
2
111
The student will be able to:
Discuss concept of Encoder and Decoder.3
Design Arithmetic circuit.4
Understand concept of ALU5

LECTURE 16:- Combinational Circuit
112
112
Combinationalcircuitisacircuitinwhichwecombinethe
differentgatesinthecircuit.Someofthecharacteristicsof
combinationalcircuitsarefollowing−
•Theoutputofcombinationalcircuitatanyinstantoftime,
dependsonlyonthelevelspresentatinputterminals.
•Thecombinationalcircuitdonotuseanymemory.The
previousstateofinputdoesnothaveanyeffectonthepresent
stateofthecircuit.
•Acombinationalcircuitcanhaveannnumberofinputsandm
numberofoutputs.
Examples:-
Multiplexer,
Demultiplexer,
Encoder,
Decoder,etc.
Introduction
Fig.3.1: Combinational Circuit

LECTURE 16:- Combinational Circuit
113
113
•Ithasmanyinput&1output,henceitisalsocalledas
manytoone.
•Itcomesundercombinationalcircuit.
•No.ofinputlines=2^(No.ofSelectlines).
•ItisaSelectorwhichcanselectanyoneofmanyinput
linetotheoutputlineaspercombinationoftheselect
line.
•AnykindofBooleanfunctioncanbedesignusingmux.
Introduction of Multiplexer

LECTURE 16:-
114
114
4x1
Mux
I0
I1
I2
I3
S1S0
Youtput
(Select line)
2
n
inputs
(n= no. of
select line)
Enable
(G)
4x1 Multiplexer
Combinational Circuit
Fig.3.2: 4x1 Mux

LECTURE 16:-
115
115
Internal Circuit of 4x1 Multiplexer
Combinational Circuit
Y =G. I0. S’1. S’0 +G. I1. S’1. S0 +G. I2. S1. S’0 + G. I3. S1. S0
Fig.3.3: Internal Circuit of 4x1 Mux

LECTURE 16:-
116
116
Characteristics Table of 4x1Multiplexer
•If the MUX is enabled:
The equivalent expression is given below-
Y =G. I0. S’1. S’0 +G. I1. S’1. S0 +G. I2. S1. S’0 + G. I3. S1. S0
SelectLines O/P Line
G S1 S0 Y
1 0 0 I0
1 0 1 I1
1 1 0 I2
1 1 1 I3
Combinational Circuit
Table 3.1: 4x1 Mux

LECTURE 17:- Examples
117
117
Implementation of F(A,B,C,D)=∑m(1,3,5,7,8,10,12,13,14)
By using a 16-to-1 multiplexer: + d(4,6,15)
16x1
Mux
F
I00
0
1
0
NOTE: 4,6 and 15 MAY BE
CONNECTED to either 0 or 1
I1
I2
I3
I4
I5
I8
I6
I9
I7
I11
I10
I13
I12
I14
I15
0
0
0
0
1
1
1
1
1
1
1
1
S
3S
2S
1S
0
Fig.3.4: 4x1 Mux

LECTURE 17:- Examples
118
118
In this example to design a 3 variable logical function,
we try to use a 4x1 MUX rather than a 8x1 MUX.
F(x, y, z)=∑ m(1, 2, 4, 7)
Design Example of MUX
Fig.3.5: 4x1 Mux

LECTURE 17:- Examples
119
119
In a canonic form:
F = x’.y’.z+ x’.y.z’+x.y’.z’ +x.y.z …… (1)
One Possible Solution:
Assume that x = S1 , y =S0.
If F is to be obtained from the output of a 4-to-1 MUX,
F =S’1. S’0. I0 + S’1. S0. I1 +S1. S’0. I2 + S1. S0. I3 ….(2)
From (1) and (2),
I0= I3=Z I1= I2=Z’
Design Example of MUX

LECTURE 17:- Examples
120
120
Z
XY
Design Example of MUX
Fig.3.6: 4x1 Mux Implementation

LECTURE 18:-
Introduction to Demultiplexer
121
121
•Ademultiplexertransfersitsinputtooneoftheoutputs
dependingonthebinarycodeprovidedattheselect
inputs.
•Ademultiplexerperformsreverseoperationofa
multiplexerthatittakeasingleinput&distributesitover
severaloutput(atatimetoanyoneofoutput)
1x4
Demux
I
S1S0
Y0
Y1
Y2
Y3
Example:1x4Demuxhavingone
inputline,twoselectlineand
Fouroutputlines.
No.ofoutputlines=2^(No.of
selectlines)
Combinational Circuit
Fig.3.7: 1x4 De Mux

LECTURE 18:-
122
122
Characteristic table of the 1x4 DMUX with ACTIVE
HIGH Outputs:
Introduction to Demultiplexer
Combinational Circuit
Table 3.2: 1x4 De Mux

LECTURE 18:-
123
123
Characteristic Table of a1x4 DMUX,with ACTIVE LOW
Outputs:
Introduction to Demultiplexer
Combinational Circuit
Table 3.3: 1x4 De Mux

LECTURE 19:-
Introduction to Encoder
124
124
•Anencoderproducesadigitalcodewhichdependson
whichoneofitsinputisactivated.Encoderisusedto
generateacodedoutputfromtheactiveinputline.
I
0
Encoder
I
1
I
2
O
0
O
1
O
N-1
I
M-1
Input lines = 2^(Output lines)
M = 2^N
Combinational Circuit
Fig.3.8: Encoder

LECTURE 19:-
4x2 Encoder
125
125
A
Encoder
B
C
Y
X
D
Inputs Outputs
ABCD Y X
1000 0 0
0100 0 1
0010 1 0
0001 1 1
•4x2Encoderhavingfourinputlinesandtwooutputlines.
•Itisconsideredthatatatimeonlyoneinputishighand
thehighinputisdisplayattheoutput.
Truth Table3.4: 4x2 Encoder
Combinational Circuit
Fig.3.9: 4x2 Encoder

LECTURE 20:-
Decimal to BCD Encoder
126
126
S
0
S
1
S
9
B
0
B
3
Thistypeofencoderhaving10inputlinesand4outputlines.
Atatimeanyoneinputlineishigh,andthesameisdisplay
attheoutput.HenceitisnothingbutadecimaltoBCDcode
converter.
Example:OutofS0-S9input
linesifS1isonlyhightheoutput
willbeinBCDas“0001”.
Sameisshowninnextslidein
truthtableformat.
Combinational Circuit
Fig.3.10: Decimal to BCD Encoder

LECTURE 20:-
127
127
Input Output
S
0S
1S
2S
3S
4S
5S
6S
7S
8S
9B
0B
1B
2B
3
10000000000000
01000000000001
00100000000010
00010000000011
00001000000100
00000100000101
00000010000110
00000001000111
00000000101000
00000000011001
Decimal to BCD Encoder
Truth Table 3.5 Dec to BCD Encoder
Truthtableshows10inputlinesand4outputlines.Asper
thecombinationofinputlinesoutputisgenerated.
Combinational Circuit

LECTURE 20:-
128
128
Priority Encoder
Whiledesigningtheencoderthedisadvantagesofstandard
digitalencodersisthattheycangeneratethewrongoutput
codewhenthereismorethanoneinputpresentatlogic
level“1”.Forexample,ifwemakeinputsD
1andD
2HIGHat
logic“1”bothatthesametime,theresultingoutputis
neitherat“01”orat“10”butwillbeat“11”whichisan
outputbinarynumberthatisdifferenttotheactualinput
present.Also,anoutputcodeofalllogic“0”scanbe
generatedwhenallofitsinputsareat“0”ORwheninputD
0
isequaltoone.
Toovercomethisdrawbackitisbettertoassignthepriority.
AndinabovecaseifD2hasassignhigherprioritythanD1
thenoutputwillbe“10”only.Thisconceptisknownasa
PriorityEncoder.
Combinational Circuit
Reference :-http://www.electronics-tutorials.ws/combination/comb_4.html

LECTURE 20:-
129
129
8-to-3 Bit Priority Encoder
Combinational Circuit
Reference :-http://www.electronics-tutorials.ws/combination/comb_4.html
PriorityencodersareavailableinstandardICformandthe
TTL74LS148isan8-to-3bitpriorityencoderwhichhas
eightactiveLOW(logic“0”)inputsandprovidesa3-bitcode
ofthehighestrankedinputatitsoutput.Priorityencoders
Fig.3.11: Block Diagram
Truth Table3.6: 8x3 Encoder

LECTURE 20:-
130
130
8-to-3 Bit Priority Encoder
outputthehighestorderinputfirstforexample,ifinputlines
“D2“,“D3”and“D5”areappliedsimultaneouslytheoutput
codewouldbeforinput“D5”(“101”)asthishasthehighest
orderoutofthe3inputs.Onceinput“D5”hadbeen
removedthenexthighestoutputcodewouldbeforinput
“D3”(“011”),andsoon.
Combinational Circuit
Reference :-http://www.electronics-tutorials.ws/combination/comb_4.html
Fig. 3.12: Internal Circuit

LECTURE 21:-
131
131
Introduction to Decoder
•Decoderactivatesonlyoneofitsoutputsdependingon
thebinarycodeprovidedasinput.
•Decoderisalogiccircuitthatacceptsetofinputswhich
representsbinarynumberandactivatesonlytheoutput
thatcorrespondstotheinputnumber.
I
N-1
O
0
Decoder
O
1
O
2
O
M-1
I
0
I
1
Outputlines<=2^(inputlines)
M<=2^N
Combinational Circuit
Fig. 3.13: Decoder

LECTURE 21:-
132
132
2x4 Decoder
A
B
C
X
Y
D
Inputs Outputs
XYA B C D
001 0 0 0
010 1 0 0
100 0 1 0
110 0 0 1
•2x4Decoderhavingtwoinputlinesandfouroutputlines.
•2inputgives4possibilitiesforeachinputcombination
thecorrespondingoutputwillbehighremainingallare
low.Detailshownintruthtableasbelow-
TruthTable3.7:2x4Decoder
Combinational Circuit
Fig. 3.14: 2x4 Decoder

LECTURE 21:-
133
133
BCD to Decimal Decoder
B
0
B
1
B
2
S
0
S
9
B
3
-
-
-
-
-
-
BCDtoDecimalDecoderrequired4x16decoderhaving4
inputlinesand16outputlinesoutof16only10linesare
used(i.e.S0–S9)andremainingoutputlinesarekept
Inactive.ForequivalentinBCDcombinationthe
correspondingoutputwillhighremainingallarelow.
Example:Ifinputas“0111”
thenS7outputlinewillbe
highremainingallare
low(Foractivehighdecoder).
Sameisexplaininnextslide
truthtable.
Combinational Circuit
Fig. 3.15: BCD to Decimal Decoder

LECTURE 21:-
134
134
BCD to Decimal Decoder
Truthtablehavingfourinputlinesandtenoutputlines.For
eachcombinationsofBCDatatimeonlyoneoutputishigh
remainingallarelow.
Input Output
B
0B
1B
2B
3S
0S
1S
2S
3S
4S
5S
6S
7S
8S
9
00001000000000
00010100000000
00100010000000
00110001000000
01001000100000
01010000010000
01100000001000
01110000000100
10000000000010
10010000000001
Truth Table 3.8: BCD-Decimal Decoder
Combinational Circuit

LECTURE 22:- Arithmetic Circuit
•Itisaarithmeticcircuitwhichperformsarithmeticoperations
•Addingtwosingle-bitbinarynumbersi.e.‘X’and‘Y’
•Producesasum‘S’bitandacarryout‘C’bit
135
135
Half Adder
X
Y
S
C
Fig. 3.16 :Symbol of Half Adder
X
Y
S
C
Fig. 3.17 :Circuit of Half Adder
S= X X-OR Y
C=X.Y
Half Adder

LECTURE 22:-
•Full adder takes a three-bits input
•Adding two single-bit binary values X, Y with a carry input Z
•Produces a sum bit ‘S’ and a carry out ‘Co’ bit.
Truth Table3.9 : Full Adder
136
136
XYZ S Co
0000 0
0011 0
0101 0
0110 1
1001 0
1010 1
1100 1
1111 1
Full Adder
X
Y
S
Co
Fig.3.18 :Symbol of Full Adder
Z
Full Adder
Arithmetic Circuit

LECTURE 22:-
137
137
S (X,Y,Z) = (1,2,4,7) Co (X,Y,Z) = (3,5,6,7)
K-map for S K-map for Co
S = X'Y'Z + XY'Z' + X'YZ‘ Co = XY + XZ + YZ
S = X Y Z
K-map of Full Adder
Arithmetic Circuit
Fig.3.19:Sum of Full Adder Fig.3.20:Carry of Full Adder

LECTURE 22:-
138
138
Co=XY+XZ +YZ
S = X Y Z
X
Y
Z
Co
Circuit of Full Adder
Arithmetic Circuit
Fig.3.21:Circuit of Full Adder

LECTURE 23:-
139
139
•Subtractingtwosingle-bitbinaryvalues‘X’,‘Y’.
•ProducesDifference‘D’bitandaBorrowout‘B’bit.
Half
Subtractor
X
Y
D
B
Half Subtractor
Arithmetic Circuit
Fig.3.22: Symbol of Half Subtractor

LECTURE 23:-
140
140
•Fullsubtractortakesathree-bitsinput.
•Subtractingtwosingle-bitbinaryvaluesX,Ywithacarry
inputbitZ.
•ProducesadifferencebitDandaBorrowoutBbit.
Truth Table 3.10 Full Subtractor
X Y Z D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Full Subtractor
Arithmetic Circuit

LECTURE 23:-
141
141
D (X,Y,Z) = (1,2,4,7) B (X,Y,Z) = (1,2,3,7)
K-map for D K-map for B
D = X'Y'Z + XY'Z' + X'YZ‘ B = X’Y + X’Z + YZ
D = X Y Z
K-map of Full Subtractor
Arithmetic Circuit
Fig.3.23: Sum of full Subtractor
Fig.3.24: Borrow of full Subtractor

LECTURE 23:-
142
142
B = X’Y + X’Z + YZ
D = X Y Z
X
Y
Z
B
Circuit of Full Subtractor
Arithmetic Circuit
Fig.3.25: Circuit of full Subtractor

LECTURE 24:-
143
143
Toreducethecomputationtime,therearefasterwaysto
addtwobinarynumbersbyusingcarrylookahead
adders.TheyworkbycreatingtwosignalsPandG
knowntobeCarryPropagatorandCarryGenerator.The
carrypropagatorispropagatedtothenextlevel
whereasthecarrygeneratorisusedtogeneratethe
outputcarry,regardlessofinputcarry.Theblockdiagram
ofa4-bitCarryLookaheadAdderisshownhereinnext
slide-
Thenumberofgatelevelsforthecarrypropagationcan
befoundfromthecircuitoffulladder.Thesignalfrom
inputcarryCintooutputcarryCoutrequiresanANDgate
andanORgate,whichconstitutestwogatelevels.
Carry Look Ahead Adder
Arithmetic Circuit
Reference :-http://iitkgp.vlab.co.in/?sub=38&brch=120&sim=480&cnt=656

LECTURE 24:-
144
144
Soiftherearefourfulladdersintheparalleladder,the
outputcarryC
5wouldhave2X4=8gatelevelsfromC
1to
C
5.Forann-bitparalleladderr,thereare2ngatelevelsto
propagatethrough.
Carry Look Ahead Adder
Arithmetic Circuit
Reference :-http://iitkgp.vlab.co.in/?sub=38&brch=120&sim=480&cnt=656
Fig.3.26: Carry Look Ahead Adder

LECTURE 24:- IC 74181
145
145
•It is a 24 pin IC having 4 select line and 1 mode line.
•If mode = 1 it can do logical operation & if 0 can do
arithmetic operations.
24
12
Vcc
A0-A3
B0-B3
C’n
Carry in
S0-S3
Select i/p
Mode control
(M)
F0-F3
C’n+4 Carry
o/p
A = B
CG
CP
ALU
74181
ALU Pin Block Diagram
Fig.3.27: ALU

LECTURE 24:- IC 74181
146
Reference :-digitales1uan.blogspot.com
Table.3.11: Functional Table of ALU

LECTURE 25:-
14
7
•Modern digital Electronics-R. P. Jain, McGraw Hill.
•Digital Integrated Electronics-Herbert Taub, McGraw Hill.
•Digital Logic and Computer Design-Morris Mano(PHI).
•Digital Integrated Electronics-Herbert Taub, McGraw Hill.
•Digital Electronics Logic and System –James Bingnelland Robert
Donovan, CengageLearning
•Digital Circuits & Systems by K.R.Venugopal& K. Shaila
•http://npteldownloads.iitm.ac.in/downloads_mp4/117106086/lec01.mp4
•http://www.digital.iitkgp.ernet.in/dec/index.php
•http://vlab.co.in/ba_nptel_labs.php?id=1
•digitales1uan.blogspot.com
•http://iitkgp.vlab.co.in/?sub=38&brch=120&sim=480&cnt=656
•http://www.electronics-tutorials.ws/combination/comb_4.html
Chapter 3 References

LECTURE 25:-
148
Summary
1. Combinational circuits studied in this chapter are-
a)Multiplexer -Having many input lines and one output line along
with select lines.
b)Demultiplexer-Having one input line and many output lines
along with select lines.
c)Encoder -Having n output lines and 2^n input lines.
d)Decoder -Having n input lines and 2^n output lines.
2. Adders are of two types:
i) Half Adder ii) Full Adder
3. Arithmetic Logic Unit (ALU) is a 24 pin IC 74181 having four select
lines and one mode (Decide types of operations)
If Mode = ‘1’ : Performs Logical operations
If Mode = ‘0’ : Performs Arithmetic operations

LECTURE 25:-
149
•What is half –adder? Write it’s truth table & develop it’s logic circuit.
•What is full adder ? How a full adder is built?
•What is full Subtractor ? Design a full Subtractor ckt.
•What is BCD adder? Realize BCD adder using full adder & logic gates.
•Draw the functional layout of arithmetic logic unit (ALU) & explain the
various algebraic & logical function that can be performed.
•What is multiplexer ? Explain 16:1 Muxin details.
•Implement the expression using a multiplexer.
F(A,B,C,D) = ∑ (1,2,4,5,12,14,15)
•Realize the function F(A,B,C,D) = ∑ (1,3,4,5,7,11,13,14,15) by using 8:1
Mux.
•Design 32:1 Muxby using two 16:1 multiplexer & one OR gate.
•Realize the function F
1(A,B,C,D) = ∑ (0,1,6,9,11,15) & F
2= ∑ (3,5,13,14)
by using a suitable Demux.
•Implement following function by using suitable decoder.
F
1= ∑ (0,1,2), F
2= ∑ (2,4,9,10) & F
3= ∑ (3,5,12,15).
•Design 8:3 parity encoder with D
7as the highest parity.
Chapter 3 Question Bank

150
“DIGITALELECTRONICSAND
FUNDAMENTALOFMICROPROCESSOR”
CHAPTER–4
“FLIP-FLOP”

CHAPTER 4:-Flip-Flop
Introduction to SR Latch and Flip-flop 1
D, JK, T flip-flops and triggering in flip-flop2
Master slave concept, Asynchronous input3
Conversion of flip flops
4
151
Counters and Registers
5
Topic 1:
Topic 2:
Topic 3:
Topic 4:
Topic 5:

CHAPTER-4 SPECIFIC OBJECTIVE / COURSE OUTCOME
Know Flip-flop as a one bit memory cell1
Distinguish between latch and flip-flop
2
152
The student will be able to:
Understand concept of Preset and Clear (Asynchronous input)3
Explain master slave concept also do the conversion of flip-flop4
Design counters and registers5

LECTURE 26:-FLIP-FLOP Sequential Circuit
153
153
Thecombinationalcircuitdoesnotuseanymemory.Hence
thepreviousstateofinputdoesnothaveanyeffecton
thepresentstateofthecircuit.Butsequentialcircuithas
memorysooutputcanvarybasedoninput.Thistypeof
circuitsusespreviousinput,output,clockandamemory
element.
Introduction to Sequential Circuit
Reference :-http://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm
Fig.4.1: Sequential Circuit

LECTURE 26:-FLIP-FLOP Sequential Circuit
154
154
•Sequentialcircuithavingoutputwhichisdependsupon
presentstateinputaswellasthecontentofstoredelement.
•Latch,Flip-flop,registersandCountersaretheexamplesof
Sequentialcircuit.
•ALatchcircuithastwooutputs,‘Q’and‘Q’’boththeoutputs
arecomplementofeachotherifQ=‘1’theQ’=‘0’andvice-
versa.
•WhentheLatchoutputi.e.Q=‘0’thenthelatchisinReset
stateandwhenQ=‘1’thenthelatchisinSetstate.
Introduction to Latch

LECTURE 26:-FLIP-FLOP Sequential Circuit
155
155
Difference between Latch & Flip-Flop
Flip-flop Latch
A flip-flop samples the inputs
only at a clock event (rising
edge, etc.)
A Latch samples the inputs
continuously whenever it is
enabled, that is, only when the
enable signal is on. (or
otherwise, it would be a wire,
not a latch).
Flip-Flop are edge sensitive.Latches are level sensitive.
Flipflopis sensitive to signal
change and not on level. They
can transfer data only at the
single instant and data cannot
be changed until next signal
change.
Latch is sensitive to duration of
pulse and can send or receive
the data when the switch is on.
Reference :-http://www.techonicals.com/2013/01/difference-between-latch-and-flip-flop.html

LECTURE 26:-FLIP-FLOP Sequential Circuit
156
156
Difference between Latch & Flip-Flop
Flip-flop Latch
A flip-flop continuously checks
its inputs and correspondingly
changes its output only at
times determined by clocking
signal.
Latch is a device which
continuously checks all its
input and correspondingly
changes its output,
independent of the time
determined by clocking signal.
It work’s on the basis of clock
pulses.
It is based on enable function
input
It is a edge trigerred , it mean
that the output and the next
state input changes when
there is a change in clock
pulse whether it may a +ve or -
ve clock pulse.
It is a level trigerred, it mean
that the output of present state
and input of the next state
depends on the level that is
binary input 1 or 0.
Reference :-http://www.techonicals.com/2013/01/difference-between-latch-and-flip-flop.html

157
157
LECTURE 27:-FLIP-FLOP
Triggering
•Thestateofaflip-flopischangedbyamomentarychange
intheinputsignal.Thischangeiscalledatrigger.
•TheClockedflip-flopsaretriggeredbypulses.
Therearetwotypesoftriggering–
1)PositiveEdgedTrigger
2)NegativeEdgedTrigger
Sequential Circuit
Fig.4.2: Triggering of Clock

LECTURE 27:-FLIP-FLOP
SR Latch
158
158
•SRlatchbasedonNORgates.
•TheSinputsettheQoutputto‘1’whileRresetitto‘0’.
•WhenR=S=‘0’thentheoutputkeepsthepreviousvalue.
•WhenR=‘1’;S=‘0’thentheflip-flopissaidtobeinReset
state(i.e.outputQ=‘0’).
•WhenR=‘0’;S=‘1’thentheflip-flopissaidtobeinSet
state(i.e.outputQ=‘1’).
•WhenR=S=1thenQ=Q’=‘0’,andthelatchmaygotoan
unpredictablenextstate.
Fig.4.3 :SR Latch using NOR gate
Truth Table 4.1
Sequential Circuit

LECTURE 27:-FLIP-FLOP
D Flip-flop
159
159
•Whenclockisapplytothelatchthenitiscalledasflip-
flop.
•Cisanenableinput:
–WhenC=1thentheoutputfollowstheinputDand
thelatchissaidtobeopen.
–WhenC=0thentheoutputretainsitslastvalueand
thelatchissaidtobeclosed.
Fig.4.4 :D flip-flop using NAND gate
Truth Table 4.2
Sequential Circuit

160
160
LECTURE 28:-FLIP-FLOP
T Flip-flop
•TheTflip-flopisasingleinputversionoftheJKflip-flop.
AsshowninFigurebelow.
•TheTflip-flopisobtainedfromtheJKtypeifbothinputs
aretiedtogether.TheoutputoftheTflip-flop"toggles"
witheachclockpulse
Fig.4.5 :T flip-flop
Truth Table 4.3
Sequential Circuit

161
161
LECTURE 28:-FLIP-FLOP
JK Flip-flop
•AJKflip-flopisarefinementoftheSRflip-flopinthat
theindeterminatestateoftheSRtypeisdefinedinthe
JKtype(i.e.InSRforinput‘1’,‘1’outputisinvalid.)
•WhenJ=K=1thenitwillcomplementitsoutput.
•JKflip-flopovercomedrawbackofSRflip-flop.
Fig.4.6 :JK flip-flop
Truth Table 4.4
Sequential Circuit

162
162
LECTURE 28:-FLIP-FLOP
JK Flip-flop
•JKflip-flopovercomedrawbackofSRflip-flopthatthe
forbiddenstateinSRflip-flopforbothinput“11”willgive
asatoggleinJKflip-flop.
•Asthereisthefeedbackfromoutputtoinputandalso
becauseofthepropagationdelayofthegateswhichis
morethantheclockpulseappliedtotheflip-flop.Hence
theoutputisnotstableforthesameclockasthereis
feedback.Thereforeduringtheclocktheoutputis
togglingwhichisknownastheracearoundcondition.
•RacearoundconditioninJKflip-flopisovercomeby
usingMasterSlaveconcept.
Sequential Circuit

163
163
LECTURE 28:-FLIP-FLOP
Master Slave Flip-flop
•Amaster-slaveflip-flopisconstructedfromtwoseparate
flip-flops.Slaveisdrivenbymaster’soutputasainputtoit.
•ThemasterisenabledonthepositivehalfofclockCPand
slaveisdisabled,whilefornegativehalfofclockmasteris
disabledandslaveisenabled.
•Henceforeachhalfofclockonlymasterorslaveisenable
andRacearoundconditioncanberemoved.
Sequential Circuit
Fig.4.7 :Master Slave flip-flop

164
164
LECTURE 28:-FLIP-FLOP
Master Slave JK Flip-flop
•Asshowninfiguredirectclockisconnectedtothemaster
andclockthroughNOTgateisappliedtoslave.
•Whenclockpulsecomesforitspositivehalfonlymasteris
onandslaveisoff,foritsnegativehalfonlyslaveisonand
masterisoff.
Sequential Circuit
Fig.4.8 : Master Slave JK flip-flop

165
165
LECTURE 29:-FLIP-FLOP Asynchronous Input
•ThePreset(Pr)andClear(Cr)arethedirecti/ptothe
flip-flop.
•Irrespectiveoftheclockflip-flopcanbesetorresetat
anytime.
•When Pr=‘0’ & Cr=‘1’
Flip-flop will set to ‘1’
•When Pr=‘1’ & Cr=‘0’
Flip-flop will reset to ‘0’
Pr
Cr
S
R
Q
Q’
SR
Flip-flop
Clk
Fig.4.9 :SR flip-flop with asynchronous input
Preset and Clear input of Flip-flop

166
166
LECTURE 29:-FLIP-FLOP Excitation table
Status of OutputSR FFJK FFD FFT FF
Present
State
(Q
n)
Next
State
(Q
n+1)
SRJK D T
0 0 0X0X 0 0
0 1 011X 1 1
1 0 10X1 0 1
1 1 X0X0 1 0
•Excitationtableisdrawnforthecharacteristicstableof
theflip-flop.
•Statusoftheoutputoftheflip-flopisconsideredand
accordingtothatinputoftheflip-flopisevaluated.As
shownbelow-
Excitation table of all Flip-flop
Table 4.5 :Excitation Table of JK flip-flop

167
167
LECTURE 29:-FLIP-FLOP
Edged Triggering
•Outputwillgetsaffectedonlyontheedgeoftheclock
eitheronrisingorfalling.
•Exampleshownbelow-
Triggering
Reference :-http://www.pa.msu.edu/courses/2012fall/PHY440/Flip%20flops.pdf
Fig.4.10 :Edged Triggering

168
168
LECTURE 29:-FLIP-FLOP
Level Triggering
•Outputwillgetsaffectedwhentheclockishigh.
•Exampleshownbelow-
Triggering
Reference :-http://www.pa.msu.edu/courses/2012fall/PHY440/Flip%20flops.pdf
Fig.4.11 :Level Triggering

169
169
LECTURE 30:-FLIP-FLOP Conversion
•Forconvertingonetypeofflip-flopintoanother,excitation
tableplaysanimportantrole.
•Excitationtablecanbedefinedasatablewhichgivesthe
statusofinputtotheflip-flopfromtheconditionofthe
output(i.e.presentandnextstate).
•Generalizeblockofflip-flopconversionisasfollow-
Conversion of SR-JK Flip-flop
Given
Flip-flop
Logic
Clock
Input1
Input2
Q
Q’
Fig.4.12 :Required flip-flop

170
170
LECTURE 30:-FLIP-FLOP Conversion
For JK FF For SR FF
Present
State Q
n
Next
State
Q
n+1
JKPresent
State Q
n
Next
State
Q
n+1
SR
0 0 0X 0 00X
0 1 1X 0 110
1 0X1 1 001
1 1X0 1 1X0
•DrawexcitationtableforJKthenSRflip-flopasshown
below-
•Considercolumnno.3,4,5astheinputcolumnand7,8as
theoutputcolumnforthenextslidetable.
Column no. 1 2 3 4 5 6 7 8
Table 4.6 :Excitation table
Conversion of SR-JK Flip-flop

171
171
LECTURE 30:-FLIP-FLOP
Input Output
In
Dec
JKPresent
State Q
n
SR
0,20X 0 0X
4,61X 0 10
3,7X1 1 01
1,5X0 1 X0
Intablebelowinputcolumnhavedon’tcarewhich
mustbereplacedwith‘0’and‘1’(i.e.forrow1-J=‘0’and
K=‘x’consider‘x’as‘0’and‘1’asforJK=“0x”-JK=“00”
andJK=“01”.Similarlyasshownintablebelow-
Row
1
2
3
4
Conversion
Conversion of SR-JK Flip-flop
Table 4.7

172
172
LECTURE 30:-FLIP-FLOP
Now draw the K-map for representing the output in the form
of input.
K-map for S K-map for R
S = JQ’ R = KQ
Conversion
Conversion of SR-JK Flip-flop
Fig.4.13 :K-map for S Fig.4.14 :K-map for R

173
173
LECTURE 30:-FLIP-FLOP Conversion
Conversion of SR-JK Flip-flop
Fig.4.15 :Circuit Implementation

LECTURE31:-
174
174
•Countercanbedefinedasaresisterthatgoesthrough
theprescribedsequenceofstatesupontheapplication
ofinputpulse.
•Countercanbeclassifiedintotwobroadcategories
accordingtothewaytheyareclocked:
Asynchronous(Ripple)Counter-Thefirstflip-flopis
clockedbytheexternalclockpulse,andtheneach
successiveflip-flopisclockedbytheQorQ'outputof
thepreviousflip-flop.
SynchronousCounter-Allmemoryelements(Flip-flops)
aresimultaneouslytriggeredbythesameclock.
Counter
Introduction

LECTURE 31:- Ripple Counter
175
175
Asynchronous (Ripple) Counter
•Circuitshowstwoflipflopsfirstflipflophavinginput
externalclockandthesecondflipflophavingtheclock
asaoutputofthefirstflipflop.
•BothJKflipflopsareusedincomplementedmode(i.e.
JKinputareshortcircuitedandconnectedtologic‘1’.)
•Belowcircuitisof2-bitupcounterasshowninwave
diagramfor1
st
clockinputoutputis“00”,for2
nd
itis“01”
for3
rd
itis“10”andfor4
th
itis“11”.
Fig. 4.16 :Ripple Counter Fig. 4.17 :Wave Diagram

LECTURE 32:-
176
176
•Asperthedefinitionofsynchronouscountertheckt.
shownbelow–SynchronousUp-CounterwithT-FF.
•Inthisalltheflipflopsincounterarehavingsimultaneous
clockinput.
•ModulusofCounter(MOD):-Modulusmeansthetotal
numberofcounts.
Synchronous Counter
Example of SynchronousCounter
Fig. 4.18 :Synchronous Counter

LECTURE 32:-
177
177
•Thecounterwhichgoesthrough10differentstatesupon
theapplicationofinputclockpulseisDecadeCounter.
•Thistypeofcounterwillcountfrom0(0000)to9(1001)
andwhen10(1010)arrivesthecounterwillresetand
againitwillcountfrom0(0000).
•Acommonmodulusforcounterswithtruncated
sequencesisten.Acounterwithtenstatesinits
sequenceiscalledadecadecounter.
•Sincethemaximumno.ofbitsrequiredtorepresentthe
binaryno.from0(0000)to9(1001)isfour.Sothere
mustbeminimumfourno.offlip-flopswillrequiredto
designthedecadecounter.
Decade Counter
Decade or MOD-10 Counter

178
LECTURE 32:-
HencethecircuitdiagramfortheDecadeCounteris
shownbelow-
HereQ3isMSBandQ0isLSB.Whenboth(i.e.
Q3andQ0are‘1’)o/poftheNANDgateis‘0’whichwill
clearthecounter.
Decade Counter
Fig. 4.19 :Decade/MOD 10 Counter
Design of Decade or MOD-10 Counter

LECTURE 32:-
179
179
The sequence of the decade counter is shown in the
table below:
Decade Counter
Truth Table of Decade or MOD-10 Counter
Table 4.8 Decade Counter

180
LECTURE 33:- Ring Counter
•Itisacascadeconnectionofflipflopsinwhichoutputof
1
st
flipflopisconnectedinputtothe2
nd
andsoon,output
oflastflipflopisconnectedinputtothe1
st
inaring
mannerhencenamedRingCounter.
•SimultaneousclockisattachedbyclearinputFF0isset
andFF1,FF2&FF3reset,aftereachclockpulse‘1’is
shiftedthrougheachflipflopinthecounter.
Fig.4.20 :4 -Bit Ring Counter
4-Bit Ring Counter

181
LECTURE 33:- Ring Counter
•Truthtableshowsfor1
st
clockFF0isset(i.e.Q0=‘1’)
whileremainingallflipflopsarereset(i.e.Q1=‘0’,Q2=‘0’,
Q3=‘0’)alloutputareQ0Q1Q2Q3=“1000”.
•For2
nd
clockoutputis“0100”,for3
rd
itis“0010”andso
on.Hence‘1’isshifteddiagonally.
Clock
Output
Q0 Q1 Q2 Q3
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 1 0 0 0
Truth Table 4.9
Operation of 4-Bit Ring Counter

182
LECTURE 33:- Johnson Counter
•CircuitdiagramissimilartoRingCounteronlydifference
isthecomplementedoutputoflastflipflopisconnected
inputtothe1
st
.
•Beforeapplyingclockcounterisresetbyclearinput.
When1
st
positiveclockarrivesoutputofthecounteris
“1000”for2
nd
clockitis“1100”forthirditis“1110”andso
on.Afterclock7
th
theoutputpatterngetsrepeated.
Fig.4.21 :4 –Bit Johnson Counter
4 –Bit Johnson/Twisted Counter

183
LECTURE 33:-
State Diagram & Truth Table
Johnson Counter
•Itshowsthathowthecounterpassesthroughdifferent
states(i.e.through8states).
•After8
th
statethepatterngetsrepeated.
•Statediagramsareusedtogiveanabstractdescriptionof
thebehaviorofasystem.
ClockQ3 Q2 Q1 Q0
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1Fig.4.22 :State Diagram
Truth Table 4.10

184
LECTURE 34:-
•DesignaMOD-6(Itgothrough6states)counter.
•Itmustrequiredminimumno.ofthreeflip-flops(No.of
states2^nwherenistheno.offlip-flops,Let’suseTflip
flop).
•TruthTableforoutputandinputtoflip-flopisasbelow-
Present state Next State Flip-flop input
Q2 Q1 Q0 Q2 Q1Q0 T2 T1 T0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 0 0 0 1 0 1
0 0 0 --- ------ --- ------
Design of Counter
Design of MOD-6 Counter
Truth Table 4.11

K-map for T1
K-map for T0
T1 = Q2’Q0
T0 = 1
K-map for T2
T2 = Q1Q0 + Q2Q0
185
LECTURE 34:-
K-mapforexpressingoutputintheformofinputfromthe
truthtable
Design of Counter
Design of MOD-6 Counter
Fig.4.23 :K-map for T1
Fig.4.24 :K-map for T0
Fig.4.25 :K-map for T2

186
LECTURE 34:-
T2 T1 T0
Q2’ Q1’ Q0’
CLK
Q2 Q1 Q0
•AspertherelationgetfromtheK-mapcircuitrealization
isdoneasbelow-
•Commonclockisappliedtoeachflipflopinthecounter.
•3T-flipflop,3ANDgatesand1ORgateisrequired.
Design of Counter
Design of MOD-6 Counter
Fig.4.26 :MOD-6 Counter

LECTURE 35:- Register
187
187
Introduction
•Typeofsequentiallogiccircuitforstorageofdigitaldata.
•Groupofflip-flopsconnectedinachainsothatthe
outputfromoneflip-flopbecomestheinputofthenext
flip-flop.
•Mostoftheregisterspossessnocharacteristicinternal
sequenceofstates.
•Alltheflip-flopsaredrivenbyacommonclock&allare
setorresetsimultaneously.
•BasictypesofShiftRegisterssuchasSerialIn-Serial
Out,SerialIn-ParallelOut,ParallelIn-SerialOut,
ParallelIn-ParallelOut,andBidirectionalshift
registers.

LECTURE 35:-
188
188
Serial In -Serial Out Shift Register
Abasicfour-bitshiftregistercanbeconstructedusingfour
Dflip-flops,havingsynchronousclockinput,outputoffirst
flipflop(FF0)isinputtosecond(FF1)andsoonasshown
below.
Various Register
Fig.4.27 :Serial In -Serial Out Shift Register

LECTURE 35:-
189
189
•Theregisterisfirstcleared,forcingallfouroutputsto
zero.
•TheinputdataisthenappliedsequentiallytotheDinput
ofthefirstflip-flopontheleft(FF0).
•Duringeachclockpulse,onebitistransmittedfromleft
toright.
•Assumeadatawordtobe1001.Theleastsignificant
bitofthedatahastobeshiftedthroughtheregisterfrom
FF0toFF3.
Operation of SISO
Various Register

190
LECTURE 36:-
Serial In -Parallel Out Shift Register
Various Register
Abasicfour-bitshiftregistercanbeconstructedusingfour
Dflip-flops,havingsynchronousclockinput,outputoffirst
flipflop(FF0)isinputtosecond(FF1)aswellasoutputas
‘Q0’andsoonClearinputisforresettingtheregister.
Outputcanbecheckaftereachclock.
Fig.4.28 :Serial In -Parallel Out Shift Register

191
LECTURE 36:-
•Forthiskindofregister,databitsareenteredseriallyin.
•Thedifferenceisthewayinwhichthedatabitsaretaken
outoftheregister.
•Oncethedataarestored,eachbitappearsonits
respectiveoutputline,andallbitsareavailable
simultaneously.
•Aconstructionofafour-bitserialin-paralleloutregister
isshowninpreviousslide.
Operation of SIPO
Various Register

LECTURE 37:-
192
192
•Afour-bitParallelIn-SerialOutshiftregisterisshown
below.ThecircuitusesDflip-flopsandNANDgatesfor
enteringdata(i.e.writing)totheregister.
Parallel In -Serial Out Shift Register
Various Register
Fig.4.29 :Parallel In -Serial Out Shift Register

193
LECTURE 37:-
193
193
•D0,D1,D2andD3aretheparallelinputs,whereD0is
themostsignificantbitandD3istheleastsignificantbit.
•Towritedatain,themodecontrollineistakentoLOW
andthedataisclockedin.Thedatacanbeshiftedwhen
themodecontrollineisHIGHasSHIFTisactivehigh.
•Theregisterperformsrightshiftoperationonthe
applicationofaclockpulse
Operation of PISO
Various Register

LECTURE 37:-
194
194
•ForParallelIn-ParallelOutshiftregisters,alldatabits
appearontheparalleloutputsimmediatelyfollowingthe
simultaneousentryofthedatabits.
•Thefollowingcircuitisafour-bitparallelin-parallelout
shiftregisterconstructedbyDflip-flops.
Parallel In -Parallel Out Shift Register
Various Register
Fig.4.30 :Parallel In -Parallel Out Shift Register

LECTURE 37:-
195
195
•TheD'saretheparallelinputsandtheQ'sarethe
paralleloutputs.
•Oncetheregisterisclocked,allthedataattheDinputs
appearatthecorrespondingQoutputssimultaneously.
Operation of PIPO
Various Register

LECTURE 37:-
19
6
•Modern digital Electronics-R. P. Jain, McGraw Hill.
•Digital Integrated Electronics-Herbert Taub, McGraw Hill.
•Digital Logic and Computer Design-Morris Mano(PHI).
•Digital Integrated Electronics-Herbert Taub, McGraw Hill.
•Digital Electronics Logic and System –James Bingnelland Robert
Donovan, CengageLearning
•Digital Circuits & Systems by K.R.Venugopal& K. Shaila
•http://npteldownloads.iitm.ac.in/downloads_mp4/117106086/lec01.mp4
•http://www.digital.iitkgp.ernet.in/dec/index.php
•http://vlab.co.in/ba_nptel_labs.php?id=1
•http://www.pa.msu.edu/courses/2012fall/PHY440/Flip%20flops.pdf
•http://www.techonicals.com/2013/01/difference-between-latch-and-flip-
flop.html
Chapter 4 References

LECTURE 37:-
197
Summary
1. Latch is a one bit memory element.
2. Clocked latch is also known as Flip-flop.
3. Flip-flops types are –a) D, b) SR, c) JK and d) T.
4. Preset and Clear are the two asynchronous input to flip-flop.
5. Using excitation table flip-flops can be converted into one another.
6. Counter is the sequential circuit which goes through the prescribed
sequence of states upon the application of input clock pulse.
There are basically two types of counter based on clocking-
a) Synchronous Counter b) Asynchronous (Ripple) Counter.
7. Modulus of counter are the number of states through which counter
progresses.
8. Johnson Counter in which complemented output of last flip flop is
connected input to the 1
st
flip flop.
9. Register can be defined as the set of the flip flop required to stored
the data in binary format. Types of register are as below-
a) SISO b) SIPO c) PISO d) PIPO e) Bidirectional shift register
f) Universal shift register.

LECTURE 37:-
198
•Differentiate between latch & flip-flop.
•Explain the triggering method used for flip-flop.
•What is preset & clear input of flip-flop?
•Draw logic diagram of JK flip-flop using NAND gate & explain it’s
working?
•What is Race around condition in JK flip-flop?
•What is Master slave JK flip-flop? Give logic dig. of JK master slave flip-
flop using NAND gate. Explain it’s working.
•Convert T flip-flop to JK flip-flop, convert JK flip-flop to D flip-flop.
•Define Register and Explain different types of shift registers .
•What is counter ? what are it’
s
type ?
•Design mod -5 counter using JK flip-flop.
•What are the merits & demerits of Synchronous counter over the
asynchronous counter ?
•Design & explain 3 bit up-down ripple counter.
•Explain the working of a Ring counter with a neat dig. & waveforms.
•Explain 4-bit Johnson counter with truth table & waveform.
Chapter 4 Question Bank

References Books:
199
•Modern digital Electronics-R. P. Jain, McGraw Hill.
•Digital Integrated Electronics-Herbert Taub, McGraw Hill.
•Digital Logic and Computer Design-Morris Mano(PHI).
•Digital Integrated Electronics-Herbert Taub, McGraw Hill.
•Digital Electronics Logic and System –James Bingnelland Robert
Donovan, CengageLearning
•Digital Circuits & Systems by K.R.Venugopal& K. Shaila
•8 bit Microprocessor by RameshGaonkar.
•8 bit microprocessor & controller by V. J. Vibhute, Techmak
Publication.
•8085 Microprocessor & its Applications by A. NagoorKani, Mc Graw
Hill.
Reference
Someslidesarecopiedfrommypreviousworki.e.PPTon
“DigitalCircuitandFundamentalofMicroprocessor”forwhichI
receivedcopyrighton07/06/2017.

Web Links:
200
•http://www.eazynotes.com/notes/microprocessor/Slides/instruction-set-of-
8085.pdf
•fac-web.spsu.edu/ecet/apreethy/2210_resources/8085.ppt
•pandeesvelu.weebly.com/uploads/1/0/7/4/10745695/interrupts.ppt
•http://www.daenotes.com/electronics/digital-electronics/decoder-encoder
•http://www.electronics-tutorials.ws/combination/comb_4.html
•http://www.slideshare.net/balajikulkarni/digital-electronics-by-anilkmaini?qid
=e0da9535-5fb5-4ca4-add3-a80361b9aa94&v=default&b=&from_search=3
•http://www.slideshare.net/shashank03/assembly-language-programming-
of-8085
•www.eeng.dcu.ie/~ee201/programmable_logic_Devices.ppt
•http://www.cpu-world.com/Arch/8085.html
•http://www.ehow.com/way_5230222_8085-microprocessor-tutorial.html
•http://microprocessorforyou.blogspot.in/2011/12/interrupts-in-8085-
microprocessor.html
•http://www.slideshare.net/saquib208/8085-microprocessor-ramesh-gaonkar
•klabs.org/richcontent/Tutorial/MiniCourses/reliable.../E_Hazards.ppt

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Digital Electronics & Fundamental of Microprocessor-I