Digital electronics sequential ckts counters

1 Counters, Classi�cation of counters, Comparison between Synchronous and Asynchronous counters
2 Asynchronous Counter, 2-Bit Asynchronous Binary Counter,
3-Bit Asynchronous Binary Counter, Asynchronous Decade Counter
3 Synchronous Counter, Ring Counters, Johnson/Twisted-Ring Counters

1. Digital Electronics
Sequential Circuits: Counters
Nilesh Bhaskarrao Bahadure
[email protected]
https://www.sites.google.com/site/nileshbbahadure/home
July 1, 2021
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 1 / 29

2. Overview
1
Counters
Classication of counters
Comparison between Synchronous and Asynchronous counters
2
Asynchronous Counter
2-Bit Asynchronous Binary Counter
3-Bit Asynchronous Binary Counter
Asynchronous Decade Counter
3
Synchronous Counter
Ring Counters
Johnson/Twisted-Ring Counters
4
Thank You
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 2 / 29

3. Counters
In digital logic and computing, a counter is a device which stores (and
sometimes displays) the number of times a particular event or process has
occurred, often in relationship to a clock signal.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 3 / 29

4. Counters
In digital logic and computing, a counter is a device which stores (and
sometimes displays) the number of times a particular event or process has
occurred, often in relationship to a clock signal.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 3 / 29

5. Classication of counters
In electronics, counters can be implemented quite easily using register-type
circuits such as the ip-op, and a wide variety of classications exist:
1
Asynchronous (ripple) counter - changing state bits are used as clocks
to subsequent state ip-ops.
2
Synchronous counter - all state bits change under control of a single
clock.
3
Decade counter - counts through ten states per stage.
4
Up/down counter - counts both up and down, under command of a
control input.
5
Ring counter - formed by a shift register with feedback connection in
a ring.
6
Johnson counter - a twisted ring counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 4 / 29

6. Classication of counters
In electronics, counters can be implemented quite easily using register-type
circuits such as the ip-op, and a wide variety of classications exist:
1
Asynchronous (ripple) counter - changing state bits are used as clocks
to subsequent state ip-ops.
2
Synchronous counter - all state bits change under control of a single
clock.
3
Decade counter - counts through ten states per stage.
4
Up/down counter - counts both up and down, under command of a
control input.
5
Ring counter - formed by a shift register with feedback connection in
a ring.
6
Johnson counter - a twisted ring counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 4 / 29

7. Classication of counters
In electronics, counters can be implemented quite easily using register-type
circuits such as the ip-op, and a wide variety of classications exist:
1
Asynchronous (ripple) counter - changing state bits are used as clocks
to subsequent state ip-ops.
2
Synchronous counter - all state bits change under control of a single
clock.
3
Decade counter - counts through ten states per stage.
4
Up/down counter - counts both up and down, under command of a
control input.
5
Ring counter - formed by a shift register with feedback connection in
a ring.
6
Johnson counter - a twisted ring counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 4 / 29

8. Classication of counters
In electronics, counters can be implemented quite easily using register-type
circuits such as the ip-op, and a wide variety of classications exist:
1
Asynchronous (ripple) counter - changing state bits are used as clocks
to subsequent state ip-ops.
2
Synchronous counter - all state bits change under control of a single
clock.
3
Decade counter - counts through ten states per stage.
4
Up/down counter - counts both up and down, under command of a
control input.
5
Ring counter - formed by a shift register with feedback connection in
a ring.
6
Johnson counter - a twisted ring counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 4 / 29

9. Classication of counters
In electronics, counters can be implemented quite easily using register-type
circuits such as the ip-op, and a wide variety of classications exist:
1
Asynchronous (ripple) counter - changing state bits are used as clocks
to subsequent state ip-ops.
2
Synchronous counter - all state bits change under control of a single
clock.
3
Decade counter - counts through ten states per stage.
4
Up/down counter - counts both up and down, under command of a
control input.
5
Ring counter - formed by a shift register with feedback connection in
a ring.
6
Johnson counter - a twisted ring counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 4 / 29

10. Classication of counters
In electronics, counters can be implemented quite easily using register-type
circuits such as the ip-op, and a wide variety of classications exist:
1
Asynchronous (ripple) counter - changing state bits are used as clocks
to subsequent state ip-ops.
2
Synchronous counter - all state bits change under control of a single
clock.
3
Decade counter - counts through ten states per stage.
4
Up/down counter - counts both up and down, under command of a
control input.
5
Ring counter - formed by a shift register with feedback connection in
a ring.
6
Johnson counter - a twisted ring counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 4 / 29

11. Classication of counters
In electronics, counters can be implemented quite easily using register-type
circuits such as the ip-op, and a wide variety of classications exist:
1
Asynchronous (ripple) counter - changing state bits are used as clocks
to subsequent state ip-ops.
2
Synchronous counter - all state bits change under control of a single
clock.
3
Decade counter - counts through ten states per stage.
4
Up/down counter - counts both up and down, under command of a
control input.
5
Ring counter - formed by a shift register with feedback connection in
a ring.
6
Johnson counter - a twisted ring counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 4 / 29

12. Comparison between Synchronous and Asynchronous
counters
1
In, Asynchronous the clock pulse inputs of all ip ops, except the
rst, are triggered not by the incoming pulses, but rather by the
transition that occurs in previous ip op's output. Whereas In a
synchronous counter, the input pulses are applied to all clock pulse
inputs of all ip ops simultaneously (directly).
2
Asynchronous counter is also known as serial sequential circuit
whereas Synchronous counter is also known as parallel sequential
circuit.
3
Asynchronous counters are slower than synchronous counter whereas
Synchronous counters are faster than asynchronous counter
4
Asynchronous circuits are quite dicult to design for a reliable
operation. Whereas Synchronous circuits are easy to design for a
reliable operation.
5
Example of asynchronous counter, Binary Ripple Counter, Up Down
Counter whereas example Synchronous counters Ring Counter,
Twisted ring counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 5 / 29

13. Comparison between Synchronous and Asynchronous
counters
1
In, Asynchronous the clock pulse inputs of all ip ops, except the
rst, are triggered not by the incoming pulses, but rather by the
transition that occurs in previous ip op's output. Whereas In a
synchronous counter, the input pulses are applied to all clock pulse
inputs of all ip ops simultaneously (directly).
2
Asynchronous counter is also known as serial sequential circuit
whereas Synchronous counter is also known as parallel sequential
circuit.
3
Asynchronous counters are slower than synchronous counter whereas
Synchronous counters are faster than asynchronous counter
4
Asynchronous circuits are quite dicult to design for a reliable
operation. Whereas Synchronous circuits are easy to design for a
reliable operation.
5
Example of asynchronous counter, Binary Ripple Counter, Up Down
Counter whereas example Synchronous counters Ring Counter,
Twisted ring counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 5 / 29

14. Comparison between Synchronous and Asynchronous
counters
1
In, Asynchronous the clock pulse inputs of all ip ops, except the
rst, are triggered not by the incoming pulses, but rather by the
transition that occurs in previous ip op's output. Whereas In a
synchronous counter, the input pulses are applied to all clock pulse
inputs of all ip ops simultaneously (directly).
2
Asynchronous counter is also known as serial sequential circuit
whereas Synchronous counter is also known as parallel sequential
circuit.
3
Asynchronous counters are slower than synchronous counter whereas
Synchronous counters are faster than asynchronous counter
4
Asynchronous circuits are quite dicult to design for a reliable
operation. Whereas Synchronous circuits are easy to design for a
reliable operation.
5
Example of asynchronous counter, Binary Ripple Counter, Up Down
Counter whereas example Synchronous counters Ring Counter,
Twisted ring counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 5 / 29

15. Comparison between Synchronous and Asynchronous
counters
1
In, Asynchronous the clock pulse inputs of all ip ops, except the
rst, are triggered not by the incoming pulses, but rather by the
transition that occurs in previous ip op's output. Whereas In a
synchronous counter, the input pulses are applied to all clock pulse
inputs of all ip ops simultaneously (directly).
2
Asynchronous counter is also known as serial sequential circuit
whereas Synchronous counter is also known as parallel sequential
circuit.
3
Asynchronous counters are slower than synchronous counter whereas
Synchronous counters are faster than asynchronous counter
4
Asynchronous circuits are quite dicult to design for a reliable
operation. Whereas Synchronous circuits are easy to design for a
reliable operation.
5
Example of asynchronous counter, Binary Ripple Counter, Up Down
Counter whereas example Synchronous counters Ring Counter,
Twisted ring counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 5 / 29

16. Comparison between Synchronous and Asynchronous
counters
1
In, Asynchronous the clock pulse inputs of all ip ops, except the
rst, are triggered not by the incoming pulses, but rather by the
transition that occurs in previous ip op's output. Whereas In a
synchronous counter, the input pulses are applied to all clock pulse
inputs of all ip ops simultaneously (directly).
2
Asynchronous counter is also known as serial sequential circuit
whereas Synchronous counter is also known as parallel sequential
circuit.
3
Asynchronous counters are slower than synchronous counter whereas
Synchronous counters are faster than asynchronous counter
4
Asynchronous circuits are quite dicult to design for a reliable
operation. Whereas Synchronous circuits are easy to design for a
reliable operation.
5
Example of asynchronous counter, Binary Ripple Counter, Up Down
Counter whereas example Synchronous counters Ring Counter,
Twisted ring counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 5 / 29

17. Asynchronous Counter
Ripple Counter Asynchronous counters called ripple counters, the rst ip-op is clocked
by the external clock pulse and then each successive ip-op is clocked by
the output of the receding ip-op. The term asynchronous refers to
events that do not have a xed time relationship with each other. An
asynchronous counter is one in which the ip-ops within the counter do
not change states at exactly the same time because they do not have a
common clock pulse.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 6 / 29

18. Asynchronous Counter
Ripple Counter Asynchronous counters called ripple counters, the rst ip-op is clocked
by the external clock pulse and then each successive ip-op is clocked by
the output of the receding ip-op. The term asynchronous refers to
events that do not have a xed time relationship with each other. An
asynchronous counter is one in which the ip-ops within the counter do
not change states at exactly the same time because they do not have a
common clock pulse.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 6 / 29

19. 2-Bit Asynchronous Binary Counter
Figure :
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 7 / 29

20. 2-Bit Asynchronous Binary Counter
A 2-Bit Asynchronous Binary Counter gure 1 shows a 2-bit counter
connected for asynchronous operation. Notice that the clock (CLK) is
applied to the clock input (C) of only the rst op-op, FF0, which is
always the least signicant bit (LSB). The second ip-op, FF1, is
triggered by theQ0out-put of FF0. FF0 changes state at the
positive-going edge of each clock pulse. But FF1 changes only when
triggered by a positive-going transition of theQ0output of FF0. Because
of the inherent propagation delay tie through a ip-op, a transition of the
input clock pulse (CLK) and a transition of theQ0output of FF0 can
never occur at exactly the same time . Therefore, the two ip-ops are
never simultaneously triggered, so the counter operation is asynchronous.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 8 / 29

21. 2-Bit Asynchronous Binary Counter
A 2-Bit Asynchronous Binary Counter gure 1 shows a 2-bit counter
connected for asynchronous operation. Notice that the clock (CLK) is
applied to the clock input (C) of only the rst op-op, FF0, which is
always the least signicant bit (LSB). The second ip-op, FF1, is
triggered by theQ0out-put of FF0. FF0 changes state at the
positive-going edge of each clock pulse. But FF1 changes only when
triggered by a positive-going transition of theQ0output of FF0. Because
of the inherent propagation delay tie through a ip-op, a transition of the
input clock pulse (CLK) and a transition of theQ0output of FF0 can
never occur at exactly the same time . Therefore, the two ip-ops are
never simultaneously triggered, so the counter operation is asynchronous.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 8 / 29

22. 2-Bit Asynchronous Binary Counter
Timing Diagram
Applying 4 clock pulses to FF0, Both ip-ops are connected for toggle operation (J=1,
K=1) and initially RESET (Q LOW).
The positive-going edge of CLK1 (clock pulse1)
causes the Q 0 output of FF0 to go HIGH.
At the same time theQ0output goes LOW,
but it has no eect on FF1 because a positive-going transition must occur to trigger the
ip-op.
After the leading edge of CLK1, Q0=1 & Q1=0.The positive-going edge of
CLK2 causes Q0 to go LOW.Q0goes HIGH and triggers FF1, causing Q1 to go HIGH.After the leading edge of CLK2, Q0=0 & Q1=1. The positive-going edge of CLK3 causes Q0 to go HIGH again.
OutputQ0goes LOW
and has no eect on FF1. Thus, after the leading edge of CLK3,Q0& Q1=1.
The
positive-going edge of CLK4 causes Q0 to go LOW, whileQ0goes HIGH and triggers
FF1, causing Q1 to go LOW.
After the leading edge of CLK4, Q0=0 & Q1=0.The 2-bit
counter exhibits four dierent states, as you would expect with two ip-ops (2
2
= 4).The fourth pulse it recycles to its original state (Q0=0, Q1=0). The term recycles; it
refers to the transition of the counter from its nal state back to its original state.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 9 / 29

23. 2-Bit Asynchronous Binary Counter
Timing Diagram
Applying 4 clock pulses to FF0, Both ip-ops are connected for toggle operation (J=1,
K=1) and initially RESET (Q LOW).
The positive-going edge of CLK1 (clock pulse1)
causes the Q 0 output of FF0 to go HIGH.
At the same time theQ0output goes LOW,
but it has no eect on FF1 because a positive-going transition must occur to trigger the
ip-op.
After the leading edge of CLK1, Q0=1 & Q1=0.The positive-going edge of
CLK2 causes Q0 to go LOW.Q0goes HIGH and triggers FF1, causing Q1 to go HIGH.After the leading edge of CLK2, Q0=0 & Q1=1. The positive-going edge of CLK3 causes Q0 to go HIGH again.
OutputQ0goes LOW
and has no eect on FF1. Thus, after the leading edge of CLK3,Q0& Q1=1.
The
positive-going edge of CLK4 causes Q0 to go LOW, whileQ0goes HIGH and triggers
FF1, causing Q1 to go LOW.
After the leading edge of CLK4, Q0=0 & Q1=0.The 2-bit
counter exhibits four dierent states, as you would expect with two ip-ops (2
2
= 4).The fourth pulse it recycles to its original state (Q0=0, Q1=0). The term recycles; it
refers to the transition of the counter from its nal state back to its original state.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 9 / 29

24. 2-Bit Asynchronous Binary Counter
Timing Diagram
Applying 4 clock pulses to FF0, Both ip-ops are connected for toggle operation (J=1,
K=1) and initially RESET (Q LOW).
The positive-going edge of CLK1 (clock pulse1)
causes the Q 0 output of FF0 to go HIGH.
At the same time theQ0output goes LOW,
but it has no eect on FF1 because a positive-going transition must occur to trigger the
ip-op.
After the leading edge of CLK1, Q0=1 & Q1=0.The positive-going edge of
CLK2 causes Q0 to go LOW.Q0goes HIGH and triggers FF1, causing Q1 to go HIGH.After the leading edge of CLK2, Q0=0 & Q1=1. The positive-going edge of CLK3 causes Q0 to go HIGH again.
OutputQ0goes LOW
and has no eect on FF1. Thus, after the leading edge of CLK3,Q0& Q1=1.
The
positive-going edge of CLK4 causes Q0 to go LOW, whileQ0goes HIGH and triggers
FF1, causing Q1 to go LOW.
After the leading edge of CLK4, Q0=0 & Q1=0.The 2-bit
counter exhibits four dierent states, as you would expect with two ip-ops (2
2
= 4).The fourth pulse it recycles to its original state (Q0=0, Q1=0). The term recycles; it
refers to the transition of the counter from its nal state back to its original state.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 9 / 29

25. 2-Bit Asynchronous Binary Counter
Timing Diagram
Applying 4 clock pulses to FF0, Both ip-ops are connected for toggle operation (J=1,
K=1) and initially RESET (Q LOW).
The positive-going edge of CLK1 (clock pulse1)
causes the Q 0 output of FF0 to go HIGH.
At the same time theQ0output goes LOW,
but it has no eect on FF1 because a positive-going transition must occur to trigger the
ip-op.
After the leading edge of CLK1, Q0=1 & Q1=0.The positive-going edge of
CLK2 causes Q0 to go LOW.Q0goes HIGH and triggers FF1, causing Q1 to go HIGH.After the leading edge of CLK2, Q0=0 & Q1=1. The positive-going edge of CLK3 causes Q0 to go HIGH again.
OutputQ0goes LOW
and has no eect on FF1. Thus, after the leading edge of CLK3,Q0& Q1=1.
The
positive-going edge of CLK4 causes Q0 to go LOW, whileQ0goes HIGH and triggers
FF1, causing Q1 to go LOW.
After the leading edge of CLK4, Q0=0 & Q1=0.The 2-bit
counter exhibits four dierent states, as you would expect with two ip-ops (2
2
= 4).The fourth pulse it recycles to its original state (Q0=0, Q1=0). The term recycles; it
refers to the transition of the counter from its nal state back to its original state.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 9 / 29

26. 2-Bit Asynchronous Binary Counter
Timing Diagram
Applying 4 clock pulses to FF0, Both ip-ops are connected for toggle operation (J=1,
K=1) and initially RESET (Q LOW).
The positive-going edge of CLK1 (clock pulse1)
causes the Q 0 output of FF0 to go HIGH.
At the same time theQ0output goes LOW,
but it has no eect on FF1 because a positive-going transition must occur to trigger the
ip-op.
After the leading edge of CLK1, Q0=1 & Q1=0.The positive-going edge of
CLK2 causes Q0 to go LOW.Q0goes HIGH and triggers FF1, causing Q1 to go HIGH.After the leading edge of CLK2, Q0=0 & Q1=1. The positive-going edge of CLK3 causes Q0 to go HIGH again.
OutputQ0goes LOW
and has no eect on FF1. Thus, after the leading edge of CLK3,Q0& Q1=1.
The
positive-going edge of CLK4 causes Q0 to go LOW, whileQ0goes HIGH and triggers
FF1, causing Q1 to go LOW.
After the leading edge of CLK4, Q0=0 & Q1=0.The 2-bit
counter exhibits four dierent states, as you would expect with two ip-ops (2
2
= 4).The fourth pulse it recycles to its original state (Q0=0, Q1=0). The term recycles; it
refers to the transition of the counter from its nal state back to its original state.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 9 / 29

27. 2-Bit Asynchronous Binary Counter
Timing Diagram
Applying 4 clock pulses to FF0, Both ip-ops are connected for toggle operation (J=1,
K=1) and initially RESET (Q LOW).
The positive-going edge of CLK1 (clock pulse1)
causes the Q 0 output of FF0 to go HIGH.
At the same time theQ0output goes LOW,
but it has no eect on FF1 because a positive-going transition must occur to trigger the
ip-op.
After the leading edge of CLK1, Q0=1 & Q1=0.The positive-going edge of
CLK2 causes Q0 to go LOW.Q0goes HIGH and triggers FF1, causing Q1 to go HIGH.After the leading edge of CLK2, Q0=0 & Q1=1. The positive-going edge of CLK3 causes Q0 to go HIGH again.
OutputQ0goes LOW
and has no eect on FF1. Thus, after the leading edge of CLK3,Q0& Q1=1.
The
positive-going edge of CLK4 causes Q0 to go LOW, whileQ0goes HIGH and triggers
FF1, causing Q1 to go LOW.
After the leading edge of CLK4, Q0=0 & Q1=0.The 2-bit
counter exhibits four dierent states, as you would expect with two ip-ops (2
2
= 4).The fourth pulse it recycles to its original state (Q0=0, Q1=0). The term recycles; it
refers to the transition of the counter from its nal state back to its original state.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 9 / 29

28. 2-Bit Asynchronous Binary Counter
Timing Diagram
Applying 4 clock pulses to FF0, Both ip-ops are connected for toggle operation (J=1,
K=1) and initially RESET (Q LOW).
The positive-going edge of CLK1 (clock pulse1)
causes the Q 0 output of FF0 to go HIGH.
At the same time theQ0output goes LOW,
but it has no eect on FF1 because a positive-going transition must occur to trigger the
ip-op.
After the leading edge of CLK1, Q0=1 & Q1=0.The positive-going edge of
CLK2 causes Q0 to go LOW.Q0goes HIGH and triggers FF1, causing Q1 to go HIGH.After the leading edge of CLK2, Q0=0 & Q1=1. The positive-going edge of CLK3 causes Q0 to go HIGH again.
OutputQ0goes LOW
and has no eect on FF1. Thus, after the leading edge of CLK3,Q0& Q1=1.
The
positive-going edge of CLK4 causes Q0 to go LOW, whileQ0goes HIGH and triggers
FF1, causing Q1 to go LOW.
After the leading edge of CLK4, Q0=0 & Q1=0.The 2-bit
counter exhibits four dierent states, as you would expect with two ip-ops (2
2
= 4).The fourth pulse it recycles to its original state (Q0=0, Q1=0). The term recycles; it
refers to the transition of the counter from its nal state back to its original state.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 9 / 29

29. 2-Bit Asynchronous Binary Counter
Timing Diagram
Applying 4 clock pulses to FF0, Both ip-ops are connected for toggle operation (J=1,
K=1) and initially RESET (Q LOW).
The positive-going edge of CLK1 (clock pulse1)
causes the Q 0 output of FF0 to go HIGH.
At the same time theQ0output goes LOW,
but it has no eect on FF1 because a positive-going transition must occur to trigger the
ip-op.
After the leading edge of CLK1, Q0=1 & Q1=0.The positive-going edge of
CLK2 causes Q0 to go LOW.Q0goes HIGH and triggers FF1, causing Q1 to go HIGH.After the leading edge of CLK2, Q0=0 & Q1=1. The positive-going edge of CLK3 causes Q0 to go HIGH again.
OutputQ0goes LOW
and has no eect on FF1. Thus, after the leading edge of CLK3,Q0& Q1=1.
The
positive-going edge of CLK4 causes Q0 to go LOW, whileQ0goes HIGH and triggers
FF1, causing Q1 to go LOW.
After the leading edge of CLK4, Q0=0 & Q1=0.The 2-bit
counter exhibits four dierent states, as you would expect with two ip-ops (2
2
= 4).The fourth pulse it recycles to its original state (Q0=0, Q1=0). The term recycles; it
refers to the transition of the counter from its nal state back to its original state.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 9 / 29

30. 2-Bit Asynchronous Binary Counter
Timing Diagram
Applying 4 clock pulses to FF0, Both ip-ops are connected for toggle operation (J=1,
K=1) and initially RESET (Q LOW).
The positive-going edge of CLK1 (clock pulse1)
causes the Q 0 output of FF0 to go HIGH.
At the same time theQ0output goes LOW,
but it has no eect on FF1 because a positive-going transition must occur to trigger the
ip-op.
After the leading edge of CLK1, Q0=1 & Q1=0.The positive-going edge of
CLK2 causes Q0 to go LOW.Q0goes HIGH and triggers FF1, causing Q1 to go HIGH.After the leading edge of CLK2, Q0=0 & Q1=1. The positive-going edge of CLK3 causes Q0 to go HIGH again.
OutputQ0goes LOW
and has no eect on FF1. Thus, after the leading edge of CLK3,Q0& Q1=1.
The
positive-going edge of CLK4 causes Q0 to go LOW, whileQ0goes HIGH and triggers
FF1, causing Q1 to go LOW.
After the leading edge of CLK4, Q0=0 & Q1=0.The 2-bit
counter exhibits four dierent states, as you would expect with two ip-ops (2
2
= 4).The fourth pulse it recycles to its original state (Q0=0, Q1=0). The term recycles; it
refers to the transition of the counter from its nal state back to its original state.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 9 / 29

31. 2-Bit Asynchronous Binary Counter
Timing Diagram
Applying 4 clock pulses to FF0, Both ip-ops are connected for toggle operation (J=1,
K=1) and initially RESET (Q LOW).
The positive-going edge of CLK1 (clock pulse1)
causes the Q 0 output of FF0 to go HIGH.
At the same time theQ0output goes LOW,
but it has no eect on FF1 because a positive-going transition must occur to trigger the
ip-op.
After the leading edge of CLK1, Q0=1 & Q1=0.The positive-going edge of
CLK2 causes Q0 to go LOW.Q0goes HIGH and triggers FF1, causing Q1 to go HIGH.After the leading edge of CLK2, Q0=0 & Q1=1. The positive-going edge of CLK3 causes Q0 to go HIGH again.
OutputQ0goes LOW
and has no eect on FF1. Thus, after the leading edge of CLK3,Q0& Q1=1.
The
positive-going edge of CLK4 causes Q0 to go LOW, whileQ0goes HIGH and triggers
FF1, causing Q1 to go LOW.
After the leading edge of CLK4, Q0=0 & Q1=0.The 2-bit
counter exhibits four dierent states, as you would expect with two ip-ops (2
2
= 4).The fourth pulse it recycles to its original state (Q0=0, Q1=0). The term recycles; it
refers to the transition of the counter from its nal state back to its original state.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 9 / 29

32. 2-Bit Asynchronous Binary Counter
Timing Diagram
Applying 4 clock pulses to FF0, Both ip-ops are connected for toggle operation (J=1,
K=1) and initially RESET (Q LOW).
The positive-going edge of CLK1 (clock pulse1)
causes the Q 0 output of FF0 to go HIGH.
At the same time theQ0output goes LOW,
but it has no eect on FF1 because a positive-going transition must occur to trigger the
ip-op.
After the leading edge of CLK1, Q0=1 & Q1=0.The positive-going edge of
CLK2 causes Q0 to go LOW.Q0goes HIGH and triggers FF1, causing Q1 to go HIGH.After the leading edge of CLK2, Q0=0 & Q1=1. The positive-going edge of CLK3 causes Q0 to go HIGH again.
OutputQ0goes LOW
and has no eect on FF1. Thus, after the leading edge of CLK3,Q0& Q1=1.
The
positive-going edge of CLK4 causes Q0 to go LOW, whileQ0goes HIGH and triggers
FF1, causing Q1 to go LOW.
After the leading edge of CLK4, Q0=0 & Q1=0.The 2-bit
counter exhibits four dierent states, as you would expect with two ip-ops (2
2
= 4).The fourth pulse it recycles to its original state (Q0=0, Q1=0). The term recycles; it
refers to the transition of the counter from its nal state back to its original state.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 9 / 29

33. 2-Bit Asynchronous Binary Counter
Timing Diagram
Applying 4 clock pulses to FF0, Both ip-ops are connected for toggle operation (J=1,
K=1) and initially RESET (Q LOW).
The positive-going edge of CLK1 (clock pulse1)
causes the Q 0 output of FF0 to go HIGH.
At the same time theQ0output goes LOW,
but it has no eect on FF1 because a positive-going transition must occur to trigger the
ip-op.
After the leading edge of CLK1, Q0=1 & Q1=0.The positive-going edge of
CLK2 causes Q0 to go LOW.Q0goes HIGH and triggers FF1, causing Q1 to go HIGH.After the leading edge of CLK2, Q0=0 & Q1=1. The positive-going edge of CLK3 causes Q0 to go HIGH again.
OutputQ0goes LOW
and has no eect on FF1. Thus, after the leading edge of CLK3,Q0& Q1=1.
The
positive-going edge of CLK4 causes Q0 to go LOW, whileQ0goes HIGH and triggers
FF1, causing Q1 to go LOW.
After the leading edge of CLK4, Q0=0 & Q1=0.The 2-bit
counter exhibits four dierent states, as you would expect with two ip-ops (2
2
= 4).The fourth pulse it recycles to its original state (Q0=0, Q1=0). The term recycles; it
refers to the transition of the counter from its nal state back to its original state.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 9 / 29

34. 2-Bit Asynchronous Binary Counter
Timing Diagram
Applying 4 clock pulses to FF0, Both ip-ops are connected for toggle operation (J=1,
K=1) and initially RESET (Q LOW).
The positive-going edge of CLK1 (clock pulse1)
causes the Q 0 output of FF0 to go HIGH.
At the same time theQ0output goes LOW,
but it has no eect on FF1 because a positive-going transition must occur to trigger the
ip-op.
After the leading edge of CLK1, Q0=1 & Q1=0.The positive-going edge of
CLK2 causes Q0 to go LOW.Q0goes HIGH and triggers FF1, causing Q1 to go HIGH.After the leading edge of CLK2, Q0=0 & Q1=1. The positive-going edge of CLK3 causes Q0 to go HIGH again.
OutputQ0goes LOW
and has no eect on FF1. Thus, after the leading edge of CLK3,Q0& Q1=1.
The
positive-going edge of CLK4 causes Q0 to go LOW, whileQ0goes HIGH and triggers
FF1, causing Q1 to go LOW.
After the leading edge of CLK4, Q0=0 & Q1=0.The 2-bit
counter exhibits four dierent states, as you would expect with two ip-ops (2
2
= 4).The fourth pulse it recycles to its original state (Q0=0, Q1=0). The term recycles; it
refers to the transition of the counter from its nal state back to its original state.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 9 / 29

35. 2-Bit Asynchronous Binary Counter
Figure :
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 10 / 29

36. 3-Bit Asynchronous Binary Counter
Figure :
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 11 / 29

37. 3-Bit Asynchronous Binary Counter
It works exactly the same way as a two-bit asynchronous binary counter
mentioned above, except it has eight states due to the third ip-op.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 12 / 29

38. 3-Bit Asynchronous Binary Counter
It works exactly the same way as a two-bit asynchronous binary counter
mentioned above, except it has eight states due to the third ip-op.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 12 / 29

39. 3-Bit Asynchronous Binary Counter
Figure :
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 13 / 29

40. Asynchronous Decade Counter/BCD Counter/Divide by 10
Counter
If we take the modulo-16 asynchronous counter and modied it with
additional logic gates it can be made to give a decade (divide-by-10)
counter output for use in standard decimal counting and arithmetic
circuits.
Such counters are generally referred to as Decade Counters. A decade
counter requires resetting to zero when the output count reaches the
decimal value of 10, ie. when DCBA = 1010 and to do this we need to
feed this condition back to the reset input. A counter with a count
sequence from binary "0000" (BCD = "0") through to \1001" (BCD =
"9") is generally referred to as a BCD binary-coded-decimal counter
because its ten state sequence is that of a BCD code but binary decade
counters are more common.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 14 / 29

41. Asynchronous Decade Counter/BCD Counter/Divide by 10
Counter
If we take the modulo-16 asynchronous counter and modied it with
additional logic gates it can be made to give a decade (divide-by-10)
counter output for use in standard decimal counting and arithmetic
circuits.
Such counters are generally referred to as Decade Counters. A decade
counter requires resetting to zero when the output count reaches the
decimal value of 10, ie. when DCBA = 1010 and to do this we need to
feed this condition back to the reset input. A counter with a count
sequence from binary "0000" (BCD = "0") through to \1001" (BCD =
"9") is generally referred to as a BCD binary-coded-decimal counter
because its ten state sequence is that of a BCD code but binary decade
counters are more common.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 14 / 29

42. Asynchronous Decade Counter/BCD Counter/Divide by 10
Counter
If we take the modulo-16 asynchronous counter and modied it with
additional logic gates it can be made to give a decade (divide-by-10)
counter output for use in standard decimal counting and arithmetic
circuits.
Such counters are generally referred to as Decade Counters. A decade
counter requires resetting to zero when the output count reaches the
decimal value of 10, ie. when DCBA = 1010 and to do this we need to
feed this condition back to the reset input. A counter with a count
sequence from binary "0000" (BCD = "0") through to \1001" (BCD =
"9") is generally referred to as a BCD binary-coded-decimal counter
because its ten state sequence is that of a BCD code but binary decade
counters are more common.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 14 / 29

43. Asynchronous Decade Counter
Figure :
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 15 / 29

44. Asynchronous Decade Counter...
This type of asynchronous counter counts upwards on each trailing edge of
the input clock signal starting from 0000 until it reaches an output 1001
(decimal 9). Both outputs QA and QD are now equal to logic "1". On the
application of the next clock pulse, the output from the 74LS10 NAND
gate changes state from logic "1" to a logic "0" level.
As the output of the NAND gate is connected to the CLEAR ( CLR )
inputs of all the 74LS73 J-K Flip-ops, this signal causes all of the Q
outputs to be reset back to binary 0000 on the count of 10. As outputs
QA and QD are now both equal to logic "0" as the ip-ops have just
been reset, the output of the NAND gate returns back to a logic level "1"
and the counter restarts again from 0000. We now have a decade or
Modulo-10 up-counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 16 / 29

45. Asynchronous Decade Counter...
This type of asynchronous counter counts upwards on each trailing edge of
the input clock signal starting from 0000 until it reaches an output 1001
(decimal 9). Both outputs QA and QD are now equal to logic "1". On the
application of the next clock pulse, the output from the 74LS10 NAND
gate changes state from logic "1" to a logic "0" level.
As the output of the NAND gate is connected to the CLEAR ( CLR )
inputs of all the 74LS73 J-K Flip-ops, this signal causes all of the Q
outputs to be reset back to binary 0000 on the count of 10. As outputs
QA and QD are now both equal to logic "0" as the ip-ops have just
been reset, the output of the NAND gate returns back to a logic level "1"
and the counter restarts again from 0000. We now have a decade or
Modulo-10 up-counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 16 / 29

46. Asynchronous Decade Counter...
This type of asynchronous counter counts upwards on each trailing edge of
the input clock signal starting from 0000 until it reaches an output 1001
(decimal 9). Both outputs QA and QD are now equal to logic "1". On the
application of the next clock pulse, the output from the 74LS10 NAND
gate changes state from logic "1" to a logic "0" level.
As the output of the NAND gate is connected to the CLEAR ( CLR )
inputs of all the 74LS73 J-K Flip-ops, this signal causes all of the Q
outputs to be reset back to binary 0000 on the count of 10. As outputs
QA and QD are now both equal to logic "0" as the ip-ops have just
been reset, the output of the NAND gate returns back to a logic level "1"
and the counter restarts again from 0000. We now have a decade or
Modulo-10 up-counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 16 / 29

47. Clock Output bit Pattern Decimal
Count QD QC QB QA Value
1 0 0 0 0 0
2 0 0 0 1 1
3 0 0 1 0 2
4 0 0 1 1 3
5 0 1 0 0 4
6 0 1 0 1 5
7 0 1 1 0 6
8 0 1 1 1 7
9 1 0 0 0 8
10 1 0 0 1 9
11 Counter Resets its Outputs back to Zero
Table :
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 17 / 29

48. Asynchronous Decade Counter
Figure :
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 18 / 29

49. How to decide number of ip ops in Modulo
Asynchronous Counter
Mod -40
Lets say we wish to count from 0 to 39, or mod-40 and repeat. Then the
highest number of ip-ops required would be six, n = 6 giving a
maximum MOD of 64 as ve ip-ops would not be enough as this only
gives us a MOD-32.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 19 / 29

50. Synchronous Counter
In synchronous counters, the clock input is connected to all of the
ip-ops so that they are clocked simultaneously. The term synchronous
refers to events that have a xed time relationship with each other.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 20 / 29

51. Ring Counters
Ring counters are implemented using shift registers. It is essentially a
circulating shift register connected so that the last ip-op shifts its value
into the rst ip-op. There is usually only a single 1 circulating in the
register, as long as clock pulses are applied.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 21 / 29

52. Ring Counters
Ring counters are implemented using shift registers. It is essentially a
circulating shift register connected so that the last ip-op shifts its value
into the rst ip-op. There is usually only a single 1 circulating in the
register, as long as clock pulses are applied.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 21 / 29

53. Ring Counters...
Figure :
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 22 / 29

54. Ring Counters...
In the diagram above, assuming a starting state of Q3 = 1 and Q2 = Q1
= Q0 = 0. At the rst pulse, the 1 shifts from Q3 to Q2 and the counter
is in the 0100 state. The next pulse produces the 0010 state and the third,
0001. At the fourth pulse, the 1 at Q0 is transferred back to Q3, resulting
in the 1000 state, which is the initial state. Subsequent pulses will cause
the sequence to repeat, hence the name ring counter.
The ring counter above functions as a MOD-4 counter since it has four
distinct states and each ip-op output waveform has a frequency equal to
one-fourth of the clock frequency. A ring counter can be constructed for
any MOD number. A MOD-N ring counter will require N ip-ops
connected in the arrangement as the diagram above.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 23 / 29

55. Ring Counters...
In the diagram above, assuming a starting state of Q3 = 1 and Q2 = Q1
= Q0 = 0. At the rst pulse, the 1 shifts from Q3 to Q2 and the counter
is in the 0100 state. The next pulse produces the 0010 state and the third,
0001. At the fourth pulse, the 1 at Q0 is transferred back to Q3, resulting
in the 1000 state, which is the initial state. Subsequent pulses will cause
the sequence to repeat, hence the name ring counter.
The ring counter above functions as a MOD-4 counter since it has four
distinct states and each ip-op output waveform has a frequency equal to
one-fourth of the clock frequency. A ring counter can be constructed for
any MOD number. A MOD-N ring counter will require N ip-ops
connected in the arrangement as the diagram above.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 23 / 29

56. Ring Counters...
In the diagram above, assuming a starting state of Q3 = 1 and Q2 = Q1
= Q0 = 0. At the rst pulse, the 1 shifts from Q3 to Q2 and the counter
is in the 0100 state. The next pulse produces the 0010 state and the third,
0001. At the fourth pulse, the 1 at Q0 is transferred back to Q3, resulting
in the 1000 state, which is the initial state. Subsequent pulses will cause
the sequence to repeat, hence the name ring counter.
The ring counter above functions as a MOD-4 counter since it has four
distinct states and each ip-op output waveform has a frequency equal to
one-fourth of the clock frequency. A ring counter can be constructed for
any MOD number. A MOD-N ring counter will require N ip-ops
connected in the arrangement as the diagram above.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 23 / 29

57. Ring Counters...
A ring counter requires more ip-ops than a binary counter for the same
MOD number. For example, a MOD-8 ring counter requires 8 ip-ops
while a MOD-8 binary counter only requires 3 (23 = 8). So if a ring
counter is less ecient in the use of ip-ops than a binary counter, why
do we still need ring counters? One main reason is because ring counters
are much easier to decode. In fact, ring counters can be decoded without
the use of logic gates. The decoding signal is obtained at the output of its
corresponding ip-op.
For the ring counter to operate properly, it must start with only one
ip-op in the 1 state and all the others at 0. Since it is not possible to
expect the counter to come up to this state when power is rst applied to
the circuit, it is necessary to preset the counter to the required starting
state before the clock pulses are applied. One way to do this is to apply a
pulse to the PRESET input of one of the ip-ops and the CLEAR inputs
of all the others. This will place a single 1 in the ring counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 24 / 29

58. Ring Counters...
A ring counter requires more ip-ops than a binary counter for the same
MOD number. For example, a MOD-8 ring counter requires 8 ip-ops
while a MOD-8 binary counter only requires 3 (23 = 8). So if a ring
counter is less ecient in the use of ip-ops than a binary counter, why
do we still need ring counters? One main reason is because ring counters
are much easier to decode. In fact, ring counters can be decoded without
the use of logic gates. The decoding signal is obtained at the output of its
corresponding ip-op.
For the ring counter to operate properly, it must start with only one
ip-op in the 1 state and all the others at 0. Since it is not possible to
expect the counter to come up to this state when power is rst applied to
the circuit, it is necessary to preset the counter to the required starting
state before the clock pulses are applied. One way to do this is to apply a
pulse to the PRESET input of one of the ip-ops and the CLEAR inputs
of all the others. This will place a single 1 in the ring counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 24 / 29

59. Ring Counters...
A ring counter requires more ip-ops than a binary counter for the same
MOD number. For example, a MOD-8 ring counter requires 8 ip-ops
while a MOD-8 binary counter only requires 3 (23 = 8). So if a ring
counter is less ecient in the use of ip-ops than a binary counter, why
do we still need ring counters? One main reason is because ring counters
are much easier to decode. In fact, ring counters can be decoded without
the use of logic gates. The decoding signal is obtained at the output of its
corresponding ip-op.
For the ring counter to operate properly, it must start with only one
ip-op in the 1 state and all the others at 0. Since it is not possible to
expect the counter to come up to this state when power is rst applied to
the circuit, it is necessary to preset the counter to the required starting
state before the clock pulses are applied. One way to do this is to apply a
pulse to the PRESET input of one of the ip-ops and the CLEAR inputs
of all the others. This will place a single 1 in the ring counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 24 / 29

60. Johnson/Twisted-Ring Counters
The Johnson counter, also known as the twisted-ring counter, is exactly
the same as the ring counter except that the inverted output of the last
ip-op is connected to the input of the rst ip-op.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 25 / 29

61. Johnson/Twisted-Ring Counters
The Johnson counter, also known as the twisted-ring counter, is exactly
the same as the ring counter except that the inverted output of the last
ip-op is connected to the input of the rst ip-op.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 25 / 29

62. Ring Counters...
Figure :
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 26 / 29

63. Ring Counters...
The Johnson counter works in the following way : Take the initial state of
the counter to be 000. On the rst clock pulse, the inverse of the last
ip-op will be fed into the rst ip-op, producing the state 100. On the
second clock pulse, since the last ip-op is still at level 0, another 1 will
be fed into the rst ip-op, giving the state 110. On the third clock
pulse, the state 111 is produced. On the fourth clock pulse, the inverse of
the last ip-op, now a 0, will be shifted to the rst ip-op, giving the
state 011. On the fth and sixth clock pulse, using the same reasoning, we
will get the states 001 and 000, which is the initial state again. Hence,
this Johnson counter has six distinct states : 000, 100, 110, 111, 011 and
001, and the sequence is repeated so long as there is input pulse. Thus
this is a MOD-6 Johnson counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 27 / 29

64. Ring Counters...
The Johnson counter works in the following way : Take the initial state of
the counter to be 000. On the rst clock pulse, the inverse of the last
ip-op will be fed into the rst ip-op, producing the state 100. On the
second clock pulse, since the last ip-op is still at level 0, another 1 will
be fed into the rst ip-op, giving the state 110. On the third clock
pulse, the state 111 is produced. On the fourth clock pulse, the inverse of
the last ip-op, now a 0, will be shifted to the rst ip-op, giving the
state 011. On the fth and sixth clock pulse, using the same reasoning, we
will get the states 001 and 000, which is the initial state again. Hence,
this Johnson counter has six distinct states : 000, 100, 110, 111, 011 and
001, and the sequence is repeated so long as there is input pulse. Thus
this is a MOD-6 Johnson counter.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 27 / 29

65. Ring Counters...
The MOD number of a Johnson counter is twice the number of ip-ops.
In the example above, three ip-ops were used to create the MOD-6
Johnson counter. So for a given MOD number, a Johnson counter requires
only half the number of ip-ops needed for a ring counter. However, a
Johnson counter requires decoding gates whereas a ring counter doesnt.
As with the binary counter, one logic gate (AND gate) is required to
decode each state, but with the Johnson counter, each gate requires only
two inputs, regardless of the number of ip-ops in the counter. Note that
we are comparing with the binary counter using the speed up technique
discussed above. The reason for this is that for each state, two of the N
ip-ops used will be in a unique combination of states. In the example
above, the combination Q2 = Q1 = 0 occurs only once in the counting
sequence, at the count of 0. The state 010 does not occur. Thus, an AND
gate with inputs (not Q2) and (not Q2) can be used to decode for this
state. The same characteristic is shared by all the other states in the
sequence.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 28 / 29

66. Ring Counters...
The MOD number of a Johnson counter is twice the number of ip-ops.
In the example above, three ip-ops were used to create the MOD-6
Johnson counter. So for a given MOD number, a Johnson counter requires
only half the number of ip-ops needed for a ring counter. However, a
Johnson counter requires decoding gates whereas a ring counter doesnt.
As with the binary counter, one logic gate (AND gate) is required to
decode each state, but with the Johnson counter, each gate requires only
two inputs, regardless of the number of ip-ops in the counter. Note that
we are comparing with the binary counter using the speed up technique
discussed above. The reason for this is that for each state, two of the N
ip-ops used will be in a unique combination of states. In the example
above, the combination Q2 = Q1 = 0 occurs only once in the counting
sequence, at the count of 0. The state 010 does not occur. Thus, an AND
gate with inputs (not Q2) and (not Q2) can be used to decode for this
state. The same characteristic is shared by all the other states in the
sequence.
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 28 / 29

67. Thank you
Please send your feedback at [email protected]
For download Click Here]
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 29 / 29

68. Thank you
Please send your feedback at [email protected]
For download Click Here]
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 29 / 29