Digital logic circuits seca 233047 published in elancho university australia

dlc plays major role in vlsi

1. 1
Lecture 1: Introduction to
Digital Logic Design
CK Cheng
CSE Dept.
UC San Diego

2. 2
Outlines
•Administration
•Motivation
•Scope

3. 3
Administration
Web site:
http://www.cse.ucsd.edu/classes/sp09/cse140/
WebBoard:
http://webboard.ucsd.edu

4. 4
Administration
Instructor: CK Cheng, CSE2130,
[email protected], 858 534-6184
Teaching Assistants:
•Thomas Weng, [email protected]
•Renshen Wang, [email protected]
•Chengmo Yang, [email protected]
•Mingjing Chen, [email protected]

5. 5
Administration
Schedule
•Outlines (Use index to check the location of
the textbook)
•Lectures: 2:00-3:20PM, TTh, Center 216.
•Discussion: 2:00-2:50PM, M, Center 212.
•Office hours: 10:30-11:30AM, TTh, CSE
2130.

6. 6
Administration
Textbook
•Digital Design and Computer Architecture,
David Money Harris and Sarah L. Harris,
published by Morgan Kaufmann, 2007.
Grading
•Midterm 1: 25% (T 4/21)
•Midterm 2: 30% (Th 5/14)
•Final Exam: 40% (3:00-6:00PM, Th 6/11)

7. 7
Motivation
•Microprocessors have revolutionized our world
–Cell phones, internet, rapid advances in
medicine, etc.
•The semiconductor industry has grown from $21
billion in 1985 to $213 billion in 2004.

8. 8
Robert Noyce, 1927 - 1990
•Nicknamed “Mayor of Silicon
Valley”
•Cofounded Fairchild
Semiconductor in 1957
•Cofounded Intel in 1968
•Co-invented the integrated
circuit

9. 9
Gordon Moore, 1929 -
•Cofounded Intel in
1968 with Robert
Noyce.
•Moore’s Law: the
number of transistors
on a computer chip
doubles every year
(observed in 1965)
•Since 1975, transistor
counts have doubled
every two years.

10. 10
Moore’s Law
“If the automobile had followed the same development cycle as the
computer, a Rolls-Royce would today cost $100, get one million
miles to the gallon, and explode once a year . . .”
– Robert Cringley

11. 11
Scope
•The purpose of this course is that we:
–Learn what’s under the hood of an electronic
component
–Learn the principles of digital design
–Learn to systematically debug increasingly
complex designs
–Design and build a digital system

12. 12
Scope
•Hiding details when
they aren’t important
Physics
Devices
Analog
Circuits
Digital
Circuits
Logic
Micro-
architecture
Architecture
Operating
Systems
Application
Software
electrons
transistors
diodes
amplifiers
filters
AND gates
NOT gates
adders
memories
datapaths
controllers
instructions
registers
device drivers
programs
f
o
c
u
s

o
f

t
h
i
s

c
o
u
r
s
e

13. 13
We will cover four major things in this
course:
- Combinational Logic (Ch 2)
- Sequential Networks (Ch 3)
- Standard Modules (Ch 5)
- System Design (Chs 4, 6-8)

14. 14
Overall Picture of CS140
Control
Subsystem
Conditions
Control
Mux
Memory File
ALU
Memory
Register
Conditions
Input
Pointer
CLK: Synchronizing Clock

15. 15
f
i(x)
x
1
.
.
.
x
n
f
i(x)
Combinational Logic vs Sequential Network
Combinational logic:
y
i = f
i(x
1,..,x
n)
CLK
Sequential Networks
1) Memory 2) Time Steps (Clock)
y
i
t
= f
i (x
1
t
,…,x
n
t
, s
1
t
, …,s
m
t
)
S
i
t+1
= g
i(x
1
t
,…,x
n
t
, s
1
t
,…,s
m
t
)
f
i
(x)
x
1
.
.
.
x
n
f
i
(x)f
i
(x)
x
1
.
.
.
x
n
f
i
(x) s
i

16. 16
Scope
Subjects Building BlocksTheory
Combinational
Logic
AND, OR,
NOT,XOR
Boolean
Algebra
Sequential
Network
AND, OR,
NOT, FF
Finite State
Machine
Standard
Modules
Operators,
Interconnects,
Memory
Arithmetics,
Universal Logic
System DesignData Paths,
Control Paths
Methodologies

17. 17
Part I. Combinational Logic
•I) Specification
•II) Implementation
•III) Different Types of Gates
ab + cd
a
b
c
d
e
cd
ab
e (ab+cd)