DMA It can give more time to an intersection approach that is experiencing heavy .pptx

It can give more time to an intersection approach that is experiencing heavy traffic, or shorten or even skip a phase that has little or no traffic waiting for a green light.

1. Modes of DMA Transfer Direct Memory Access (DMA): DMA basically stands for Direct Memory Access. It is a process which enables data transfer between the Memory and the IO (Input/ Output) device without the need of or you can say without the involvement of CPU during data transfer. Modes of DMA Transfer: During the DMA Transfer CPU can perform only those operation in which it doesn’t require the access of System Bus which means mostly CPU will be in blocked state. For how much time CPU remains in the blocked state or we can say for how much time CPU will give the control of DMAC of system buses will actually depend upon the following modes of DMA Transfer and after that CPU will take back control of system buses from DMAC.

2. Mode-1:  Burst Mode – DMA returns the bus after complete data transfer. A register is used as a byte count, being decremented for each byte transfer, and upon the byte count reaching zero, the DMAC will release the bus. When the DMAC operates in burst mode, the CPU is halted for the duration of the data transfer. In this mode Burst of data (entire data or burst of block containing data) is transferred before CPU takes control of the buses back from DMAC. This is the quickest mode of DMA Transfer since at once a huge amount of data is being transferred. Since at once only the huge amount of data is being transferred so time will be saved in huge amount.

3. Mode-2:   Cyclic Stealing : An alternative method in which DMA controller transfers one word at a time after which it must return the control of the buses to the CPU. The CPU delays its operation only for one memory cycle to allow the direct memory I/O transfer to “steal” one memory cycle.

4. Data Transfer Schemes Programmed I/O : It is due to the result of the I/O instructions that are written in the computer program. Each data item transfer is initiated by an instruction in the program. Usually the transfer is from a CPU,register and memory. In this case it requires constant monitoring by the CPU of the peripheral devices.

5. I/O ports: 8051 microcontrollers have 4 I/O ports each of 8-bit, which can be configured as input or output. Hence, total 32 input/output pins allow the microcontroller to be connected with the peripheral devices . Pin configuration , i.e. the pin can be configured as 1 for input and 0 for output as per the logic state. Input/Output (I/O) pin  − All the circuits within the microcontroller must be connected to one of its pins except P0 port because it does not have pull-up resistors built-in. Input pin  − Logic 1 is applied to a bit of the P register. The output FE transistor is turned off and the other pin remains connected to the power supply voltage over a pull-up resistor of high resistance. Port 0  − The P0 (zero) port is characterized by two functions − When the external memory is used then the lower address byte (addresses A0A7) is applied on it, else all bits of this port are configured as input/output. When P0 port is configured as an output then other ports consisting of pins with built-in pull-up resistor connected by its end to 5V power supply, the pins of this port have this resistor left out.

6. Input Configuration If any pin of this port is configured as an input, then it acts as if it “floats”, i.e. the input has unlimited input resistance and in-determined potential. Output Configuration When the pin is configured as an output, then it acts as an “open drain”. By applying logic 0 to a port bit, the appropriate pin will be connected to ground (0V), and applying logic 1, the external output will keep on “floating”. In order to apply logic 1 (5V) on this output pin, it is necessary to build an external pullup resistor.

7. Ports: Port 1: P1 is a true I/O port as it doesn’t have any alternative functions as in P0, but this port can be configured as general I/O only. It has a built-in pull-up resistor and is completely compatible with TTL circuits. Port 2: P2 is similar to P0 when the external memory is used. Pins of this port occupy addresses intended for the external memory chip. This port can be used for higher address byte with addresses A8-A15. When no memory is added then this port can be used as a general input/output port similar to Port 1. Port 3: In this port, functions are similar to other ports except that the logic 1 must be applied to appropriate bit of the P3 register.

8. Purpose of Polling and Interrupts Polling and interrupts are used to efficiently manage and handle communication between the  CPU  and other devices such as I/ Os and  sensors  in computing systems. Implementing such mechanisms helps to ensure timely responses to events and enhanced system performance. While polling and interrupts are used for a similar purpose, they each have different operation methods that come with their own advantages and disadvantages.

9. What is Polling? Polling is a method where a device continuously checks the status of another device to determine if it needs attention. This involves sending requests or queries to the device, waiting for a response, and repeating this process in a loop until the desired condition or data is obtained .

10. Advantages of polling include: Simplicity : It is a simpler mechanism to implement and provides straightforward control over the process. Compatibility: Polling can work on systems that do not support interrupt-driven mechanisms, making it widely applicable across various platforms. Predictability: Since the system checks for data at regular intervals, the behavior is predictable and can be fine-tuned for specific performance requirements . Disadvantages of polling include: Resource Intensive: Constantly checking for data or events consumes system resources, including CPU cycles, leading to inefficiency and wasted power. Latency: There can be a delay between the occurrence of an event and the system detecting it, especially if the polling interval is long, leading to higher latency in event processing. Complexity in Real-Time Systems: In real-time applications where immediate responses are critical, polling may not be suitable.

11. Polling and Interrupts in Communication Protocols In communication protocols such as I2C, SPI, USB, and CAN, both polling and interrupts are vital mechanisms in facilitating efficient data exchange in  embedded systems . Total Phase offers a line of host adapters and protocol analyzers for I2C, SPI, USB, CAN, and eSPI systems to help engineers streamline their debugging and developing efforts. Our host adapters allow engineers to emulate entire systems, including master and slave devices, to test and validate operations and responses between each other. Our protocol analyzers provide advanced visibility into the bus, allowing users to view bus communication and any errors in real time. These tools allow users to confirm systems and their operations, including polling or interrupt mechanisms, are working as expected.