DRAM PPT ADVANTAGES AND DISADVANTAGES APPLICATION

DRAM PPT Advantage disadvantage

1. A SEMINAR PRESENTATION ON PHASE LOCKED LOOP (PLL) Department of Electronics & Communication Engineering Bhagalpur College Of Engineering , Bhagalpur Registration Number - 22141108020 Presented By - Akanksha Arya Roll Number - 22MECE09 Dr Pushpalata Under The Supervision Of HOD , ECE Department

2. CONTENTS What is PLL Why do we use PLL Block diagram of PLL Stages of PLL operation Ranges of PLL Application of PLL Conclusion and Future scope References

3. What is PLL? A phase-locked loop (PLL) is a feedback system containing a voltage controlled oscillator and a phase comparator so connected that the oscillator maintains a constant phase angle relative to a reference signal. PLLs are used to generate, stabilize,  modulate , demodulate, filter or recover a signal from a "noisy" communications channel where data has been interrupted.

4. PLL When phase between signal changes it means that they have different frequencies. When phase difference remains constant frequencies are equal.

5. WHY WE USE PLL? VCO cannot produce stable high frequency carrier. VCO is affected by temperature and noise. So we need a reference with stable frequency and we force VCO to follow that reference.

6. BLOCK DIAGRAM OF PLL

7. PHASE DETECTOR A phase detector is basically a comparator that compares input frequency fi with feedback frequency fo . Comparing the input frequency and output frequency it provides error signal which is basically a dc voltage. The loop is locked when these two signals are of the same frequency and have a fixed phase difference. Basically phase detector works as an Ex-OR gate.

8. LOW PASS FILTER Low pass filter is used to remove high frequency components and noise from output of the phase detector. Low pass filter provides a steady dc level voltage which becomes the input of VCO.

9. VOLTAGE CONTROLLED OSCILLATOR Voltage controlled oscillator generates frequency controlled by input voltage. The dc level output of a low pass filter is applied as control signal to voltage-controlled oscillator The VCO frequency is adjusted till it becomes equal to the frequency of the input signal. During this adjustment, PLL goes through three stages-free running,capture and phase lock.

10. STAGES OF PLL OPERATION 1. FREE RUNNING STAGES 2. CAPTURE STAGE 3. PHASE LOCKED STATE

11. When input frequency is applied at the phase detector then due to feedback mechanism PLL tries to track the output wrt input . PHASE LOCKED STATE When no input is applied at the phase detector, then due to VCO, PLL works in free running stage.The output frequency of this stage is dependent on the free running of VCO. FREE RUNNING STAGES CAPTURE STAGE Due to feedback mechanism ,the comparison stops as soon as the output frequency becomes equal to the input frequency. This stage is called phase locked state . Due to feedback mechanism ,the comparison stops as soon as the output frequency becomes equal to the input frequency. This stage is called phase locked state.

12. RANGES OF PLL

13. RANGES OF PHASE LOCKED LOOP .

14. PLL can acquire lock state only when input signal is within capture range. 1. CAPTURE RANGE The range of input frequencies around the VCO center frequency in which loop can lock when starting from unlocked condition. 2. LOCK RANGE The range of input frequencies over which the loop remain in the lock condition once it has captured the input signal.

15. APPLICATION The majority of PLL applications fall into four main categories: Frequency synthesis(Most widely PLL used as a frequency synthesiser) Frequency (FM), Phase (PM) and Amplitude modulation and demodulation Radar synchronization and communication Data and carrier recovery Tracking filters.

16. CONCLUSION AND FUTURE SCOPE In this work a PLL with a better lock time is presented . The lock time of PLL is found to be 280.6 ns The lock time of PLL mainly depends upon the type of PFD architecture and adjusting the charge pump and loop filter. The centre frequency of oscillation of the VCO depends upon the sizing of the transistor. The convex technique is used to find out the transistor sizing to meet only the desired frequency specification. The other constraint like area,power and phase noise can also be applied.

17. 1] J. J. Stiffler, Theory of Synch EngleCambridge , Mass.: M.I.T. Press, 1969. 2] J. Klapper and J. T. Frankle , Phase-Locked and Frrquencywood Cliffs, N.J.: Prentice-Hall, 1971. 3] W. C. Lindsey, Synchronization Systems in Communications. Feedback System. New York: Academic Press, 1972. Englewood Cliffs, N.J.: Prentice-Hall, 1972 4] R.E. Best ,Phase locked loop Design ,Simulation and Appllications,McGraw -Hill Publications 5 th edition 2002 5] Phase locked loops 6/e ,6 th edition by Roland Best REFERENCES