Dynamic Power Consumption In Large FPGAs.ppt

Dynamic Power Consumption In Large FPGAs.ppt

1. Dynamic Power
Consumption In Large FPGAs
WILLIAM GARCIA,
ANDREW MORTELLARO

2. Literature Survey
L. Shang , A. S. Kaviani and K. Bathala  "Dynamic power
consumption in Virtex-II FPGA family", Proc. ACM/SIGDA 10th Int.
Symp. FPGA,  pp.157 -164 2002

3. Introduction
Recent advances in semiconductor process technology has led to
rapid scaling of transistor dimensions
High density of transistors on the same chip has made power
consumption one of the major challenges of deep submicron IC design
Need to identify utilized logic and routing resources that contribute
to the dynamic power consumption
Goals of the paper:
Better understanding of where power is consumed in FPGAs
Use this understanding to help expert designers reduce or control the
power characteristics of their design

4. Related Work
FPGA-specific power studies lagging behind those of ASIC
Recent studies:
Power distribution of the Xilinx 4000 family
Power dissipation of FPGA interconnection
Manhattan distances between logic blocks
This study
Consideration of state-of-the-art FPGA
Advanced process technology and reduced power supply
More accurate results
Access to detailed schematics of FPGA circuits
Larger circuits tested

5. Background
What is in an FPGA?
Look-Up Tables (LUTs)
Element in Block Ram (BRAM) that represents a simple logic circuit
Combinational logic element
BRAM is indexed by inputs to LUT
Flip-Flops
Sequential logic element
Can be connected to LUT output
Groups of LUT’s and flip-flops called slices
Slices can be combined to form Complex Logic Blocks (CLB’s)
The Routing Matrix
Responsible for connecting CLB’s to rest of FPGA
Consists of switch boxes and multiplexors

6. Virtex-II Family
Legacy Device
Most of the area is utilized by the programmable fabric
Paper focuses solely on fabric power consumption
Each Configurable Logic Block (CLB) contains 4 slices
Each slice contains two LUTS and two FFs
The fabric contains a segmented routing structure
2 CLB (doubles), 6 CLB (Hexes), and cross-chip (Longs)
Two sets of switches at the inputs and outputs of CLBs
Input Crossbar (IXbar) and Output Crossbar (OXbar)

7. Power Consumption
Static Power (caused by leakage current)
Due to subthreshold channel conduction
Very important for large future designs, but only dynamic power is considered here
Subthreshold channel current of a transistor exponentially increases with any Vth decrease
Dynamic Power (caused by signal transitions)
Largest cause is charging/discharging of capacitance
Additional cause is short-circuit power (less than 10%)
Due to switching of inverters in the buffers
Virtex-II power consumption is 5-20% static power
Three main factors of total power dissipation
Effective Capacitance, Resource Utilization, and Switching Activity

8. Effective Capacitance
Power Measurements
Target resource is added to reference circuit to calculate power difference
Linear relationship between frequency and power insures correctness
Spice Simulation
Needed because some resources not easily isolated
Using Cadence and Hspice transistors are simulated from vendor schematics
Results
Found for device 2v1000FG256-5

9. Resource Utilization
Large designs are only used in this case study
The routed design is available in a NCD format
This is used for power estimation
Xilinx tools convert NCD binary to text format
Perl programs convert text format to resource utilization metrics

10. Switching Activity
Most difficult to analyze; dependent on input patterns
Random inputs were mostly used
Two activities contribute to switching activity
Nets
One source and multiple destinations
Logic
Occurs inside the LUT
Modeling is used to calculate switching activity

11. Results (1/2)
Input Stimuli
Next best thing to real input
Large benchmark circuit
90% area of 2V3000 with 14336 slices
Flip-flop count as high as 85% the LUT count
Random Inputs
Restricts the choice of benchmark circuits
Used a set of designs for benchmarking
FIR, FFT filters; DES encryption; multiplier circuits
Utilizes 7790 slices with 13276 LUTs and 2483 flip-flops
Two cases:
Random input supplied every five cycles
Random input supplied every cycle
V = supply voltage
f = operating frequency
Ci = effective capacitance
Ui = utilization
Si = switching activity

12. Results (2/2)
All
High Switching Activity
Switching Activity
Real Input Stimuli Random Input Stimuli

13. Conclusion
Power estimation in FPGAs depend on three factors:
Effective capacitance
Obtained by measurement and SPICE simulations
Resource Utilization
Large reference designs were tested against for a standard analysis
Switching activity
Study considered a variety of input patters for various benchmarks
Shortcomings and Opportunities
Power estimation for newer Virtex devices
Tradeoffs between using large or small designs
More varied or realistic input patterns for switching measurements