EC6612 VLSI Design Lab Manual

VLSI LAB

1. 1
ERODE SENGUNTHAR ENGINEERING COLLEGE
(A pproved by A I C T E - N ew D elhi, P ermanently A ffiliated to A nna U nivers ity – C hennai,
A c c redited by N ational B oard of A c c reditation (N B A ), N ew D elhi and
N ational A s s es s ment & A c c reditation C ounc il (N A A C ), B angalore with ‘A ’ G rade)
Perundurai, Erode – 638 057.


DEPARTMENT OF
ELECTRONICS AND COMMUNICATION
ENGINEERING



ACADEMIC YEAR (2017-2018)





EC6612-VLSI DESIGN LABORATORY



Prepared By

V.THAMIZHARASAN, AP/ECE


EC6612 VLSI DESIGN LAB

2. 2
SYLLABUS

11. HDL based design entry and simulation of simple counters, state machines, adders (min
8 bit) and multipliers (4 bit min).

2. Synthesis, P&R and post P&R simulation of the components simulated in (I) above.
Critical paths and static timing analysis results to be identified. Identify and verify possible
conditions under which the blocks will fail to work correctly.

3. Hardware fusing and testing of each of the blocks simulated in (I). Use of either
chipscope feature (Xilinx) or the signal tap feature (Altera) is a must. Invoke the PLL and
demonstrate the use of the PLL module for clock generation in FPGAs.


IC DESIGN EXPERIMENTS: (BASED ON CADENCE / MENTOR GRAPHICS /
EQUIVALENT)

4. Design and simulation of a simple 5 transistor differential amplifier. Measure gain, ICMR,
and CMRR

5. Layout generation, parasitic extraction and resimulation of the circuit designed in (I)

6. Synthesis and Standard cell based design of an circuits simulated in 1(I) above.
Identification of critical paths, power consumption.

7. For expt (c) above, P&R, power and clock routing, and post P&R simulation.
8. Analysis of results of static timing analysis.





LIST OF EXPRIMENTS

3. 3
CYCLE-I
Using FPGA-SPARTAN3E:
1. Design and implementation of 8-bit adder.
2. Design and implementation of 4*4 array Multiplier.
3. a. Design and implementation of Multiplexer & Demultiplexers.
b. Design and implementation of Encoder & Decoder.
4. a. Design and implementation of 4 bit Ripple Counter.
b. Design and implementation of synchronous 3 bit up/down counter.
5. Design and implementation of FSM.
6. Design and implementation of MAC unit.

CYCLE – II
Using tanner EDA Tool:
7. Design and simulation of CMOS Inverter, NAND & NOR gate.
8. Design and simulation of Differential Amplifier.
9. Design and simulation of Full Adder.
Using MICROWIND Tool:
10. Design Layout of CMOS Inverter, NAND & NOR gate.





Working procedure for Modelsim software

4. 4
1. To open the modelsim5.7g software in desktop. Then editor window will be obtained. In
that window click on filenewproject. Then a create project window will be
displayed.
2. In project window give the project name and location of the project, for example d:/III
ECE. And then click ok. Then add items to the project window will be displayed.
3. In that window click create new file. Create project file will be displayed. In that to give
file name and then click ok.
4. In workspace that file will be displayed with file name. Then open this file. Then type
your HDL code. And then save.
5. Click Toolscompile. Then add to project window will be displayed. In that click yes.
Then compilation will be start.
6. If the compilation was successful then display message compile of file_name.v was
successful. Otherwise error will be displayed. Double click the error and then clear it.
Then repeat the 5
th
step.
7. Then simulatesimulate. Simulate window will be displayed. In that click work (+) to
select a file name and then ok.
8. After simulation click viewsignals. Signals window will be appeared in that select the
input and then edit force. To give the value and then click ok.
9. Then in signals window click add wavesignals in region. Then wave window will
be appear and then click on run button. To verify the output.


Working procedure for Xilinx software

5. 5
1. To open the Xilinx ISE 9.2i.The Xilinx environment will be open .In that environment
consist of source, process and control windows.
2. In that window click on File New project. Then a project create window will be
displayed. In that window it requires details like project name, project location, top level
source type, for source type, choose HDL when verilog or VHDL used. In project
window give the Project Name and then click next button.
3. Then a new project wizard requiring device properties open. In that choose family
[Spartan3E], device [xcs500E], package [FT256], speed [-4or-5].Then click finish.
4. Then click ProjectNew source Verilog modulegive the file name and then click
next.
5. Then new window will be appeared. In that window specifies the input, output &in out
signals and also specifies these are bit type or bit vector type.
6. Then create User constraint file for that go to Project New SourceImplementation
Constraint File.
7. Then go to process window. In that click User constraintsassign package pins.
8. Then new window will be appeared .In that window to assign the pin numbers in the
input and output signals and save it.
9. Double click the synthesis in process window. It will generate the synthesis report
(timing and device utilization summary report).
10. Double click the implement design in process window. It will generate the place and
route report.
11. Double click the generate program file in process window. It will generate the bit file.
12. To switch on the Spartan3E kit and then double click the generate program
fileConfigure Device. A New window will be appeared then click finish button.
13. Then new dialog box will be appeared in that select your bit file (i.e filename.bit).Then
click ok button. Again new dialog box will be appeared then click bypass button.
14. Know your program was downloading to spartan3e kit.
15. After completing download process. Applying the input to the kit and verify the output.

EXPT NO : 1
DATE :

6. 6

8-BIT ADDER
Aim:

To design and implement a 8-bit adder using verilog HDL.

Software/Hardware required:

 Modelsim software
 Xilinx software
 Spartan3e FPGA kit

Algorithm:
1. Start the program.
2. Declare the input and output variables.
3. Half adder:
 Compute sum and carry value using the following equation.
Sum =a ^ b;
Carry=a & b;
Full adder:
 Compute sum and carry value using the following equation.
Sum =a ^r b ^ cin;
Carry=(a & b) | (b & cin) | (cin & a);
Half subtractor:
 Compute difference and borrow value using the following equation.
Difference =a ^ b;
Borrow = (a & b);
Full subtractor:
 Compute difference and borrow value using the following equation.
Difference =a ^ b ^ bin;
Borrow =(~ a & b) |(~ a & bin)| (b & bin);

4. Design a 8 bit adder using full adder as function.
5. Apply the input and verify the output.
6. Stop of the program.


Theory:

Half adder:

A half adder is a logic circuit that
performs an addition operation on two
binary digits. The half adder produces a
sum and carry value which are both
binary digits. The drawback of this circuit
is that in case of a multi bit addition, it
cannot include a carry.


Full adder:

7. 7
A full adder is a logic circuit that
performs an addition operation o n three
binary digits. The fulladder produces a
sum and carry value which is both binary
digits. In full adder sum output will be
taken from X-OR Gate, carry output will
be taken from OR Gate.

HALF SUBTRACTOR:
The half subtractor is constructed
using X-OR and AND Gate. The half
subtractor has two input and two outputs.
The outputs are difference and borrow.
The difference can be applied using X-OR
Gate, borrow output can be implemented
using an AND Gate and an inverter.

FULL SUBTRACTOR:
The full subtractor is a combination
of X-OR, AND, OR, NOT Gates. In a full
subtractor the logic circuit should have
three inputs and two outputs. The two half
subtractor put together gives a full
subtractor .The first half subtractor will be
C and A B. The output will be difference
output of full subtractor. The expression
AB assembles the borrow output of the
half subtractor and the second term is the
inverted difference output of first X-OR.






RIPPLE CARRY ADDER:

8. 8
A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output carry
from each full adder connected to the input carry of next full adder in chain. The augends
bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from right to left,
with subscript 0 denoting the least significant bits. The carries are connected in chain
through the full adder.



TEST BENCH :

Test bench is another verilog code that creates a circuit involving the circuit to be
tested. This code will send different inputs to the code under test and get the output and
displays to check the accuracy.




















Program:

9. 9
HALF ADDER

module ha(a, b, sum, carry);
input a, b;
output sum,carry;
assign carry=a&b;
assign sum=a^b;
endmodule

FULL ADDER

module fulladd(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
assign s=a^b^cin;
assign cout=a&b|b&cin|cin&a;
endmodule

HALF ADDER TEST BENCH

module halfltest;
reg ta,tb;
wire ts,tcout;
ha f1(ta,tb,ts,tcout);
initial
begin
ta=1'b0;
tb=1'b0;
#100
ta=1'b0;
tb=1'b0;
#100
ta=1'b0;
tb=1'b1;
#100
ta=1'b1;
tb=1'b0;
#100
ta=1'b1;
tb=1'b1;
end
endmodule


















FULLADDER TEST BENCH

module fulltest;
reg ta,tb,tcin;
wire ts,tcout;
fulladd f1(ta,tb,tcin,ts,tcout);
initial
begin
ta=1'b0;
tb=1'b0;
tcin=1'b0;
#100
ta=1'b0;
tb=1'b0;
tcin=1'b1;
#100
ta=1'b0;
tb=1'b1;
tcin=1'b0;
#100
ta=1'b0;
tb=1'b1;
tcin=1'b1;
#100
ta=1'b1;
tb=1'b0;
tcin=1'b0;

#100
ta=1'b1;
tb=1'b0;
tcin=1'b1;
#100
ta=1'b1;
tb=1'b1;
tcin=1'b0;
#100
ta=1'b1;
tb=1'b1;
tcin=1'b1;
end
endmodule
HALF SUBTRACTOR

module hasub(a, b, difference, borrow);
input a, b;

10. 10
output difference, borrow;
assign borrow =a&b;
assign difference =a^b;
endmodule
FULL SUBTRACTOR

module fullsub (a,b,cin, diff, borrow);
input a,b,cin;
output diff, borrow;
assign diff=a^b^cin;
assign borrow=~a&b|b&cin|cin&~a;
endmodule


HALF ADDER TEST BENCH

module halfsubtest;
reg ta,tb;
wire tdiff,tborrow;
hasub f1(ta,tb, tdiff,tborrow);
initial
begin
ta=1'b0;
tb=1'b0;
#100
ta=1'b0;
tb=1'b0;
#100
ta=1'b0;
tb=1'b1;
#100
ta=1'b1;
tb=1'b0;
#100
ta=1'b1;
tb=1'b1;
end
endmodule





















FULLADDER TEST BENCH

module fullsubtest;
reg ta,tb,tcin;
wire tdiff,tborrow;
fullsub f1(ta,tb,tcin, tdiff,tborrow);
initial
begin
ta=1'b0;
tb=1'b0;
tcin=1'b0;
#100
ta=1'b0;
tb=1'b0;
tcin=1'b1;
#100
ta=1'b0;
tb=1'b1;
tcin=1'b0;
#100
ta=1'b0;
tb=1'b1;
tcin=1'b1;
#100
ta=1'b1;
tb=1'b0;
tcin=1'b0;

#100
ta=1'b1;
tb=1'b0;
tcin=1'b1;
#100
ta=1'b1;
tb=1'b1;
tcin=1'b0;
#100
ta=1'b1;
tb=1'b1;
tcin=1'b1;
end
endmodule
8-BIT ADDER

module adder8(a,b,s,cout);
input[7:0]a,b;

11. 11
output[7:0]s;
output cout;
wire[6:0]tc;
fulladd a1(a[0],b[0],1'b0,s[0],tc[0]);
fulladd a2(a[1],b[1],tc[0],s[1],tc[1]);
fulladd a3(a[2],b[2],tc[1],s[2],tc[2]);
fulladd a4(a[3],b[3],tc[2],s[3],tc[3]);
fulladd a5(a[4],b[4],tc[3],s[4],tc[4]);
fulladd a6(a[5],b[5],tc[4],s[5],tc[5]);
fulladd a7(a[6],b[6],tc[5],s[6],tc[6]);
fulladd a8(a[7],b[7],tc[6],s[7],cout);
endmodule










8-BIT ADDER TEST BENCH

module add8test;
reg[7:0]ta,tb;
wire[7:0]ts;
wire tcout;
adder8 a1(ta,tb,ts,tcout);
initial
begin
ta=8'b00000011;
tb=8'b00000011;
#100
ta=8'b00000111;
tb=8'b00000011;
#100
ta=8'b00001000;
tb=8'b00000011;
#100
ta=8'b00000011;
tb=8'b00001001;
end
endmodule


























OUTPUT FOR 8 BIT ADDER

12. 12
USER CONSTRAINT FILE:

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "a<0>" LOC = "t14" ;
NET "a<1>" LOC = "t12" ;
NET "a<2>" LOC = "t9" ;
NET "a<3>" LOC = "t7" ;
NET "a<4>" LOC = "t2" ;
NET "a<5>" LOC = "g12" ;
NET "a<6>" LOC = "h1" ;
NET "a<7>" LOC = "r3" ;
NET "b<0>" LOC = "n11" ;
NET "b<1>" LOC = "n3" ;
NET "b<2>" LOC = "m13" ;
NET "b<3>" LOC = "m7" ;
NET "b<4>" LOC = "m3" ;
NET "b<5>" LOC = "k4" ;
NET "b<6>" LOC = "j12" ;
NET "b<7>" LOC = "j11" ;
NET "cout" LOC = "p14" ;
NET "s<0>" LOC = "r1" ;
NET "s<1>" LOC = "r2" ;
NET "s<2>" LOC = "k3" ;
NET "s<3>" LOC = "t4" ;
NET "s<4>" LOC = "t5" ;
NET "s<5>" LOC = "r6" ;
NET "s<6>" LOC = "t8" ;
NET "s<7>" LOC = "r10" ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE















Input/output waveform:

13. 13


Device utilization summary:
---------------------------

Selected Device : 3s500eft256-4

Number of Slices: 9 out of 4656 0%
Number of 4 input LUTs: 15 out of 9312 0%
Number of IOs: 25
Number of bonded IOBs: 25 out of 190 13%


Timing Summary:
---------------
Speed Grade: -4

Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 13.616ns



















RESULT

Thus the program for 8-bit Adder was implemented using spartan3e FPGA kit.

14. 14
EXPT NO : 2
DATE :

ARRAY MULTIPLIER
Aim:
To design and implement an 4*4 array multiplier using verilog HDL.

Software/Hardware required:

 Modelsim software
 Xilinx software
 Spartan3e FPGA kit
Algorithm:
1. Start the program.
2. Declare the input and output variables.
3. Design and gate & full adder.
4. Design multiplier using and gate and full adder as component. (Refer
block diagram).
5. Apply the input and verify the outputs.
6. Stop the program.

Theory:
An array multiplier is a digital combinational circuit that is used for the multiplication of
two binary numbers by employing an array of full adders and half adders. This array is used
for the nearly simultaneous addition of the v arious product terms involved. To form the
various product terms, an array of AND gates is used before the Adder array.
To clarify more on the concept, let us take the example of a 2X2 bit multiplication with
A and B being the multiplicand and the multiplier respectively. Assuming A = a(1)a(0) and
B= b(1)b(0), the various bits of the final product term P can be written as:-
P (0) = a (0) b (0)
P (1)=a(1)b(0) + b(1)a(0)
P(2) = a(1)b(1) + C1 where C1 is the carry generated during the addition for the P(1)
term.
P(3)=C2 where C2 is the carry generated during the addition for the P(2) term.
For the above multiplication, an array of four AND gates is required to form the various
product terms like a(0)b(0) etc. and then an Adder array is required to calculate the sums

15. 15
involving the various product terms and carry combinations mentioned in the above
equations in order to get the final Product bits.
The Hardware requirement for an m x n bit array multiplier is given as:-
(m x n) number of AND gates, (m -1).n number of Adders containing at least (m -2).n
full adders. The rest n can be either half adders or full adders used with the input carry kept
at 0.

16. 16
Program:
module mul4(a,b,p);
input[3:0]a,b;
output[7:0]p;
wire[15:1]c;
wire[10:0]q;
wire[6:1]s;
andf a0(a[0],b[0],p[0]);
andf a1(a[1],b[0],c[1]);
andf a2(a[2],b[0],c[2]);
andf a3(a[3],b[0],c[3]);

andf a4(a[0],b[1],c[4]);
andf a5(a[1],b[1],c[5]);
andf a6(a[2],b[1],c[6]);
andf a7(a[3],b[1],c[7]);

andf a8(a[0],b[2],c[8]);
andf a9(a[1],b[2],c[9]);
andf a10(a[2],b[2],c[10]);
andf a11(a[3],b[2],c[11]);

andf a12(a[0],b[3],c[12]);
andf a13(a[1],b[3],c[13]);
andf a14(a[2],b[3],c[14]);
andf a15(a[3],b[3],c[15]);

fulladd f0(c[1],c[4],1'b0,p[1],q[0]);
fulladd f1(q[0],c[2],c[5],s[1],q[1]);
fulladd f2(q[1],c[3],c[6],s[2],q[2]);
fulladd f3(q[2],1'b0,c[7],s[3],q[3]);
fulladd f4(s[1],1'b0,c[8],p[2],q[4]);
fulladd f5(q[4],s[2],c[9],s[4],q[5]);
fulladd f6(q[5],s[3],c[10],s[5],q[6]);
fulladd f7(q[6],q[3],c[11],s[6],q[7]);
fulladd f8(s[4],1'b0,c[12],p[3],q[8]);
fulladd f9(q[8],s[5],c[13],p[4],q[9]);
fulladd f10(q[9],s[6],c[14],p[5],q[10]);
fulladd f11(q[10],q[7],c[15],p[6],p[7]);
endmodule
Test Bench
module multest;
reg[3:0]ta,tb;
wire[7:0]tp;
mul4 m1(ta,tb,tp);
initial
begin
ta=4'b0011;
tb=4'b0011;
#100
ta=4'b0111;
tb=4'b0011;
#100
ta=4'b1000;
tb=4'b0011;
#100
ta=4'b0011;
tb=4'b1001;
end
endmodule

17. 17
OUTPUT FOR MULTIPLIER

USER CONSTRAINT FILE:
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "a<0>" LOC = "t14" ;
NET "a<1>" LOC = "t12" ;
NET "a<2>" LOC = "t9" ;
NET "a<3>" LOC = "t7" ;
NET "b<0>" LOC = "m3" ;
NET "b<1>" LOC = "k4" ;
NET "b<2>" LOC = "j12" ;
NET "b<3>" LOC = "j11" ;
NET "p<0>" LOC = "r1" ;
NET "p<1>" LOC = "r2" ;
NET "p<2>" LOC = "k3" ;
NET "p<3>" LOC = "t4" ;
NET "p<4>" LOC = "t5" ;
NET "p<5>" LOC = "r6" ;
NET "p<6>" LOC = "t8" ;
NET "p<7>" LOC = "r10" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE

Input/output wave form:

18. 18

Device utilization summary:
---------------------------
Selected Device : 3s500eft256-4
Number of Slices: 16 out of 4656 0%
Number of 4 input LUTs: 28 out of 9312 0%
Number of IOs: 16
Number of bonded IOBs: 16 out of 190 8%

Timing Summ ary:
---------------
Speed Grade: -4

Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 15.272ns
























RESULT:
Thus the program for 4*4 array multiplier was implemented using spatan3e FPGA.

19. 19
EXPT NO : 3a
DATE :
MULTIPLEXER & DEMULTIPLEXERS
Aim:
To Design and implement a Multiplexer & Demultiplexers using verilog HDL.
Software/Hardware required:

 Modelsim software
 Xilinx software
 Spartan3e FPGA kit
Algorithm:
1. Start the program.
2. Declare the input and output variables.
3. Multiplexer:
Compute output using
y = (~ so & ~ s1 & do) | (~ so & s1 & d1) | (so & ~ s1 & d2) | (so & s1 &
d3); this equation or if selection is “00” ,”01”,”10”,”11” means output is
1
st
,2
nd
,3
rd
,and 4
th
data respectively.
Demultiplexer:
Compute output using following equation
out0<= (~ s0) & (~ s1) & din;
out1<= (~ s0) & s1 & din;
out2<=s0 & (~ s1) & din;
out3<=s0 & s1 & din; this equation or
if selection is “00”,”01”,”10”,”11” means output is d0=din,
d1=din, d2=din, and d3=din respectively.
4. Apply the input and verify the outputs.
5. Stop the program.
THEORY:
MULTIPLEXER:
Multiplexer is transmitting a large
number of information units over a
smaller number of channels or lines. A
digital multiplexer is a combinational
circuit that selects binary information from
one of many input lines and directs it to a
single output line. The selection of a
particular input line is controlled by a set
of selection lines. Normally there are 2
n

input line and n selection lines whose bit
combination determine which input is
selected.

20. 20
DEMULTIPLEXER:
The function of Demultiplexer is in
contrast to multiplexer function. It takes
information from one line and distributes
it to a given number of output lines. For
this reason, the Demultiplexer is also
known as a data distributor. Decoder can
also be used as Demultiplexer.
In the 1: 4 Demultiplexer circuit,
the data input line goes to all of the AND
gates. The data select lines enable only
one gate at a time and the data on the
data input line will pass through the
selected gate to the associated data
output line.


PROGRAMS :

MUX

module mux(dout,d0,d1,d2,d3,s0,s1);
input d0,d1,d2,d3;
input s0,s1;
output dout;
reg dout;
always @(d0 or d1 or d2 or d3 or s0 or
s1)
begin
case({s1,s0})
2'd0:dout=d0;
2'd1:dout=d1;
2'd2:dout=d2;
2'd3:dout=d3;
endcase
end
endmodule












DEMUX

module dmux(din,d0,d1,d2,d3,s0,s1);
output d0,d1,d2,d3;
input din,s0,s1;
reg d0,d1,d2,d3;
always @(din or s0 or s1)
begin
if (s0==1'b0 && s1==1'b0)
begin
d0=din;
d1=1'b0;d2=1'b0;d3=1'b0;
end
else if(s0==1'b0 && s1==1'b1)
begin
d1=din;d0=1'b0;d2=1'b0;d3=1'b0;
end
else if(s0==1'b1 && s1==1'b0)
begin
d2=din;d0=1'b0;d1=1'b0;d3=1'b0;
end
else
begin
d3=din;
d0=1'b0;d1=1'b0;d2=1'b0;
end
end
endmodule
OUTPUT FOR MULTIPLEXER

21. 21

USER CONSTRAINT FILE:

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "d0" LOC = "t14" ;
NET "d1" LOC = "t12" ;
NET "d2" LOC = "t9" ;
NET "d3" LOC = "t7" ;
NET "dout" LOC = "r1" ;
NET "s0" LOC = "j12" ;
NET "s1" LOC = "j11" ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE

Input/output wave form:



Device utilization summary:
---------------------------

Selected Device : 3s500eft256-4

Number of Slices: 1 out of 4656 0%
Number of 4 input LUTs: 2 out of 9312 0%
Number of IOs: 7
Number of bonded IOBs: 7 out of 190 3%

Timing Summary:
---------------
Speed Grade: -4

Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 6.557ns

OUTPUT FOR DEMULTIPLEXER

22. 22
USER CONSTRAINT FILE:
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "d0" LOC = "r1" ;
NET "d1" LOC = "r2" ;
NET "d2" LOC = "k3" ;
NET "d3" LOC = "t4" ;
NET "din" LOC = "t14" ;
NET "s0" LOC = "j12" ;
NET "s1" LOC = "j11" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
Input/output wave form:



Device utilization summary:
---------------------------
Selected Device : 3s500eft256-4
Number of Slices: 2 out of 4656 0%
Number of 4 input LUTs: 4 out of 9312 0%
Number of IOs: 7
Number of bonded IOBs: 7 out of 190 3%

Timing Summary:
---------------
Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 6.376ns


RESULT:
Thus the programs for multiplexer & Demultiplexers was implemented using Spartan3e
FPGA kit.

23. 23
EXPT NO : 3b
DATE :
ENCODER & DECODER
Aim:
To Design and implement a encoder & decoder using verilog HDL.
Software/Hardware required:

 Modelsim software
 Xilinx software
 Spartan3e FPGA kit
Algorithm:
1. Start the program.
2. Declare the input and output variables.
3. Encoder:
Compute output using following equation
Out(0)<=din(4) | din(5) | din(6) | din(7);
Out(1)<=din(2) | din(3) | din(6)| din(7);
Out(2)<=din(1) | din(3) | din(5) | din(7); this equation or if “din” is
“00000001” ,” 00000010”,” 00000100”,” 00001000” “00010000” ,”
00100000”,” 01000000”,” 10000000” means output out is
“000”,”001”,”010”,”011”,”100”,”101”,”110”,”111” respectively.
Decoder:
Compute output using following equation
d0<=(~ s0) & (~ s1) & en;
d1<=(~ s0) & s1 & en;
d2<=s0 & (~ s1) & en;
d3<=s0 & s1 & en; using this equation or if enable is”0” then output “0”
otherwise if selection is “00”,”01”,”10”,”11” means output is d0=1, d1=1,
d2=1, and d3=1 respectively.
4. Apply the input and verify the outputs.
5. Stop the program.

ENCODER:
An encoder is digital circuits that
perform inverse operation of a decoder.
An encoder has 2
n
input lines and n output
lines. In encoder the output lines
generates the binary code corresponding
to the input value. In octal to binary
encoder it has eight inputs, one for each
octal digit and three output that generate
the corresponding binary code. In encoder
it is assumed that only one input has a
value of one at any given time otherwise
the circuit is meaningless. It has an
ambiguity that when all inputs are zero
the outputs are zero. The zero outputs can
also be generated when D0 = 1.

24. 24
DECODER:
A decoder is a multiple input
multiple output logic circuit which converts
coded input into coded output where input
and output codes are different. The input
code generally has fewer bits than the output
code. Each input code word produces a
different output code word i.e. there is one
to one mapping can be expressed in truth
table. In the block diagram of decoder
circuit the encoded information is present as
n input producing 2
n
possible outputs. 2
n

output values are from 0 through out 2
n
– 1.

Programs:
Encoder:
module encoder(din,dout);
input[7:0]din;
output[2:0]dout;
reg[2:0]dout;
always @(din)
begin
case(din)
8'b00000000:dout =3'b000;
8'b00000001:dout =3'b000;
8'b00000010:dout =3'b001;
8'b00000100:dout =3'b010;
8'b00001000:dout =3'b011;
8'b00010000:dout =3'b100;
8'b00100000:dout =3'b101;
8'b01000000:dout =3'b110;
8'b10000000:dout =3'b111;
endcase
end
endmodule








Decoder:
module decoder(en,d0,d1,d2,d3,s0,s1);
output d0,d1,d2,d3;
input en,s0,s1;
reg d0,d1,d2,d3;
always @(en or s0 or s1)
begin
if(en==1'b0)begin
d0=1'b0;d1=1'b0;d2=1'b0;d3=1'b0;
end
else
if (s0==1'b0 && s1==1'b0)
begin
d0=1'b1;d1=1'b0;d2=1'b0;d3=1'b0;
end
else if(s0==1'b0 && s1==1'b1)
begin
d1=1'b1;d0=1'b0;d2=1'b0;d3=1'b0;
end
else if(s0==1'b1 && s1==1'b0)
begin
d2=1'b1;d0=1'b0;d1=1'b0;d3=1'b0;
end
else
begin
d3=1'b1;d0=1'b0;d1=1'b0;d2=1'b0;
end
end
endmodule

25. 25

OUTPUT FOR ENCODER

USER CONSTRAINT FILE:

#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "din<0>" LOC = "t14" ;
NET "din<1>" LOC = "t12" ;
NET "din<2>" LOC = "t9" ;
NET "din<3>" LOC = "t7" ;
NET "din<4>" LOC = "t2" ;
NET "din<5>" LOC = "g12" ;
NET "din<6>" LOC = "h1" ;
NET "din<7>" LOC = "r3" ;
NET "dout<0>" LOC = "r1" ;
NET "dout<1>" LOC = "r2" ;
NET "dout<2>" LOC = "k3" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE

Input/output waveform:




Device utilization summary:
---------------------------
Selected Device : 3s500eft256-4
Number of Slices: 8 out of 4656 0%
Number of 4 input LUTs: 14 out of 9312 0%
Number of IOs: 11
Number of bonded IOBs: 11 out of 190 5%
IOB Flip Flops: 3


Timing Summary:
---------------
Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: 4.318ns
Maximum output required time after clock: 4.368ns
Maximum combinational path delay: No path found

26. 26
OUTPUT FOR DECODER

User constraint file:

#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "d0" LOC = "r1" ;
NET "d1" LOC = "r2" ;
NET "d2" LOC = "k3" ;
NET "d3" LOC = "t4" ;
NET "en" LOC = "t14" ;
NET "s0" LOC = "j12" ;
NET "s1" LOC = "j11" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
Input/output waveform:



Device utilization summary:
---------------------------
Selected Device : 3s500eft256-4
Number of Slices: 2 out of 4656 0%
Number of 4 input LUTs: 4 out of 9312 0%
Number of IOs: 7
Number of bonded IOBs: 7 out of 190 3%

Timing Summary:
---------------
Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 6.376ns



Result:

Thus the program for encoder and decoder was implemented using Spartan3e FPGA kit.

27. 27
EXPT NO : 4a
DATE :

4BIT RIPPLE COUNTER
Aim:

Design and implement a 4bit ripple counter using Verilog HDL.

Software/Hardware required:

 Modelsim software
 Xilinx software
 Spartan3e FPGA kit

Algorithm:
1. Start the program.
2. Declare the input and output variables.
3. Design each flip flop using following equation:
D flip flop: Qn+1=D
SR flip flop: Qn+1=S+R’Q
JK flip flop: Qn+1=JQn’+K’Qn
T flip flop: Qn+1=TQn’+T’Qn
4. Design 4-bit ripple counter using JK Flip flop as component.(Refer Below
Mention Diagram)
5. Apply the input and verify the outputs.
6. Stop the program.

Theory:
Latch: They are sensitive to the duration of pulse and can transfer data until they are switched
on. They hold the last logic at the output if we put it off(bring the strobe pin to low). They are
used as temporary buffers.

FF: They are sensitive to signal change (low to high or high to low) and not the level. Hence
they transfer data only at that instant and it cannot be changed until next signal change. Due to
this they are used as registers.
The D flip-flop tracks the input, making transitions with match those of the input D. The
D stands for "data"; this flip-flop stores the value that is on the data line. It can be thought of as a
basic memory cell. A D flip-flop can be made from a set/reset flip-flop by tying the set to the
reset through an inverter. The result may be clocked.
The T or "toggle" flip-flop changes its output on each clock edge, giving an output
which is half the frequency of the signal to the T input It is useful for constructing binary
counters, frequency dividers, and general binary addition devices. It can be made from a J-K flip-
flop by tying both of its inputs high.

28. 28
The J-K flip-flop is the most versatile of the basic flip-flops. It has the input- following
character of the clocked but has two inputs, traditionally labeled J and K. If J and K are different
then the output Q takes the value of J at the next clock edge. If J and K are both low then no
change occurs. If J and K both are high at the clock edge then the output will toggle from one
state to the other. It can perform the functions of the set/reset flip-flop and has the advantage that
there are no ambiguous states. It can also act as a T flip-flop to accomplish toggling action if J
and K are tied together. This toggle application finds extensive use in binary counters.
An SR (Set/Reset) flip-flop is perhaps the simplest flip-flop, and is very similar to the SR
latch, other than for the fact that it only transitions on clock edges. While as theoretically valid as
any flip-flop, synchronous edge-triggered SR flip-flops are extremely common because they
retain the illegal state when both S and R are asserted. Generally when people refer to SR flip-
flops, they mean SR latches. While the S and R inputs are both low, feedback maintains the Q
and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R
(Reset) is held low, then the Q output is forced high, and stays high when S returns to low;
similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low
when R returns to low.
S.NO TYPE OF
FLIP FLOP
TRUTH TABLE
1 SR
S R Qn+1 Equation
0 0 Qn
Qn+1=S+R’Q
0 1 0
1 0 1
1 1 Indeterminate state
2 JK
J K Qn+1 Equation
0 0 Qn
Qn+1=JQn’+K’Qn
0 1 0
1 0 1
1 1 Qn’
3 D
D Qn+1 Equation
0 0
Qn+1=D
1 1
4 T
T Qn+1 Equation
0 Qn
Qn+1=TQn’+T’Qn
1 Qn’

29. 29
Counter:
A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. A specified sequence of states
appears as counter output. This is the main difference between a register and a counter. There are
two types of counter, synchronous and asynchronous. In synchronous common clock is given to
all flip flop and in asynchronous first flip flop is clocked by external pulse and then each
successive flip flop is clocked by Q or Q output of previous stage. A soon the clock of second
stage is triggered by output of first stage. Because of inherent propagation delay time all flip
flops are not activated at same time which results in asynchronous operation. An up/down
counter is one that is capable of progressing in increasing order or decreasing order through a
certain sequence. An up/down counter is also called bidirectional counter. Usually up/down
operation of the counter is controlled by up/down signal. When this signal is high counter goes
through up sequence and when up/down signal is low counter follows reverse sequence.

4-bit ripple counter

30. 30
Program:
RIPPLE COUNTER

module ripplecounter(q,clk,rst);
input rst,clk;
output[0:3]q;
reg clkd;
integer count;
parameter a=100000000;
initial
begin
clkd=1'b0;
count=0;
end
always @(posedge clk)
begin
count=count+1;
if(count==a)
begin
count=0;
clkd=~clkd;
end
end
jk j0(q[3],1'b1,1'b1,clkd,rst);
jk j1(q[2],1'b1,1'b1,q[3],rst);
jk j2(q[1],1'b1,1'b1,q[2],rst);
jk j3(q[0],1'b1,1'b1,q[1],rst);
endmodule

module jk(q,j,k,clk,rst);
input j,k,clk,rst;
output q;
reg q;
always @(negedge clk,negedge rst)
begin
if(rst==0)
q=1'b0;
else
if(j==1'b0&&k==1'b0)
q=q;
else
if(j==1'b0&&k==1'b1)
q=1'b0;
else
if(j==1'b1&&k==1'b0)
q=1'b1;
else
if(j==1'b1&&k==1'b1)
q=~q;
end
endmodule

31. 31
OUTPUT FOR RIPPLE COUNTER
User constraint file:

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "clk" LOC = "a8" ;
NET "q<0>" LOC = "r1" ;
NET "q<1>" LOC = "r2" ;
NET "q<2>" LOC = "k3" ;
NET "q<3>" LOC = "t4" ;
NET "rst" LOC = "j6" ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE

Input/output waveform:


Device utilization summary:
---------------------------

Selected Device : 3s500eft256-5

Number of Slices: 46 out of 4656 0%
Number of Slice Flip Flops: 37 out of 9312 0%
Number of 4 input LUTs: 78 out of 9312 0%
Number of IOs: 6
Number of bonded IOBs: 6 out of 190 3%
Number of GCLKs: 1 out of 24 4%

Timing Summary:
---------------
Speed Grade: -5

Minimum period: 7.763ns (Maximum Frequency: 128.823MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 4.134ns
Maximum combinational path delay: No path found





RESULT:
Thus the program for 4 bit ripple counter was implemented using spartan3e FPGA kit.

32. 32
EXPT NO : 4b
DATE :

3BIT SYNCHRONOUS UP/DOWN COUNTER
Aim:

Design and implement a 3 bit up/down counter using Verilog HDL.

Software/Hardware required:

 Modelsim software
 Xilinx software
 Spartan3e FPGA kit

Algorithm:
1. Start the program.
2. Declare the input and output variables.
3. Design JK flip flop using following equation:
JK flip flop: Qn+1=JQn’+K’Qn or if input(JK) is 00,01,10,11 means the
output was q(n+1)&q0(n+1) is q,10,01,~q respectively
4. Design and gate using c= a & b this equation.
5. Design and gate using c= a & b this equation.
6. Design 3-bit up/down counter using JK Flip flop as component.(Refer Below
Mention Diagram)
7. Apply the input and verify the outputs.
8. Stop the program.

33. 33
Theory:

The circuit above is of a simple 3 -bit Up/Down synchronous counter using JK flip-flops
configured to operate as toggle or T-type flip-flops giving a maximum count of zero (000) to
seven (111) and back to zero again. Then the 3 -Bit counter advances upward in sequence
(0,1,2,3,4,5,6,7) or downwards in reverse sequence (7,6, 5,4,3,2,1,0) but generally,
bidirectional counters can be made to change their count direction at any point in the
counting sequence. An additional input determines the direction of the count, either Up or
Down and the timing diagram gives an example of th e counters operation as this Up/Down
input changes state.
Nowadays, both up and down counters are incorporated into single IC that is fully
programmable to count in both an "Up" and a "Down" direction from any preset value
producing a complete Bidirectional Counter chip.

34. 34
Program:
module updown(uc,dc,clk,rst,out1);
input uc,dc,clk,rst;
output[2:0]out1;
wire
q0,qn0,x1,x2,x3,q1,qn1,x4,x5,x6,q2,qn2;
reg clkd;
integer count;
parameter a=100000000;
initial
begin
clkd=1'b0;
count=0;
end
always @(posedge clk)
begin
count=count+1;
if(count==a)
begin
count=0;
clkd=~clkd;
end
end
jkupdown f1(q0,qn0,1'b1,1'b1,clkd,rst);
and a1(x1,uc,q0);
and a2(x2,dc,qn0);
or o1(x3,x1,x2);
jkupdown f2(q1,qn1,x3,x3,clkd,rst);
and a3(x4,uc,q1,q0);
and a4(x5,dc,qn1,qn0);
or o2(x6,x4,x5);
jkupdown f3(q2,qn2,x6,x6,clkd,rst);
assign out1={q2,q1,q0};
endmodule


















module andf(a,b,c);
input a,b;
output c;
assign c=a &b;
endmodule


module orf(a,b,c);
input a,b;
output c;
assign c=a | b;
endmodule


module jkupdown(q,q0,j,k,clk,rst);
input j,k,clk,rst;
output q,q0;
reg q,q0;
initial q=1'b0;
always @( negedge clk,negedge rst)
begin
if(rst==0)
begin
q=1'b0;
q0=1'b1;
end
else
if(j==1'b0&&k==1'b0)
begin
q=q;
q0=q0;
end
else
if(j==1'b0&&k==1'b1)
begin
q=1'b0;
q0=1'b1;
end
else
if(j==1'b1&&k==1'b0)
begin
q=1'b1;
q0=1'b0;
end
else
if(j==1'b1&&k==1'b1)
begin
q=~q;q0=~q0;
end
end
endmodule

35. 35
OUTPUT FOR 3 BIT SYNCHRONOUS UP DOWN COUNTER

User constraint file
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "clk" LOC = "a8" ;
NET "dc" LOC = "t14" ;
NET "out1[0]" LOC = "r1" ;
NET "out1[1]" LOC = "r2" ;
NET "out1[2]" LOC = "k3" ;
NET "rst" LOC = "j6" ;
NET "uc" LOC = "j11" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE

Input/output wave form:


Device utilization summary:
---------------------------
Selected Device : 3s500eft256-4

Number of Slices: 49 out of 4656 1%
Number of Slice Flip Flops: 38 out of 9312 0%
Number of 4 input LUTs: 82 out of 9312 0%
Number of IOs: 7
Number of bonded IOBs: 7 out of 190 3%
Number of GCLKs: 1 out of 24 4%
Timing Summary:
---------------
Speed Grade: -4
Minimum period: 8.965ns (Maximum Frequency: 111.5 51MHz)
Minimum input arrival time before clock: 4.678ns
Maximum output required time after clock: 4.450ns
Maximum combinational path delay: No path found

RESULT:
Thus the program for 3 bit up/down synchronous counter was implemented using
spartan3e FPGA kit.

36. 36
EXPT NO : 5
DATE :

SEQUENCE DETECTOR USING FINITE STATE MACHINE (FSM)
Aim:

Design and implement a Sequence Detector using Finite State Machine.

Software/Hardware required:

 Modelsim software
 Xilinx software
 Spartan3e FPGA kit
Algorithm:
1. Start the program.
2. Declare the input and output variables.
3. Check the rst input using if statement. If rst=1 means assign state as a initial
state ‘a ‘.otherwise state as a next state.
4. Check the state by using case statement
5. To check the each state by using if statement .If the state ‘a’ then to check
input ‘x’. Then assign respective next state and output for each case of input.
6. Repeat the step 5 for all the state.
7. Apply the input and verify the outputs.
8. Stop the program.
THEORY:

We now do the 11011 sequence detector as an example. We begin with the formal
problem statement, repeat the design rules, and then apply them. A sequence detector accepts as
input a string of bits: either 0 or 1. Its output goes to 1 when a target sequence has been
detected. There are two basic types: overlap and non-overlap. In a sequence detector that
allows overlap, the final bits of one sequence can be the start of another sequence. Our example
will be a 11011 sequence detector. It raises an output of 1 when the last 5 binary bits received
are 11011. At this point, a detector with overlap will allow the last two 1 bits to serve at the first
of a next sequence. By example we show the difference between the two detectors. Suppose an
input string 11011011011.

11011 detector with overlap X 11011011011
Z 00001001001
11011 detector with no overlap Z 00001000001
The sequence detector with no overlap allowed resets itself to the start state when the sequence
has been detected. Write the input sequence as 11011 011011. After the initial sequence 11011
has been detected, the detector with no overlap resets and starts searching for the initial 1 of the
next sequence. The detector with overlap allowed begins with the final 11 of the previous
sequence as ready to be applied as the first 11 of the next sequence; the next bit it is looking for
is the 0.

37. 37
Program:
module sm(z,ns,clk,rst,x);
output z,ns;
reg z;
input x,clk,rst;
parameter a=3'b000;
parameter b=3'b001;
parameter c=3'b010;
parameter d=3'b011;
parameter e=3'b100;
reg[2:0]s;
reg[2:0]ns;
always@(posedge clk)
begin
if(rst)
s<=a;
else
s<=ns;
end
always@(s,x)
begin
case(s)
a:if(x)
begin
ns<=b;
z<=1'b0;
end
else if(x==1'b0)
begin
ns<=a;
z<=1'b0;
end
b:if(x)
begin
ns<=b;
z<=1'b0;
end


else if(x==1'b0)
begin
ns<=c;
z<=1'b0;
end
c:if(x)
begin
ns<=b;
z<=1'b0;
end
else if(x==1'b0)
begin
ns<=d;
z<=1'b0;
end
d:if(x)
begin
ns<=b;
z<=1'b0;
end
else if(x==1'b0)
begin
ns<=e;
z<=1'b0;
end
e:if(x)
begin
ns<=b;
z<=1'b1;
end
else if(x==1'b0)
begin
ns<=a;
z<=1'b0;
end
endcase
end
endmodule

38. 38
OUTPUT FOR SEQUENCE GENERATOR

User constraint file:

#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "clk" LOC = "a8" ;
NET "ns[0]” LOC = "r1" ;
NET "ns[0]” LOC = "r2" ;
NET "rst" LOC = "j6" ;
NET "x" LOC = "t14" ;
NET "z" LOC = "k3" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
Input/output waveform:


Device utilization summary:
---------------------------
Selected Device : 3s500eft256-4

Number of Slices: 48 out of 4656 1%
Number of Slice Flip Flops: 37 out of 9312 0%
Number of 4 input LUTs: 75 out of 9312 0%
Number of IOs: 6
Number of bonded IOBs: 6 out of 190 3%
Number of GCLKs: 1 out of 24 4%


Timing Summary:
---------------
Speed Grade: -4

Minimum period: 8.965ns (Maximum Frequency: 111.551MHz)
Minimum input arrival time before clock: 3.840ns
Maximum output required time after clock: 4.394ns
Maximum combinational path delay: No path found






RESULT:
Thus the Sequence Detector using Finite State Machine was implemented using
spartan3e FPGA kit.

39. 39
EXPT NO : 6
DATE :

Accumulator
Aim:
Design and implement a accumulator using Verilog HDL.

Software/Hardware required:

 Modelsim software
 Xilinx software
 Spartan3e FPGA kit
Algorithm:

1. Start the program.
2. Declare the input and output variables.
3. Initialize the accumulator content (i.e accin=0).
4. Multiply the two inputs and then add to accumulator content and then stored
to accumulator.
5. Repeat the step 4 continuously.
6. Apply the input and verify the outputs.
7. Stop the program.
Theory:
In computing, especially digital signal processing, the multiply–accumulate operation is a
common step that computes the product of two numbers and adds that product t o
an accumulator. The hardware unit that performs the operation is known as a multiplier–
accumulator (MAC, or MAC unit); the operation itself is also often called a MAC or a MAC
operation. The MAC operation modifies an accumulator a:

When done with floating point numbers, it might be performed with two roundings (typical in
many DSPs), or with a single rounding. When performed with a single rounding, it is called
a fused multiply–add (FMA) or fused multiply–accumulate (FMAC).
Modern computers may contain a dedicated MAC, consisting of a multiplier implemented
in combinational logic followed by an adder and an accumulator register that stores the
result. The output of the register is fed back to one input of the adder, so that on each clock
cycle, the output of the multiplier is added to the register. Combinational multipliers require
a large amount of logic, but can compute a product much more quickly than the method of
shifting and adding typical of earlier computers. The first processors to be equipped with
MAC units were digital signal processors, but the technique is now also common in general -
purpose processors.

40. 40
Program:
module mac(account,ov,x,y,clk,rst);
input[3:0]x,y;
input clk,rst;
output ov;
output[8:0]account;
reg ov,clkd;
integer count;
reg[8:0]accin;
parameter a=200000000;
initial
begin
clkd=1'b0;
count=0;
end
always @(posedge clk)
begin
count=count+1;
if(count==a)
begin
count=0;
clkd=~clkd;
end
end
always@(posedge clkd)
begin
if(rst==0)
begin
accin=9'b000000000;
ov=1'b0;
end
else
accin=(x*y)+accin;
if(accin[8])
ov=1'b1;
end
assign account=accin;
endmodule

41. 41
OUTPUT FOR MAC UNIT
USER CONSTRAINT FILE:
#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "account<0>" LOC = "r1" ;
NET "account<1>" LOC = "r2" ;
NET "account<2>" LOC = "k3" ;
NET "account<3>" LOC = "t4" ;
NET "account<4>" LOC = "t5" ;
NET "account<5>" LOC = "r6" ;
NET "account<6>" LOC = "t8" ;
NET "account<7>" LOC = "r10" ;
NET "account<8>" LOC = "n10" ;
NET "clk" LOC = "a8" ;
NET "ov" LOC = "p14" ;
NET "rst" LOC = "j6" ;
NET "x<0>" LOC = "t14" ;
NET "x<1>" LOC = "t12" ;
NET "x<2>" LOC = "t9" ;
NET "x<3>" LOC = "t7" ;
NET "y<0>" LOC = "j11" ;
NET "y<1>" LOC = "j12" ;
NET "y<2>" LOC = "k4" ;
NET "y<3>" LOC = "m3" ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE

Input/output waveform:

42. 42
Device utilization summary:
---------------------------

Selected Device : 3s500eft256-4

Number of Slices: 52 out of 4656 1%
Number of Slice Flip Flops: 43 out of 9312 0%
Number of 4 input LUTs: 84 out of 9312 0%
Number of IOs: 20
Number of bonded IOBs: 20 out of 190 10%
Number of MULT18X18SIOs: 1 out of 20 5%
Number of GCLKs: 1 out of 24 4%

Timing Summary:
---------------
Speed Grade: -4

Minimum period: 8.965ns (Maximum Frequency: 111.551MHz)
Minimum input arrival time before clock: 11.110ns
Maximum output required time after clock: 4.310ns
Maximum combinational path delay: No path found




























RESULT:
Thus the program for MAC unit was implemented using spartan3e FPGA kit.

43. 43
TANNER EDA
Tanner EDA is a leading provider of Electronic Design Automation (EDA) software
solutions for the design, layout and verification of Analog/Mixed signal ICs and MEMS. This
tool helps to automate and simplify the design process, enabling engineers to cost-effectively
bring out commercially successful electronic products to the market ahead of competition.
Tanner EDA’s innovative solutions are used in a range of applications in next generation
wireless, consumer electronics, imaging, power management, biomedical, automotive and RF
market segments. Tanner EDA tools are used by more than 25,000 for Analog/Mixed signal ICs
and MEMS devices. Customers such as Catalyst Semiconductor, Honeywell, Jet propulsion
Laboratory, NEC, Ricoh Company Ltd., Sarnoff Corporation, Xerox Corporation and others rely
on these tools to help them speed from concept to silicon efficiently. Some of the products
designed with Tanner EDA include imaging technology for the Mars Rover, components for
Bluetooth peripherals and thermal management sensors for cell phones and notebook PCs.
Tanner’s fully integrated solutions consist of tools for schematic entry, circuit simulation,
waveform probing, full-custom layout editing, placement and routing, net list extraction, LVS
and DRC verification. It delivers smooth efficient design flow from schematic to simulation
waveform viewing.
5.1.1 T-Spice
T-Spice offers options and commands not found in Berkely SPICE or most derivatives,
such as design optimization, Monte Carlo analysis, multi dimensional parameters, or source and
temperature sweeping. Tightly integrated with Tanner EDA’s S-Edit schematic capture tool, T-
Spice provide state-of-the-art analog design environment at an affordable price.
5.1.2 S-Edit
S-Edit, Tanner EDA’s schematic capture tool, has been completely re-architected and
rebuilt into a new tool with user interface, performance and interoperability enhancements added.
Ability to probe element and sub-circuit terminal currents and charges. S-Edit uses the Tool
Control Language (TCL) scripting language, which makes it fully expandable, as well as
enabling easy modifications of current designs. Integrated productivity tools such as Design
Checker and Library Browser, plus multiple libraries and language support for English, Chinese,
Russian and Japanese, all combine to deliver a comprehensive and interactive design
environment. S-Edit supports integrated analog simulation with automatic conversion from

44. 44
Cadence
®
and View Draw
®
schematics. Users can run simulations and to probe a node from S-
Edit, making the design process real-time and more efficient. The ability to view operating point
simulation results directly on the schematic entry is another S-Edit productivity enhancing
feature.
5.1.3 L-Edit
Designs created in S-Edit, or other schematic capture tools, can proceed to L-Edit for
layout, place and route, and verification. L-Edit performs the physical design with design rules
calibrated to the requirements of the chip design and the foundry where the chips will be
manufactured. L-Edit adds several key features to improve productivity, to automate tedious
manual design tasks and make designing faster. An improved ability to import Virtuso
®
language
technology files was added along with the Layout-Versus-Layout (LVL) comparison capability.
These new capabilities add to L-Edit’s existing Schematic Driven Layout (SDL).Tanner EDA’s
HiPer Verify v2.1 automates Data Redundancy Check (DRC) for deep submicron
manufacturing. It runs Calibre
®
and Dracula
®
rules set hierarchically and natively, and it tightly
integrates to the L-Edit environment, allowing the design rule violations to be identified and
repaired early before they become a major problem. The features in HiPer Verify v2.1 include
significantly improved performance on many layer derivations, DRCs and connectivity based
rules, including Electrical Rule Checking (ERC) for such problems as soft connections or
floating wells. S-Edit and T-Spice together provide a highly effective front-end design solution
where as if back-end design required, L-Edit gives the solution. Designing a layout there are five
basic steps.
Step 1.Design of schematic in S-Edit
Step 2.Simulate the schematic to make sure it behaves as expected using T-Spice
Step 3.Layout the schematic in L-Edit
Step 4.Perform an LVS (Layout Vs Schematic) to make sure layout is functionally the
same as the schematic designed in S-Edit.
Step 5.Simulate the layout using T-Spice with a high-level SPICE model, making sure
L-Edit generates parasitic capacitances so they are included in the simulation.

45. 45
WORKING PROCEDURE FOR TANNER EDA TOOL

1. To open the tanner software from desktop& then new window will be appeared.
2. Then go to Filesave asenter the file name and click to save button. Now the
module is saved.
3. Go to project new module, now the work space is ready for design.
4. To click symbol browser from tool bar. To select the required component and then click
the place button .finally close the symbol browser window.
5. To interconnect the transistor using wires[also use the ctrl & alt button for copy &
movement of the components]
6. To click the input or output port & then click where it is required and then gives the
input &output names.
7. After the all connection completed, to click T-Spice button in the tool bar. A new
window will be open with net list of your design
8. In that include vdd, input pulse type of analysis & output simulation time.[ File
include or click symbol from the tool bar]
 Select file  browse  select the model file. And then click insert. Now model
file is included in the design.
 Select source constantgive the voltage source name as(v1),positive terminal
as vdd, negative terminal as gnd & the DC value as 5 or 3.3 volts and then click
insert button.
 Select source pulsegive the voltage source name as (v2), positive terminal as
(input name),voltage initial as (0),peak as(5v),rise time as(0.1ns),fall time
as(0.1ns)pulse width as(25ns),pulse period as(100ns)and then click insert
command.
 Select analysis transient select powerup simulation, give the maximum time
step as 0.1s & simulation length as 300ns, and the click insert command.
 Select output transient results .to give the node name of which signal is to be
printed in the waveform window (example v1).click add button. Similarly
remaining signals. Then click the insert command.
9. Now entire net list is ready for simulation. Go to simulation run or click run button in
the tool bar.
10. Now verify the outputs.

46. 46
EXPT NO : 7
DATE :

DESIGN AND SIMULATION OF CMOS INVERTER, CMOS NAND & NOR GATES
Aim:

Design and simulate CMOS inverter, CMOS NAND & NOR gates using Tanner EDA
tool.

Software required:

Tanner

THEORY:

CMOS INVERTER:
CMOS inverters (Complementary MOSFET Inverters) are some of the most widely used and
adaptable MOSFET inverters used in chip design. They operate with very little power loss and at
relatively high speed. Furthermore, the CMOS inverter has good logic buffer characteristics, in
that, its noise margins in both low and high states are large.
A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate
terminals, a supply voltage VDD at the PMOS source terminal, and a ground connected at the
NMOS source terminal, were A is connected to the gate terminals and Q is connected to the
drain terminals.(See diagram). It is important to notice that the CMOS does not contain any
resistors, which makes it more power efficient that a regular resistor-MOSFET inverter. As the
voltage at the input of the CMOS device varies between 0 and 5 volts, the state of the NMOS and
PMOS varies accordingly.

47. 47
CMOS NAND & NOR GATE:


A NAND gate (Negated AND or NOT AND) is a logic gate which produces an output
that is false only if all its inputs are true; thus its output is complement to that of the AND gate.
A LOW (0) output results only if both the inputs to the gate are HIGH (1); if one or both inputs
are LOW (0), a HIGH (1) output results. It is made using transistors. The NAND gate is
significant because any Boolean function can be implemented by using a combination of NAND
gates. This property is called functional completeness. Digital systems employing certain logic
circuits take advantage of NAND's functional completeness. The function NAND (a1, a2,
..., an) is logically equivalent to NOT(a1 AND a2 AND ... AND an).
The NOR gate is a digital logic gate that implements logical NOR. A HIGH output (1)
results if both the inputs to the gate are LOW (0); if one or both input is HIGH (1), a LOW
output (0) results. NOR is the result of the negation of the OR operator. It can also be seen as an
AND gate with all the inputs inverted. NOR is a functionally complete operation—NOR gates
can be combined to generate any other logical function. By contrast, the OR operator
is monotonic as it can only change LOW to HIGH but not vice versa.

48. 48
T-SPICE NET LIST FOR INVERTER

.include "C:\Tanner\TSpice70\models\ml2_125.md"
v1 vdd gnd 5
v2 in gnd PULSE (0 5 0 0.1n 0.1n 25n 50n)
.tran/powerup 0.1n 300n method=bdf
.print tran v(in) v(out)
* SPICE netlist written by S-Edit Win32 7.00
* Written on Mar 5, 2014 at 05:55:04
* Waveform probing commands
.probe
.options probefilename="sedit.dat"
+ probesdbfile="D:\vlsi lab\inver.sdb"
+ probetopmodule="Module0"
* Main circuit: Module0
M1 out in Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 out in Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
* End of main circuit: Module0

INPUT/OUTPUT WAVEFORM FOR INVERTER

49. 49
T-SPICE NET LIST FOR NAND GATE

.include "C:\Tanner\TSpice70\models\ml2_125.md"
v1 vdd gnd 5
v2 A gnd PULSE (0 5 0 0.1n 0.1n 25n 50n)
v2 B gnd PULSE (0 5 0 0.1n 0.1n 50n 100n)
.tran/powerup 0.1n 300n method=bdf
.print tran v(A) v(B)v(OUT)
* SPICE netlist written by S-Edit Win32 7.00
* Written on Mar 5, 2014 at 06:05:13
* Waveform probing commands
.probe
.options probefilename="sedit.dat"
+ probesdbfile="nand.sdb"
+ probetopmodule="Module0"
* Main circuit: Module0
M1 OUT A N9 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 N9 B Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 OUT A Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 OUT B Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
* End of main circuit: Module0

INPUT/OUTPUT WAVEFORM FOR NAND GATE

50. 50
T-SPICE NET LIST FOR NOR GATE

.include "C:\Tanner\TSpice70\models\ml2_125.md"
v1 vdd gnd 5
v2 A gnd PULSE (0 5 0 0.1n 0.1n 25n 50n)
v2 B gnd PULSE (0 5 0 0.1n 0.1n 50n 100n)
.tran/powerup 0.1n 300n method=bdf
.print tran v(A) v(B)v(OUT)
* SPICE netlist written by S-Edit Win32 7.00
* Written on Mar 5, 2014 at 06:11:51
* Waveform probing commands
.probe
.options probefilename="sedit.dat"
+ probesdbfile="NOR.sdb"
+ probetopmodule="Module0"
* Main circuit: Module0
M1 OUT A Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 OUT B Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 N8 A Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 OUT B N8 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
* End of main circuit: Module0

INPUT/OUTPUT WAVEFORM FOR NOR GATE


RESULT:
Thus the CMOS inverter, CMOS NAND & NOR gates were simulated using tanner
EDA tool.

51. 51
EXPT NO : 8
DATE :

DESIGN AND SIMULATION OF DIFFERENTIAL AMPLIFIER
Aim:

Design and simulate Differential Amplifier using Tanner EDA tool.

Software required:

Tanner

THEORY:


Differential Amplifier amplifies the current with very little voltage gain. It consists of
two FETs connected so that the FET sources are connected together. The common source is
connected to a large voltage source through a large resistor Re, forming the "long tail" of the
name, the long tail providing an approximate constant current source. The higher the resistance
of the current source Re, the lower Ac is, and the better the CMRR. In more sophisticated
designs, a true (active) constant current source may be substituted for the long tail. The output
from a differential amplifier is itself often differential.

52. 52
T-SPICE NET LIST FOR DIFFERENTIAL AMPLIFIER

.include "C:\Tanner\TSpice70\models\ml2_125.md"
v1 vdd gnd 3.3
.tran/powerup 0.1U 50U method=bdf
.print tran v(N2) v(N3) v(OUT)
* SPICE netlist written by S-Edit Win32 7.00
* Written on Mar 5, 2014 at 07:02:53
* Waveform probing commands
.probe
.options probefilename="F:\LAB\DIFF.tpr.dat"
+ probesdbfile="D:\vlsi lab\DIFFfinal.sdb"
+ probetopmodule="Module0"
* Main circuit: Module0
M1 OUT N3 N9 Gnd NMOS L=0.25u W=2.50u AD=66p PD=24u AS=66p PS=24u
M2 N9 N1 Gnd Gnd NMOS L=0.25u W=2.50u AD=66p PD=24u AS=66p PS=24u
M3 N5 N2 N9 Gnd NMOS L=0.25u W=2.50u AD=66p PD=24u AS=66p PS=24u
M4 N5 N5 Vdd Vdd PMOS L=0.25u W=2.50u AD=66p PD=24u AS=66p PS=24u
M5 OUT N5 Vdd Vdd PMOS L=0.25u W=2.50u AD=66p PD=24u AS=66p PS=24u
v6 N1 Gnd 0.7
v7 N3 Gnd sin 0v 0.5 100k 0.0 0.0 0.0
v8 N2 Gnd sin 0v 0.3 100k 0.0 0.0 0.0
* End of main circuit: Module0

INPUT/OUTPUT WAVEFORM FOR DIFFERENTIAL AMPLIFIER



RESULT:
Thus the differential amplifier was simulated using tanner EDA tool.

53. 53
EXPT NO : 9
DATE :
DESIGN AND SIMULATION OF FULL ADDER
Aim:
Design and simulate full adder using Tanner EDA tool.
Software required:
Tanner
THEORY:

Full adder:
A full adder is a logic circuit that
performs an addition operation on three
binary digits. The full adder produces a
sum and carry value which is both binary
digits. In full adder sum output will be
taken from X-OR Gate, carry output will
be taken from OR Gate.

FULL ADDER USING TANNER

54. 54
T-SPICE NET LIST FOR 10 BIT CONTROLLED OSCILLATOR

* SPICE netlist written by S-Edit Win32 7.00
* Written on Mar 5, 2014 at 06:37:01
* Waveform probing commands
.probe
.include "C:\Tanner\TSpice70\models\ml2_125.md"
v1 vdd gnd 5
v2 in gnd PULSE (0 5 0 0.1n 0.1n 25n 50n)
v3 a0 gnd dc 0 BIT ({0})
v4 a1 gnd dc 0 BIT ({0})
v5 a2 gnd dc 0 BIT ({0})
v6 a3 gnd dc 0 BIT ({1})
v7 a4 gnd dc 0 BIT ({1})
v8 a5 gnd dc 0 BIT ({1})
v9 a6 gnd dc 0 BIT ({1})
v10 a7 gnd dc 0 BIT ({1})
v11 a8 gnd dc 0 BIT ({1})
v12 a9 gnd dc 0 BIT ({1})
.tran/powerup 0.1n 500n method=bdf
.PRINT V(OUT)
.power V1
.options probefilename="oscilator final.dat"
+ probesdbfile="D:\vlsi lab\oscilator final.sdb"
+ probetopmodule="oscillator"
* Main circuit: oscillator
M1 out in N9 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 N9 Vdd Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 out in N6 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 N6 Gnd Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M5 N6 a0 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M6 N6 a1 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M7 N6 a2 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M8 N6 a3 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M9 N6 a4 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M10 Gnd a0 N9 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M11 Gnd a1 N9 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M12 Gnd a2 N9 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M13 Gnd a3 N9 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M14 Gnd a4 N9 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M15 Gnd a8 N9 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M16 Gnd a7 N9 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M17 Gnd a6 N9 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M18 Gnd a5 N9 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M19 N6 a8 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M20 N6 a7 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

55. 55
M21 N6 a6 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M22 N6 a5 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M23 N6 a9 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M24 Gnd a9 N9 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
* End of main circuit: oscillator



INPUT/OUTPUT WAVEFORM 10 BIT CONTROLLED OSCILLATOR









RESULT:
Thus the full adder was simulated using tanner EDA tool.

56. 56
MICROWIND TOOL

It is a layout and simulation tool for deep sub-micron CMOS design. The tool consists of
the user friendly PC tools DSCH3 and MICROWIND3.
DSCH3
The DSCH3 program is a logic editor and the simulator. It is used to validate the
architecture of the logic circuit before the microelectronics design is started. DSCH3 provides a
user friendly environment for hierarchical logic design, and fast simulation with delay analysis,
which allows the design and validation of complex logic structures. The DSCH3 also includes an
interface to SPICE.
Features
 User-friendly environment for rapid design of logic circuits
 Handles both conventional pattern based logic simulation and intuitive on-screen
mouse-driven simulation.
 Supports hierarchical logic design Built-in extractor which generates a SPICE netlist
from the schematic diagram (Compatible with PSPICE and WINSPICE).
 Current and power consumption analysis
 Generates a VERILOG description of the schematic for the layout editor.
 Immediate access to symbol properties(Delay, fanout)
 Models and assembly support for 8051 and PIC 16F84.
 Sub-micron, deep-submicron, nano scale technology supported by huge symbol
library.
MICROWIND3

The MICROWIND3 program allows to design and simulate an integrated circuit at
physical description level. The package contains a library of common logic and analog ICs to
view and simulate. MICROWIND3 includes all the commands for a mask editor.

57. 57
Features

NanoLambda Precision CMOS Layout tool up to 90 nanometers
 Sub-micron, deep-submicron, nanoscale technology support.
 Unsurpassed illustration capabilities
 Design-error-free cell library(contacts, vias, MOS devices, etc.,)
 Advanced macro generator: (capa, MOS, matrix, ROM, pads, path, etc.,)
 Incredible translator from logic expression into compact design-error free layout.
 Powerful automatic compiler from VERILOG circuit into the Layout.
 Online design rule checker: width, spacing, overlap, extension rule verification.
 Built in extractor which generates a SPICE net list from layout.
 Extraction of all MOS width and length.
 Parasitic capacitance, crosstalk and resistance extracted for electrical nodes.
 Import/Export CIF layout from third party layout tools.
 Lock and Unlock layers to protect some part of the design from any changes.
 Enhanced editing commands and layout control.

58. 58
EX.NO:10
DATE:

CMOS Inverter, CMOS NAND and NOR Gates design using Micro Wind
Aim
To design and simulate CMOS Inverter, CMOS NAND and NOR Gates design using
micro wind tool.

Tools required:
Micro wind

Circuit diagram:

CMOS INVERTER:

CMOS NAND & NOR GATE:

59. 59


LAYOUT OF CMOS INVERTER:




LAYOUT OF CMOS NAND AND NOR GATE:

60. 60

OUTPUT OF CMOS INVERTER:


OUTPUT OF CMOS NAND:

61. 61

OUTPUT OF CMOS NOR GATE:























RESULT:
Thus the CMOS inverter, CMOS NAND & NOR gates were simulated using MICRO
WIND Tool.

62. 62
VIVA QUESTION
1. Why we go for VLSI?
2. Why we go for HDL?
3. Why we go for digital?
4. Why we go for CMOS rather than BJT.
5. What is meant by IC?
6. Limitations of half adder?
7. What are the advantages of full adder?
8. What are the advantage & disadvantage of k-map?
9. What are the different types of adder?
10. What is the difference between fast adder and slow adders?
11. What is library?
12. What is simulation?
13. What is synthesis?
14. What is mean by modeling?
15. What are the different types of levels of simulation in verilog?
16. What is mean by gate level modeling?
17. What is mean by behavioral modeling?
18. What is mean by structural modeling?
19. What is mean by switch level modeling?
20. What is mean by RTL modeling?
21. What is mean by algorithm?
22. Expand VHDL, FPGA, and CPLD.
23. What is the use of sensitivity list?
24. What are the combinational logic circuits and sequential circuits?
25. Give the program structure of verilog.
26. What are the various delays in verilog?
27. What are the various data types available in verilog.
28. What are the two main classes of statements used in verilog descriptions?
29. Differentiate wire and reg declaration.
30. What is a statement? How are they classified?
31. Explain concurrent statement?
32. What are sequential statements?
33. Difference between concurrent statement & sequential statements
34. What is always statement?
35. What is use of always statement in Verilog and write the syntax
36. Explain Block statements.
37. What are Generate Statements?
38. Give the verilog operators.
39. What is event?
40. What is elaboration?
41. What is Test Bench?
42. Write syntax for FOR Statements?

63. 63
43. Write the different types of primary construct in Verilog.
44. Name the primary design units in Verilog.
45. What is meant by mealy & moore model.
46. What is meant by synchronous and asynchronous circuits?
47. What are the different types of multiplier in digital?
48. How many clock pulses are needed to compute 8*8 multiplier operation?
49. What is meant by data selector?
50. What is meant by self complementing code?
51. What is meant by data distributer?
52. What are the applications of multiplexer, Demultiplexer, encoder decoder.
53. What is meant by priority encoder?
54. Difference between latch and flipflop.
55. What actually means DFF?
56. What actually means JKFF?
57. What actually means TFF?
58. What actually means SRFF?
59. What are the different types of counter?
60. What is meant by register?
61. What are the different types of shift register?
62. What is mean by universal shift register?
63. What is mean by barrel shift register?
64. What is meant by frequency divider?
65. What are the advantages and application of frequency divider?
66. What is mean by sequence detector?
67. What is meant by overlapping and non overlapping sequence?
68. What is state diagram?
69. What is excitation and truth table?
70. What is meant by state assignment?
71. What is mean by hazards?
72. What is spice?
73. What are uses of spice
74. What is advantage of spice?
75. What is different analysis used in spice?
76. What are the different types of spice?
77. What is mean by net list?
78. What are universal gates?
79. Why we go for spice?
80. What are tools available in VLSI for backend and front end?
81. Why PMOS is good for one?
82. Why NMOS is good for zero?
83. Expansion for spice.
84. What is mean by ALU?
85. Why we go fpga?
86. What is mean by cpld devices?
87. What is mean by PLA
88. What is mean by PAL?

64. 64
89. What is mean by synthesis?
90. What is meant by PAR?
91. What is mean by bit file?
92. What is mean by RTC?
93. What are the difference between normal clock and real time clock?
94. Why we go for micro wind tool?
95. What are the advantages of micro wind tool?
96. What is meant by layout?
97. What is mean by stick diagram?
98. What is mean by polysilicon?
99. When NMOS or PMOS transistor formed?
100. What is meant by nwell?
101. Difference between MOS and BJT.
102. What are the limitations of encoder?
103. What are the various types of encoder?
104. What are the advantages of gray code?
105. What are the various types of code converters?
106. What is the use of comparator?
107. What is mean by negation? Also what type of gate is used for negation?
108. What is mean by technology file?
109. What is the use of Concatenation Operator?
110. Difference between identifiers and keyword.
111. What are the advantage and disadvantages of k-map?
112. What is advantage of tabulation method?
113. What are the logic families’ available in digital.
114. What is uses/advantage/application of parity checker/generator?
115. What is mea by master slave flip flop?
116. Why k-map variables placed in this order 00,01,11,10?
117. Difference between johns’ and ring counter.
118. How many flip flops are required to design mod-n counter.
119. What is mean by fundamental mode and pulse mode circuit?
120. What is mean by races?
121. What is mean by critical races and non critical races?
122. What is mean by cycles?
123. What advantages do synchronous counter have over asynchronous counter?
124. What are the different types hazards occur in digital circuits?
125. What are tristate circuits?