Efabless Marketplace webinar slides 2024

tech

1. Easily make the chips you want using Efabless verified modules & IP blocks
Efabless Marketplace
Making custom chips:
Easier and faster than ever before
Image courtesy of Maximo Balestrini
May 9, 2024
https://efabless.com

2. Introductions
●Anton Maurovic
○Technical Program Manager

●Marwan Abbas
○IC / EDA Developer

●Andrea Vedanayagam
○Marketing Communications Services
●Tim Edwards
○SVP Analog and Design

●David Lindley
○Technical Program Manager

●Andy Wright
○SVP New Product Introduction

3. June 2024 tapeout special offer!
If your tapeout in June 2024 goes for fabrication as part of our chipIgnite CI2406 shuttle…
…you won’t pay $2500 to use our new high-density SRAM macros!
Our SRAM macros are offered free of charge
for all CI2406 shuttle slots – a limited introductory offer.

4. What we’ll go through today…
1.Who we are and what we enable for you
2.Efabless Marketplace: Drop-in analog, digital, and streamlined SRAM IP blocks
3.Overview of some of the available IP blocks
4.Let’s create a design: Simple digital layout using SRAM macro, done with OpenLane & IPM
5.Chip submission process, high-level
6.More details about analog & digital IP blocks, now and coming soon
7.Some example design ideas
8.Q&A

5. If you haven’t heard about us…
1.We make chips, or rather help you make them – more quickly,
easily, and affordably than has ever been possible.
2.Democratizing chip design - OpenMPW
3.Quick overview of Caravel, Caravan, OpenFrame
4.QFN64 package with multiple power domains, 38 GPIOs (some
supporting dedicated analog)
5.RISC-V SoC for testing and/or system supervision: microcontroller
running firmware via SPI, with internal 32-bit wishbone bus and
128-port control/LA.
Photographs courtesy of Maximo Balestrini

6. Why Efabless?
1.Built on open source, working with the community
2.Incredible affordability for prototyping and volume production
3.Free, open-source tools and 130nm open PDK – Start now; no NDAs, no commitment
4.An ever-growing community and wide range of open designs
5.Strong support network and consultation services
6.And now: Efabless Marketplace offers drop-in, ready-made IP blocks

7. What this means…
●You can now assemble just the chip you want.
●Use our verified components, either partially or entirely.
●Cut research, development, and licensing costs.
●Save time, improve confidence, and extend your functionality.
●Target your particular needs, including:
○Low power footprint
○High performance
○High system integration, in a small package
○Analog & mixed-signal applications
○Reconfigurability
Suitable for new designers
and experienced
EDA/VLSI designers alike

8. What this means...
Even if you’ve never done ASIC/VLSI design before, in 1 day you could create a chip design
and join one of our shuttles…
●Use our library, guides, and free tools to assemble the IP blocks you need.
●Optionally create glue logic or a specialized control design & additional functionality
●Generate a layout, run tests, get performance metrics
●Submit to our servers, review with our team, join a shuttle for $9,750
●Receive 100 bare dice, or 100 QFN parts, inc. 10 mounted on PCBs plus 2 eval boards

For more experienced designers…
●Embed and modify our analog layouts, or combine with your own
●Use commercial or FOSS EDA tools for schematic capture, layout, DRC, LVS, extraction/simulation
Ask us about commercial
volumes & specialized
packaging requirements

9. Available macros
Available IPs on the Marketplace
Digital Analog
4KByte Commercial SRAM Ultra low-power comparator HGBW Operational amplifier
16KByte Commercial SRAM Instrumentation amplifier Over-voltage detector
32KByte Commercial SRAM LP Operational amplifier Brown-out detector
GPIO peripheral Comparator Temperature sensor
32-bit timer and PWM generator 1.8v Precision bandgap Low-speed XO
Quad SPI Flash memory controller Low-power 1.8v LDO High-speed XO
DFFRAM512x32 Current reference bias generator Programmable PLL
DFFRAM256x32 16-bit capacitive DAC Programmable Sallen-Key filter
DFFRAM128x32 12-bit resistive DAC Bandgap-referenced Power-on-Reset
UART 8-bit Rheostat 16-bit SAR ADC 1MSPS
I2S receiver 12-bit IDAC
I2C master controller

SPI master controller Sourced internally, from Chipalooza, and
other community/commercial partners

10. Let’s create a design
NOTE: The presented example design can be found here:
https://github.com/amm-efabless/my_sram_test_chip1

11. Let’s create a design…
We’ll do this using Caravel, but options exist for Caravan & OpenFrame
Caravel padframe
Caravel
RISC-V
Management
SoC
User project area
Wishbone
SRAM IP
Our controller (logic,
mix of IP blocks, etc.)
We’ll do this option
in this webinar
Option: Embed IP in your design
Caravel padframe
User project area
Wishbone
SRAM IP
Our controller
(logic, etc.)
Caravel
RISC-V
Management
SoC
Option: Use separate blocks and connect them up
A
B

12. Steps overview
●Step 1: Install & try IPM
●Step 2: Create your project repository from our template
●Step 3: Clone your repo, install OpenLane, PDK, etc…
●Step 4: Install EFSRAM IP with ‘IPM’
●Reviewing the components of our project
●Step 5: Create OpenLane config for our macro
○5.1: config.json – Project essentials
○5.2: config.json – Hard IP integration
○5.3: config.json – PDN & special routing requirements
●Step 6: Custom logic (Verilog)
●Step 7: Run OpenLane flow for our macro
●Step 8: Review results
●Step 9: Build user_project_wrapper GDS
●Step 10: Finalisation

13. Step 1: Install & try IPM
cd ~
git clone https://github.com/efabless/IPM.git
pip install ./IPM
ipm ls-remote

14. Step 2: Create your project repository from our template
https://github.com/efabless/caravel_user_project

15. Step 3: Clone your repo, install OpenLane, PDK, etc…
Some of this you might’ve done already, and in other ways:
●Clone your repo:
○git clone [email protected]:amm-efabless/my_sram_test_chip


●Install OpenLane, PDK, etc…
○make setup
○Takes ~10mins, uses 7.5GB disk
●We now have:
○caravel
○dependencies/openlane_src
○dependencies/pdks
○dependencies/timing-scripts
○mgmt_core_wrapper
○venv
○venv-cocotb

16. Step 4: Install EFSRAM IP with IPM
●Use IPM to install the IP block(s) we want:
○ipm install EFSRAM_01024x032_008_18
├── README.md - General information (or datasheet) for project
├── EFSRAM_01024X032_008_18.yaml - Configuration file for IP
├── doc/ - Documentation files for the project.
├── hdl/ - Hardware Description Language files.
│ ├── rtl/ - For Register Transfer Level designs.
│ │ └── bus_wrapper/ - Wrapper for bus interfaces.
│ ├── gl/ - Gate-level designs and netlists.
│ └── sim/ - Simulation models.
├── lib/ or spef/ - timing related files.
├── gds/ - Contains the final GDSII layout files of the design
├── lef/ - Library Exchange Format files
├── mag/ - Layouts in Magic format
├── verify/ - Verification and testing scripts.
│ └── utb/ - Unit test benches for module-level verification
└── fw/ - Firmware code for the project.
●This creates:
○ip/dependencies.json – suitable to commit to your repo:
git add ip/dependencies.json
○A link in ip/ to your own local copy of the IP files, including
wrapper file(s) if available/applicable
●We’re mostly interested in the following files as found in
ip/EFSRAM_01024x032_008_18:
○hdl/EFSRAM_1024x32_wrapper.v – hard IP
○hdl/ram_controller.v – Wishbone
○hdl/SRAM_1024x32.v – Macro
○hdl/EFSRAM_01024x032_008_18_stub.v - Black box
○gds/EFSRAM_1024x32_wrapper.gds
○lef/EFSRAM_1024x32_wrapper.lef
○lib/EFSRAM_1024x32_wrapper_tt_180V_25C.lib
Example IP contents (may vary):

17. Step 4: Install EFSRAM IP with IPM
●Use IPM to install the IP block(s) we want:
○ipm install EFSRAM_01024x032_008_18
├── README.md - General information (or datasheet) for project
├── EFSRAM_01024X032_008_18.yaml - Configuration file for IP
├── doc/ - Documentation files for the project.
├── hdl/ - Hardware Description Language files.
│ ├── rtl/ - For Register Transfer Level designs.
│ │ └── bus_wrapper/ - Wrapper for bus interfaces.
│ ├── gl/ - Gate-level designs and netlists.
│ └── sim/ - Simulation models.
├── lib/ or spef/ - timing related files.
├── gds/ - Contains the final GDSII layout files of the design
├── lef/ - Library Exchange Format files
├── mag/ - Layouts in Magic format
├── verify/ - Verification and testing scripts.
│ └── utb/ - Unit test benches for module-level verification
└── fw/ - Firmware code for the project.
●This creates:
○ip/dependencies.json – suitable to commit to your repo:
git add ip/dependencies.json
○A link in ip/ to your own local copy of the IP files, including
wrapper file(s) if available/applicable
●We’re mostly interested in the following files as found in
ip/EFSRAM_01024x032_008_18:
○hdl/EFSRAM_1024x32_wrapper.v – hard IP
○hdl/ram_controller.v – Wishbone
○hdl/SRAM_1024x32.v – Macro
○hdl/EFSRAM_01024x032_008_18_stub.v - Black box
○gds/EFSRAM_1024x32_wrapper.gds
○lef/EFSRAM_1024x32_wrapper.lef
○lib/EFSRAM_1024x32_wrapper_tt_180V_25C.lib
Datasheets and other documentation provided

18. Reviewing the components of our project
Caravel padframe
Caravel RISC-V
Management
SoC
User project area
Wishbone
SRAM IP
Our controller: logic,
mix of IP blocks, etc.
wishbone_sram
openlane/user_project_wrapper/
●We’ll modify it to properly
contain our design and wire it
up to the rest of the chip
●Depends on basic “top-level”
Verilog to describe the macros
being used and how the wiring
is done.
openlane/wishbone_sram/
●We’ll create it to tell
OpenLane how to build
our main design’s macro
●Can (and will) depend on
additional digital logic
(Verilog code).
openlane/user_proj_example/
●Example project that can be
deleted or ignored.

19. Step 5: Create OpenLane config for our macro
Create openlane/wishbone_sram/ …
Most of the files that will go into this directory (below) can be assembled from a combination of
openlane/user_proj_example/* and caravel_user_sram/openlane/SRAM_1024x32
●config.json
●macro.cfg
●pin_order.cfg
●pdn.tcl
●base.sdc
Caravel padframe
Caravel RISC-V
Management
SoC
User project area
Wishbone
SRAM
IP
Our controller: logic,
mix of IP blocks, etc.
wishbone_sram

20. Step 5.1: config.json – Project essentials
1
2
3
4
5
1.Name your macro. Should match parent
directory name.
2.Specify files that will be used to
synthesize your design’s logic. In this case
they come from our IP’s supplied
reference design + our small extra logic:
wishbone_sram.v
3.Our timing target is for a 25ns clock (i.e.
40MHz).
4.Absolute: Specifying exact size, instead of
letting OpenLane choose a relative size.
5.We are opting to control precisely where
connections are made on the edges of our
macro.
Caravel padframe
Caravel RISC-V
Management
SoC
User project area
Wishbone
SRAM
IP
Our controller: logic,
mix of IP blocks, etc.
wishbone_sram

21. Step 5.2: config.json – Hard IP integration
Caravel padframe
Caravel RISC-V
Management
SoC
User project area
Wishbone
SRAM
IP
Our controller: logic,
mix of IP blocks, etc.
wishbone_sram
Actual instance name we want for the hard SRAM IP wrapper that
we’ll place inside our wishbone_sram macro. Instance is based on
the supplied Efabless Wishbone wrapper reference design:
ip/EFSRAM_01024x032_008_18/hdl/SRAM_1024x32.v

22. Step 5.3: config.json – PDN & special routing requirements
Caravel padframe
Caravel RISC-V
Management
SoC
User project area
Wishbone
SRAM
IP
Our controller: logic,
mix of IP blocks, etc.
wishbone_sram
Refer to each IP’s documentation for
any special power or routing
requirements.

Contact Efabless for additional
support if needed.

NOTE: PDN = Power Distribution
Network, typically a series of
horizontal and/or vertical metal
straps that offer balanced power
distribution across the whole area for
the layout and any IP blocks.

23. Step 6: Custom logic (Verilog)
Create verilog/rtl/wishbone_sram.v

24. Step 6: Custom logic (Verilog)
Create verilog/rtl/wishbone_sram.v

(from macro.cfg)

25. Step 7: Run OpenLane flow for our macro
make wishbone_sram

26. Step 8: Review results
●Timing & other reports
●View the GDS: klayout gds/wishbone_sram.gds
380um x 435um

27. Step 9: Build user_project_wrapper GDS
●Modify openlane/user_project_wrapper/config.json
●Modify macro.cfg
●Wire up our macro in verilog/rtl/user_project_wrapper.v …
Caravel padframe
Caravel RISC-V
Management
SoC
User project area
Wishbone
SRAM
IP
Our controller: logic,
mix of IP blocks, etc.
wishbone_sram

28. Step 9: Build user_project_wrapper GDS
●Modify openlane/user_project_wrapper/config.json
●Modify macro.cfg
●Wire up our macro in verilog/rtl/user_project_wrapper.v
Caravel padframe
Caravel RISC-V
Management
SoC
User project area
Wishbone
SRAM
IP
Our controller: logic,
mix of IP blocks, etc.
wishbone_sram
●Run: make user_project_wrapper
●Inspect reports and final GDS: klayout gds/user_project_wrapper.gds

29. Step 9: Build user_project_wrapper GDS
●Modify openlane/user_project_wrapper/config.json
●Modify macro.cfg
●Wire up our macro in verilog/rtl/user_project_wrapper.v
Caravel padframe
Caravel RISC-V
Management
SoC
User project area
Wishbone
SRAM
IP
Our controller: logic,
mix of IP blocks, etc.
wishbone_sram
●Run: make user_project_wrapper
●Inspect reports and final GDS: klayout gds/user_project_wrapper.gds
Whole available user project area

30. Step 10: Finalisation
●Edit verilog/rtl/user_defines.v






●Compress GDS for repo: make compress
●Update verilog/includes/*
●Write & run automated tests: cocotb and/or Verilog
●Option for full-chip simulation with annotated timing data
●Add files to repo, especially lef/, def/, gds/

31. Submitting your chip to the shuttle
1.Reserve your slot: $200 deposit
2.Set up an Efabless Platform repository & push
3.Join shuttle through Efabless website/platform
4.Get in early with preliminary:
a.MPW Precheck job
b.Tapeout job
5.Iterate on your design as you need, repeating step 4
6.Design reviews & other support
7.Submit

32. More about IP blocks, now & future
●Wrapped vs. unwrapped analog IPs
●More coming soon
●Analog routing considerations,
cooperating with OpenLane +
Magic/Xschem
●Documentation: Datasheets, guides,
simulation/testing

33. Some example design ideas
●Edge ML applications: Learning & inference
●Boot-load code in SRAM
●Data processing - buffer audio
●Energy harvesting
●Monitoring & control: 32-bit RISC-V or proprietary MCU w/ memory-mapped devices:
○64kByte SRAM
○8 ADCs – Different Vrefs
○4x I2C controllers
○6x UARTs
○Complex internal filter
○DAC
○SPI
○Test pins

34. So what next?
●Upcoming webinar: Demonstration of an analog project prepared by Tim using IP blocks
●More information forthcoming about Efabless Marketplace, IPs, documentation
●How we can help? What IPs do you need? What do you want to make? What’s holding you back?
Don’t forget: Use any or all of our high-density SRAM macros in your June 2024
tapeout, and you won’t pay any extra. Skip the $2500 fee before June 3rd, 2024!
Contact us at: [email protected]

35. Links
●https://github.com/efabless/IPM
●https://github.com/efabless/EFSRAM_01024x032_008_18
●https://github.com/efabless/caravel_user_sram
●https://github.com/efabless/caravel_user_project
●https://github.com/amm-efabless/my_sram_test_chip1
●https://platform.efabless.com/design_catalog/ip_block
●https://efabless.com
●https://openlane.readthedocs.io/en/latest/reference/configuration.html
●Chipalooza information and webinar recording
●https://github.com/RTimothyEdwards/chipalooza_projects_1

36. Thank you for joining us!
https://efabless.com
For more info, reach out to us at: [email protected]