Flip flop and sequential circuit in digital electronics .pdf

Flip flop and sequential circuit

1. Flip Flops

2. Simple Latch
•circuit ouput - LO state, command input – LO
latch output low.
Command input – HI, gate output – HI
The feeciback loop to the other gate input - latch
remains HI
even when the HI is removed from -the latch
command input.
Command input has no effect.
•Unlatch – remove power or break feedback
connection
NOR Q
0 0 1 0
0 1 0 1
1 0 0 0
1 1 0 1

3. Memory Element
Set Reset Q
0 0 0
0 1 1 --> 0
1 1 0
1 0 0 --> 1
Q = 0 Reset / Clear state
Q = 1 Set state

4. Improved Circuit
Set Clear Q Q’
0 0
0 1
1 0
1 1
Normal output
Complentary output

5. Circuit Operation
Set Clear Q Q’
0 0 Hold Hold
0 1 0 1
1 0 1 0
1 1 Should be avoided

6. Timing Diagram
can also be constructed from NAND
gates

7. Circuit Operation
Set’ Clear’ Q Q’
0 0 Should be avoided
0 1 1 0
1 0 0 1
1 1 Hold Hold

9. two stable states
bistable multivibrators
High (logic 1) and Low (logic 0).
flip – flop - can switch between the states
under the influence of a control signal (clock or
enable)
i.e. they can ‘flip’ to one state and ‘flop’ back to
other state.
Flip – flops - a binary storage device
can store binary data (0 or 1).
FlipFlop States

10. 1 – bit binary data storage devices.
The main difference is the triggering mechanism.
Latches are transparent when enabled
flip – flops are dependent on the transition of the clock signal
i.e. either positive edge or negative edge.
The modern usage is reserved to clocked devices
latch is much simpler device.
Latches vs Flip-Flops

12. Controlled SR Latch

13. D Latch

14. Clocked Memory Element
Latches are level-sensitive - output follows their inputs as long
as enabled.
Transparent during this entire time when the enable signal is
asserted.
The output change only at the rising or falling edge of the
enable signal.
This enable signal is usually the controlling clock signal.
All changes synchronized to the rising or falling edge of the
clock.
edge-triggered flip-flop achieves this by combining in series a
pair of latches.

15. D Flip Flop using Latches
10 gates (46 transistors)

16. D Flip Flop using Latches

17. Clock Signal

18. Like a camera!
Clock rising edge causes Q to change after a short delay
This is the only time Q ever changes
The value of D just before the clock rising edge is the new Q
D-FF is like a camera...
“picture” from the scene (input is D).
clock input is like trigger/click on the camera
when pressed, samples the input and takes a picture.
The “cause” is the rising edge of the CLOCK and the “effect” is the Q output
sample D input and keep the value until the next rising edge of the clock.
I

19. Timing Constraints
t
su
– Set Up Time
t
h
– Hold Time

20. FF Timing Specifications
Clock:
Periodic Event, causes state of memory
element to change.
Setup Time (Tsu):
Minimum time before the clocking event by
which the input must be stable
Hold Time (Th)
Minimum time after the clocking event during
which the input must remain stable
Input
Clock
T
su
T
h
There is a timing "window" around the clocking event during which the input
must remain stable and unchanged in order to be recognized

21. • Setup time
• Hold time
• Minimum clock width
• Propagation delays
(low to high, high to low,
max and typical)
D
Clk
Q
T
su
20
ns
T
h
5
ns
T
w
25
ns
T
plh
25 ns
13 ns
T
su
20
ns
T
h
5
ns
T
phl
40 ns
25 ns
All measurements are made from the clocking event
that is, the rising edge of the clock
Set up & Hold Time

23. Positive-edge-triggered D flip-
flop
three interconnected SR latches
6 NAND gates (26 transistors)
as opposed to 10 gates (46 transistors)
for the pair of D latches

24. Before Clock Edge

25. After Clock Edge

26. Comparison of Latch and Flip
Flop
Qa Latch Output
Qb Positive Edge Triggered flipflop output
Qc Negative Edge Triggered flipflop output

27. Asynchronous Inputs
Direct Inputs

28. 1 Bit Storage

29. 2 Bit Storage

30. 4 Bit Storage

31. 1 Bit Controlled Storage

32. 2 Bit Controlled Storage

33. 4 Bit Controlled Storage
Element