Flip Flops (JK,SR,D and T)in digital electronics.pptx

Flip flops

1. Prof. J. N. Kale Assistant Professor Subject- Flip Flop

2. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> One bit memory cell is designed using two cross coupled invertors N1 and N2. (NAND gates are used as invertors). It is known as bistable element as it contain only two states logic 1 state (HIGH) and logic 0 state (LOW). Let us assume that Q=1 Which is input to N2. So output of N2 is 0 which is input for N1. So output of N1 is 1 which confirms our assumption. A B Y 1 1 1 1 1 1 1

3. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> Conclusion The outputs Q and Q’ are always complementary. The circuit has two stable states. If circuit is in 1 state then it continues to remain in this state. Similarly if it is in 0 state then it continues to remain in this state. So it is one bit memory cell.

4. No way of entering desired digital information in latch shown in Fig. 1 When power is switched ON the circuit will switch to one of the stable state either 1 or 0 . Can not predict!! DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> Fig. 1 Fig. 2

5. A B Y 1 1 1 1 1 1 1 DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> Case 1 S=R=0 Assume Initial Q = 0 then Next Q=0 Assume Initial Q = 1 then Next Q=1 State does not change. Note: If We know that one of the input of NAND gate is 0 then output of the NAND will be always 1… Case 2 S=1 and R=0 Assume Initial Q = 0 then Next Q=1 Assume Initial Q = 1 then Next Q=1 Set state.

6. A B Y 1 1 1 1 1 1 1 DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> Note: If We know that one of the input of NAND gate is 0 then output of the NAND will be always 1… Case 3 S=0 and R=1 Assume Initial Q = 0 then Next Q=0 Assume Initial Q = 1 then Next Q=0 Reset state. Case 4 S=1 and R=1 Both Q and Q’ tries to become 1. Invalid. (This condition is prohibited)

7. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> Summary of operation of SR Latch S R Q n Q n+1 Remark No Change 1 1 1 Reset 1 1 1 1 Set 1 1 1 1 1 × Ambiguous 1 1 1 × Case 1 S=R=0 State does not change. Case 2 S=0 and R=1 Reset state. Case 3 S=1 and R=0 Set state. Case 4 S=1 and R=1 Invalid.

8. It is often require to set or reset the memory cell in synchronism with train of pulse known as clock. Such a circuit is called as clocked SR Flip Flop. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

9. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

10. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> Summary of operation of SR Flip Flop (Positive edge triggered) CLK S R Q n Q n+1 Remark No Change 1 1 1 Reset 1 1 1 1 Set 1 1 1 1 1 × Ambiguous 1 1 1 ×

11. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> Summary of operation of SR Flip Flop (Negative edge triggered) CLK S R Q n Q n+1 Remark No Change 1 1 1 Reset 1 1 1 1 Set 1 1 1 1 1 × Ambiguous 1 1 1 ×

12. Similar to SR FF only one major difference: J=K=1 condition does not result in ambiguous state. For this condition (J=K=1) the FF always goes in opposite state (i.e. if previous state of FF is 0 then next state will be 1 and if previous state is 1 then next state will be 0). This is called as toggle mode of operation. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

13. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> Operation of JK Flip Flop (Negative edge triggered) CLK J K Q n Q n+1 Remark No Change 1 1 1 Reset 1 1 1 1 Set 1 1 1 1 1 1 Toggle 1 1 1

14. It has only one input D, which stands for data. Block diagram Operation If D is 0 then Q n+1 will 0. If D is 1 then Q n+1 will be 1. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> CLK D Q n Q n+1     1   1 1   1 1 1

15. D FF can easily implemented using JK FF by adding DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

16. It has only one input T. Block diagram Operation If T is 0 then no change IF T is 1 then toggle. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> CLK T Q n Q n+1     1 1   1 1   1 1

17. It is obtained from JK FF by connecting J and K inputs together. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

18. In designing sequential circuits sometimes present state and next state of the circuit are specified and it is required to find input condition that will cause desired transition of the state. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

19. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> Truth table for SR Flip Flop (Negative edge triggered) CLK S R Q n Q n+1 Remark No Change 1 1 1 Reset 1 1 1 1 Set 1 1 1 1 1 × Ambiguous 1 1 1 × Excitation table Q n Q n+1 S R × 1 1 1 1 1 1 ×

20. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> Truth table for JK Flip Flop (Negative edge triggered) CLK J K Q n Q n+1 Remark No Change 1 1 1 Reset 1 1 1 1 Set 1 1 1 1 1 1 Toggle 1 1 1 Excitation table Q n Q n+1 J K × 1 1 × 1 × 1 1 1 ×

21. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> Excitation table Q n Q n+1 D 1 1 1 1 1 1 Truth Table CLK D Q n Q n+1     1   1 1   1 1 1

22. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> Excitation table Q n Q n+1 T 1 1 1 1 1 1 Truth Table CLK T Q n Q n+1     1 1   1 1   1 1

23. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> Excitation table Q n Q n+1 T 1 1 1 1 1 1 Truth Table CLK T Q n Q n+1     1 1   1 1   1 1

24. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

25. Convert SR FF into D FF DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

26. Convert SR FF into D FF Step1 Write TT of D FF. Step2 Add two column S and R in TT of D FF. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> D Q n Q n+1 1 1 1 1 1 1 D Q n Q n+1 S R 1 1 1 1 1 1

27. Step3 DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> D Q n Q n+1 S R 1 1 1 1 1 1 Excitation table Q n Q n+1 S R × 1 1 1 1 1 1 × D Q n Q n+1 S R × 1 1 1 1 1 1 1 1 ×

28. Step4 Neglect Qn+1 Design required combinational circuit assuming D, Qn DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> D Q n Q n+1 S R × 1 1 1 1 1 1 1 1 ×

29. Step5 DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> D Q n S R × 1 1 1 1 1 1 ×

30. Step6 DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

31. It is a sequential circuit used for counting. It is used for counting particular event. Clock is given as a input. A circuit used for counting the clock pulses is called as counter. Counter is group of FF. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

32. Basically there are two types of counter Asynchronous counter (Ripple counter) Synchronous counter In case of Asynchronous counter all the flip flops are not clocked simultaneously. External clock pulse is applied only to first FF and output of first becomes clock for second, output of second becomes clock for third and so on. In case of Synchronous counter all the flip flops are clocked simultaneously. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

33. No. of FF required? 2 bit counter so two FF will be required. Type of FF T or JK Fig. shows 2 bit counter with T FF having negative edge triggering.. It will have 4 states (2 2 ). Inputs of both FF should be at Logic 1 so that output will toggle. External clock pulse is applied to FF A and its o/p Q A is connected to clock input of FF B. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

34. f(Q A )=f(CLK)/2 f(Q B )= DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

35. When power is applied, all flip flops comes in random state. In some digital system it is required to set FF when power is applied.. In some digital system it is required to reset FF when power is applied.. So we have Preset and Clear input in FF.. These are active low inputs. If Preset’=0 then Q=1 If clear’=0 then Q=0 These are asynchronous inputs because there operation is independent of the clock. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

36. The counter with N FF can have 2 N states. For example 2 bit counter has 4 states, 3 bit counter has 8 states. If counter has m states then it is called MOD m counter. 2 bit counter is MOD 4 counter. If MOD m counter is required then number of FF required (N) is determined using following condition. m<=2 N Example For MOD 3 counter 2 FF For MOD 6 counter 3 FF But using 3 FF we will get 8 states. In MOD 6 counter only 6 states will be used, 2 will be unused. The counter is required to reset at the end of 6 th clock pulse. This is possible by generating logic 0 signal at the end of 6 th clock pulse and applying it to clear input of all FF. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

37. Design MOD 6 ripple counter. Using 2 FF not possible Using 3 FF it is possible but required to design RESET logic. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> Modulus Asynchronous counter cont..

38. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> It is ripple counter IC. It is decade counter. (mod 10) It consist of 4 FF internally connected together. It contain two separate counter i.e MOD 2 and MOD 5. These counter can be used as independently or in combination to provide MOD 10 counter. There are two reset input R0(1) and R0(2) both of which are to be connected to logic 1 for clearing outputs of counter . There are two more reset input R9(1) and R9(2) both of which are to be connected to logic 1 for setting counter to 1001.

39. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

40. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

41. Design MOD 6 counter using 7490 DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

42. Steps Determine number of FF required and decide type of FF. Write excitation table for selected FF. Draw state diagram. Prepare circuit excitation table. Prepare K map for each FF input in terms of FF outputs as input variable. Simplify K map and obtain minimized expression. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

43. Step1: 2 bit counter so 2 FF will be required. Type of FF is T as given in problem. Step2: Step3: DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> Excitation table Q n Q n+1 T 1 1 1 1 1 1

44. Step4: DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> Present state Next state TB TA Q B Q A Q B1 Q A1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

45. Step5: DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number> Present state Next state TB TA Q B Q A Q B1 Q A1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

46. Step7: DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>

47. DEPARTMENT OF COMPUTER ENGINEERING, Sanjivani COE, Kopargaon <number>