FPGA based mini Project.pptx

FPGA Based Mini Project

1. Power Point Presentation on FPGA Based Mini Project Under the guidance of Dr. Kangkana Baishya Dr. Mridusmita Sharma Electronics Design Lab

2. PRESENTED BY : UDDIPON DUTTA 190610003088 SATYABRAT BORDOLOI 190610003078 NEELAV BARMAN 190610103048 SUMAN SUKLABAIDYA 190650003007 24 June 2022 2

3. C ONTENT 1 2 3 4 Introduction to FPGA •Pros and Cons •Applications Introduction:- • Development Board • Components of FPGA Mimas – Spartan 6 FPGA Development Board:- •Oracle VirtualBox •Xilinx ISE Design Suite Softwares Used:- • Project Summary • Smart Digital Locker Experiments:- 4-6 11-17 7-8 9-10 Slide Numbers Slide Numbers Slide Numbers Slide Numbers 24 June 2022 3

4. INTRODUCTION A FPGA (Field Programmable Gate Arrays) is a programmable integrated circuit which consists of collection of: Configurable Logic Blocks (CLBs) Configurable I/O Blocks Programmable Interconnect 24 June 2022 4 FPGAs are designed to be configured by a customer or designer after manufacturing – hence “Field Programmable ”. Similar to Lego boxes FPGA contains modular digital circuits comprising a few of both combinational (e.g. logic gates, multiplexers) and sequential components (e.g. flip-flops ). FPGA can be used to build almost any digital circuit — provided the selected FPGA part has enough resources (blocks and speed) to implement that circuit.

5. P ROS A ND C ONS ▪ FPGAs can be programmed at logic level. Hence it can implement faster and parallel processing of signals. This is difficult to be executed by processor. ▪ The programming of FPGA requires knowledge of VHDL/ Verilog programming languages as well as digital system fundamentals. ▪ FPGA ICs are readily available which can be programmed using HDL code in no time. Hence the solution is available faster to the market ▪ The manufacturing cycle is too much costly, lengthy and engages lots of manpower. ▪ FPGA allows flexibility in design without introducing a large amount of delay and cost risk. ▪ Can not get as much circuitry a single chip. 24 June 2022 5

6. APPLICATIONS DEFENSE: Increased cyber security. Increasing automation in vehicles and weapons Battlefield portability and high mission life COMMUNICATIONS: Lower physical and carbon footprint IoT growth with minimal energy consumption Delivers 4k video INDUSTRIAL: Rise of cloud services requiring decentralized, secure computing Increased networking of factory automation Portability becoming more prevalent 24 June 2022 6

7. SPECIFICATIONS :- FPGA: Spartan-6 XC6SLX9 in TQG144 package Flash memory: 16 Mb SPI flash memory (M25P16) 100MHz CMOS oscillator USB 2.0 interface for On-board flash programming FPGA configuration via JTAG and USB 8 LEDs and four switches for user-defined purposes 70 IOs for user-defined purposes Onboard voltage regulators for single power rail operation Mimas – Spartan 6 FPGA Development Board 24 June 2022 7

8. COMPONENTS OF SPARTAN-6 USB Interface ON BOARD LEDs ON BOARD PUSH BUTTONS DC Power Supply SPARTAN-6 LX9 CHIP JTAG Connector 100MHz CMOS oscillator M25P16: 16 Mb SPI flash memory ON BOARD GPIOs 24 June 2022 8

9. SOFTWARE Oracle VirtualBox allows us to use Linux OS in host Windows 11 thereby providing us a way to run the discontinued version of Xilinx ISE Design Suite in host Windows 11. 24 June 2022 9

10. Design Suite V14.7 Design Summary window Xilinx ISE (Integrated Synthesis Environment) is a discontinued software tool from Xilinx for synthesis and analysis of HDL designs , which primarily targets development of embedded firmware for Xilinx FPGA and CPLD integrated circuit (IC) product families. ISE supports up to Spartan 6 , and the older devices including CPLDs (XC9500 and CoolRunner ) Xilinx ISE Design Suite 24 June 2022 10

11. EXPERIMENTS PROJECT Summary : 24 June 2022 11

12. EXPERIMENTS PROJECT Summary : Implement Design 24 June 2022 12

13. Impelmentation 24 June 2022 13

14. Result : Single on-board LED Blink Multiple on-board LED Blink External LED Blink using GPIOs 24 June 2022 14

15. DIGITAL SMART LOCKER A digital circuit that serves as the controller for a lock that secures the vault area of a UNSECURE BANK. Bank Officials may open the lock according to the following protocols: PROTOCOLS: 1.During business hours – Bank P resident (P) or Both V ice P residents (VP1 & VP2) 2.Off hours – the P resident and either Vice P resident 24 June 2022 15

16. STEPS FOLLOWED: 24 June 2022 16

17. BANK LOCKED (red led glows) and OFF hours(blue led off) BANK LOCKED (red led glows) and BUSINESS hours(blue led glows) BANK UNLOCKED (red led OFF, green LEDs blinking) in OPEN hours when: 2 . BANK UNLOCKED (red led OFF, green LEDs blinking) during OFF hours when: PRESIDENT UNLOCKS VICEPRESIDENT1 & 2 UNLOCKS PRESIDENT & VICEPRESIDENT 1 UNLOCKS PRESIDENT & VICEPRESIDENT 2 UNLOCKS 24 June 2022 17

18. CONCLUSION :- Learned the various aspects of a FPGA board along with its implementation in small projects. Got the practical experience regarding the theories about digital circuits, Truth table, Digital logic etc. Learned to use ISE Design Suite and acquired some Verilog coding skills. Got to know about VirtualBox along with its applications. 18

19. References Numato Lab - https://numato.com/product/mimas-spartan-6-fpga-development-board/ FPGA for Dummies by Andrew Moore EE Times- https://www.eetimes.com/all-about-fpgas/ Oracle VirtualBox - https://www.virtualbox.org/ 24 June 2022 19

20. Thank You 24 June 2022