FPGA Design Flow and synthesis Techniques

Low Power VLSI Design

1. For Academic Use Only
Presentation Name 1
FPGA Design Flow

2. For Academic Use Only
Presentation Name 2
Sintesi

3. For Academic Use Only
Presentation Name 3
Translate

4. For Academic Use Only
Presentation Name 4
Circuitnetlist
Netlist: A textdescriptionof the circuitconnectivity. Itisbasicallya
list of connectors, a list of instances, and, foreachinstance, a list of
the signalsconnectedtothe instanceterminals. In addition, the netlist
containsattributeinformation.

5. For Academic Use Only
Presentation Name 5
Mapping

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Presentation Name 6
Placing

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Presentation Name 7
Routing

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Presentation Name 8
Statictiming analyzer

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Presentation Name 9
Statictiming analyzer

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Presentation Name 10
Statictiming analyzer

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Presentation Name 11
Configuration

12. ISE Software
Flow !"#$%

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Presentation Name 13
Outline
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Presentation Name 14
Foundation Series ISE
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Presentation Name 15
Translate
Map
Place & Route
Xilinx Design Flow
Plan & Budget
HDL RTL
Simulation Synthesize
to create netlist
Functional
Simulation
Create
Bit File
Attain Timing
Closure
Timing
Simulation
Implement
Create Code/
Schematic

16. For Academic Use Only
Presentation Name 16 Advanced design management
through project navigator
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Presentation Name 17
Processes and Tools

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Step 1:
Design
Step 2:
Synthesize to
create netlist
Step 3:
Implement design
Step 4:
Configuration

18. For Academic Use Only
Presentation Name 18
Context Sensitive Flow

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Presentation Name 19
ISE Push Button Flow
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Presentation Name 20
Design Entry
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Presentation Name 21
Schematic Source File
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Presentation Name 22
Options and Symbols
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Presentation Name 23
HDL Source File
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Presentation Name 24
Xilinx CORE Generator
System GUI
Core type, version,
device support, and
vendor
Cores can be organized by function,
vendor, or device family

25. For Academic Use Only
Presentation Name 25
Core Customize Window
Parameters
tab allows
you to
customize
the core
Contact tab
provides
information
about the
vendor
Data sheet
access
Core Overview tab provides version
information and a brief functional description

26. For Academic Use Only
Presentation Name 26·
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5.1i Synthesis Solutions

27. For Academic Use Only
Presentation Name 27
XST Flow
To Implementation
Tools
Synthesis
Report File
Synthesis
Technology Specific Optimization
Supported Families: Virtex XC9500
Virtex-E XC9500XL
Virtex-II XC9500XV
Virtex-IIPro CoolRunner
Spartan-II CoolRunner-II
Spartan-IIE
Constraints
VHDL
Verilog
.LOG
.NGC
ISE 5.1i
PC & WS

28. For Academic Use Only
Presentation Name 28
XilinxImplementation
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Map
Place & Route
Implement
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Presentation Name 29
What is Implementation?
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Presentation Name 30
Implement
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Presentation Name 31
Download
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32. For Academic Use Only
Presentation Name 32
Program the FPGA
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