Full ARM7 Microprocessor Architecture.pdf

introduction on ARM7 Microprocessor Architecture

1. Prof. Pritesh N. Saxena
EC Department
SCET, SURAT


ARM Architecture

2. A Simple Processor
Program counter
Registers
ALU
Instruction Decoder circuits
Control Logic Unit

3. Level of Abstraction

Abstraction is the process by which data and programs are
defined with a representation similar to its meaning while
hiding away the implementation details.
Typical Hierarchy at hardware level:
Transistors
Logic gates
ALU
Processors
Integrated System

4. Processors
Misconception of computing
Maximum time is wasted to locate
memory and data
Dynamic measurement

5. Typical Dynamic Instruction range

6. The ARM was originally developed at Acorn
Computer Limited of Cambridge, England,
between 1983 and 1985.

The first RISC microprocessor developed for
commercial use

7. Differs from traditional RISC
processor
Control Over ALU and other unit
Auto incremental and decremental mode
Load & store architecture of multiple
data
High Code Density

8. Developed by Advanced RISC Machines
32-bit RISC embedded processor
Low-end ARM core for applications like digital mobile
phones
load/store architecture
ARM Architecture

9. ◊32 bit address and data bus
◊4 byte boundary
◊3-stage pipeline
◊Fetch
◊Instruction is fetched from memory and placed in instruction
pipeline
◊Decode
◊Instruction is decoded and data path is prepared for next
instruction
◊Execute
◊The final execution is completed

10. ARM TDMI
T: in addition to the 32-bit ARM instruction set, also support
16-bit Thumb instructions

D: on-chip Debug support Enable the processor to halt in
response to a debug request

M: an enhanced Multiplier Can yield a full 64-bit result

I: Embedded ICE hardware to give on-chip breakpoint and
watch point support the embedded ICE module introduces
breakpoint and watch point registers that are accessed
using JTAG interface

11. Drawbacks of RISC Processors
Poor code density
Don’t execute X86 codes

12. ARM Processor
Acorn RISC machine
An analogy to Berkeley RISC Design

13. Features Used
A load and store Architecture
Instructions accesses registers only
Fixed length 32 bit instructions
3 address instructions format

14. Features rejected
Registers windows
Berkeley RISC processors used large
numbers of visible register
32 registers were visible
large register window occupy large chip
area
Hence higher cost

15. ARM Block
diagram

16. The barrel shifter, which can shift or rotate one operand by
any number of bits using combinational logic
The ALU, which performs the arithmetic and logic functions
required by the instruction set.
The address register and incrementer , which select and
hold all memory addresses and generate sequential
addresses when required.
The data registers, which hold data passing to and from
memory.
The instruction decoder and associated control logic.

17. A barrel shifter is wired so you can move bits from any
position to any position in a single clock. It takes a lot of
gates. A regular shifter moves bits right or left one position
in one clock.
A barrel shifter uses multiplexer for its operation while
normal shift registers uses Flip flops