Fundamentals of Electrons - Latches FlipFlop

Examples are: Adders, subtractors, comparators, decoders, encoders, and multiplexers.
• These components are available in integrated circuits as medium-scale integration (MSI) circuits.
• The analysis of a combinational circuit requires that we determine the function that the circuit
implements.

1. Fundamentals of Electronics
ECN 102

2. •Examples are: Adders, subtractors, comparators, decoders, encoders, and multiplexers.
•These components are available in integrated circuits as medium-scale integration (MSI) circuits.
•The analysis of a combinational circuit requires that we determine the function that the circuit
implements.
•This task starts with a given logic diagram and culminates with a set of Boolean functions, a truth table,
or, possibly, an explanation of the circuit operation.
•The diagram of a combinational circuit has logic gates with no feedback paths or memory elements .
•A feedback path is a connection from the output of one gate to the input of a second gate whose output
forms part of the input to the first gate.
•Feedback paths in a digital circuit define a sequential circuit and must be analyzedby special methods
Combinational Circuits

3. Analysis

4. Example:
How to create this circuit?

6. Circuit Implementation

7. Binary Adder and Subtractor
Half AdderA combinational circuit that performs the
addition of two bits is called a half adder .
One that performs the addition of three bits
(two significant bits and a previous carry) is a full
adder .
Needs two binary inputs and two
binary outputs

8. Full Adder

9. How do you implement a full adder with 2 half adders?

10. Binary Adder
Four bitadder

11. Binary Subtractor
/Adder
When M = 0, the circuit is an adder, and when M = 1, the circuit becomes a subtractor.
•The subtraction A -B can be done by taking the 2’s complement of B and adding it
to A
•The 2’s complement can be obtained by taking the 1’s complement and adding 1
to the least significant pair of bits

12. Decimal Adder
BCD Adder
How many inputs and outputs?
Requires a minimum of nine
inputs and five outputs.
Moreover, the ‘BCD sum’ is not
exactly same as the ‘binary sum’
Following condition needs to
satisfy:

13. Circuit level implementation

14. Binary Multiplier

15. Decoders
3-to-8 Decoder
•A binary code of n bits is capable of
representingup to 2ndistinct elements of
coded information.
•A decoder is a combinational circuit that
converts binary information from n input
lines to a maximum of 2nunique output
lines.
•If the n -bit coded information has unused
combinations, the decoder may have fewer
than 2n outputs.

16. Decoders
3-to-8 Decoder2-to-4 decoder with Enable

17. Encoders
Octal-to-Binary Encoder
Performs the inverse operation
of a decoder.

18. Multiplexers
A multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a
single output line
2-to-1 Mux
4-to-1 Mux
Multiplexers may have an Enable inputto control the
operation of the unit.

19. Boolean Function Implementation using MUX
Example:
Example:

21. SEQUENTIAL CIRCUITS
•The new value is stored (i.e., the flip-flop is
updated) when a pulse of the clock signal
occurs.
•Prior to the occurrence of the clock pulse, the
combinational logic forming the next value of
the flip-flop must have reached a stable value.
•Therefore, the speed at which the combinational
logic circuits operate is critical.
•If the clock (synchronizing) pulses arrive at a
regular interval, the combinational logic must
respond to a change in the state of the flip-flop
in time to be updated before the next pulse
arrives.
•Storage elements that operate with signal
levelsare referred to as latches –Level
Sensitive
•Those controlled by a clock transition are
flip-flops –Edge Sensitive

22. LATCHES
SR Latch using NOR gate
Latches are building blocks
flip-flops
1 bit memory
(0,0) is the hold state
A bistable multivibrator
Active high SR latch

23. LATCHES
SR Latch using NAND gate
(1,1) is the hold state
Active low SR latch

24. GATED Latches OR LATCHES with ENABLE

26. D-Latch or GATED D-Latch
1 bit memory device

28. XOR Function
XOR: 3-bits
Odd function

29. XOR ApplicationParity generation and checking
•A parity bit is an extra bit included with a binary message to make the number of 1’s either odd or even.
•Themessage, including the parity bit, is transmitted and then checked at the receiving end for errors.
•An error is detected if the checked parity does not correspond with the one transmitted.
Even-Parity-Generator Truth Table
C will be equal to 1 if an error occurs

30. ‘Clocked’ D-LATCH –Pulsed Latch

33. •If CLR is made Low àQ=0
•IfPREismadeLowàQ=1
For falling edge of the CLK

34. FLIP-FLOPSThe state is changed by an external input –trigger.
The D latch with pulses in its control input is essentially a flip-flop that is triggered every time the
pulse goes to the logic-1 level.
As long asthe pulse input remains at this level, any changes in the data input will change the output
and the state of the latch.
Master-Slave D-type Flip-Flop

35. D-type Flip-Flop
Timing Diagram

36. The J-K Flip-Flop
Alleviates the problem of SR Latches
J-K Latch
Eliminates the possibility of Q and
Q’ to have the same value.

37. The J-K Flip-Flop
Timing Diagram

39. The T Flip-Flop

40. Thank you